CN102347775B

CN102347775B - PLDA (parallel layered decoding algorithm)-based LDPC (low density parity check) decoder

Info

Publication number: CN102347775B
Application number: CN 201110262178
Authority: CN
Inventors: 叶凡; 姚远; 任俊彦; 许俊; 李宁; 李巍
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2011-09-06
Filing date: 2011-09-06
Publication date: 2013-07-10
Anticipated expiration: 2031-09-06
Also published as: CN102347775A

Abstract

The invention belongs to the technical field of designs of integrated circuits and particularly relates to a PLDA (parallel layered decoding algorithm)-based LDPC (low density parity check) decoder. The design of the decoder is based on the PLDA, input data to be decoded is stored in register chains; the decoder has a ping pong structure by using the two register chains, namely when one register chain receives new data to be decoded and simultaneously outputs the decoded data, the other register chain with the data to be decoded is divided into M subchains and carries out decoding operation, wherein the M is equal to the number of arrays of submatrixes in an LDPC check matrix; and each subchain corresponds to an array of submatrixes in the check matrix and stores the data to be decoded corresponding to the array of submatrixes. The LDPC decoder prevents excess storage units from being used in chip designs by using the register chains so as to further reduce the chip area of the PLDA-based decoder and maintain a relatively high decoding rate.

Description

A kind of ldpc code decoder based on the parallel hierarchical decoding algorithm

Technical field

The invention belongs to the integrated circuit (IC) design technical field, be specifically related to a kind of ldpc code decoder based on the parallel hierarchical decoding algorithm.

Background technology

The LDPC sign indicating number receives publicity because of its outstanding error-correcting performance in recent years.Based on the LDPC hierarchical decoder algorithm of minimum sum-product algorithm (Layered Decoding Algorithm, LDA) can describe with following equation:

[1]

[2]

[3]

In the above-mentioned formula, α represents modifying factor, and value is generally about 0.8; Q represents to pass to from variable node the information of check-node; Λ represents the variable node canned data; R represents that check-node passes to the information of variable node.LDA is divided vertically into several layers with the LDPC code check matrix.Each decoding iteration is divided some steps, and one deck that per step is chosen matrix carries out decoded operation.In the decoded operation of each layer correspondence, check-node and variable node are carried out equation [1], [2] and [3], and the very long critical path that therefore causes delaying time.Insert number level production line register in this critical path and cut apart it, then can worsen error performance.Because if Λ value begins to participate in the decoding of certain one deck, so until this layer decoding finish and with this Λ value renewal after, this Λ value could participate in the decoding of other layer again, otherwise error performance will worsen.Suppose that inserting K-1 level production line register in critical path mentioned above cuts apart it, then the L layer needs K clock cycle to finish decoding.Before the L layer was finished decoding, L+1 layer to L+K-1 layer successively began decoding.If certain Λ value of L layer correspondence comes across L+1 layer certain layer to the L+K-1 layer equally, then the L layer finish decoding and with this Λ value renewal before, this Λ value will be admitted to L+1 layer certain layer to the L+K-1 layer.It is more frequent to notice that more big this situation of K value takes place, and it is more serious that error performance worsens.So critical path is difficult to use pipeline register to be cut apart, maximum clock frequency and the decoding rate of decoder are restricted.

K. Zhang in 2009, X. the paper " High-throughput layered decoder implementation for quasi-cyclic LDPC codes " delivered at IEEE J. Sel. Areas Commun. of Huang and Z. Wang has proposed can be applicable to parallel hierarchical decoding algorithm (the Parallel Layered Decoding Algorithm of quasi-cyclic LDPC code, and use among the 802.16e 1/2 code check quasi-cyclic LDPC code to describe PLDA PLDA).This LDPC code check matrix is totally 1152 row, and 2304 row are divided into 12 layers.Every layer 96 row of matrix contains 24 submatrixs.Submatrix size 96 * 96.This check matrix as shown in Figure 1, label is that the submatrix of I represents that this submatrix is that unit matrix ring shift right I forms.PLDA is divided into 96 parts with this check matrix.First is made up of every layer first row, and second portion is made up of every layer second row, and the rest may be inferred by analogy.This 96 part is deciphered one by one in proper order from part 1 to the 96 parts in each decoding iteration.Can be divided into for 96 steps so decipher iteration at every turn, each goes on foot operates one of 96 parts of this matrix, and each clock cycle is carried out a step.Each check-node and variable node are combined into an independent compute node in PLDA.Because each part of matrix comprises 12 row, decoder needs 12 compute node.In a step in each iteration, compute node reads the Λ value from memory cell, and after carrying out equation [1], [2] and [3] the operation described, with the new Λ value that obtains after upgrading, namely new_ Λ sends memory cell back to.

PLDA makes amendment to the LDPC code check matrix that uses.802.16e in modification matrix such as Fig. 2 of 1/2 code rate LDPC code check matrix correspondence.The ring shift right operation that every layer of each non-NULL submatrix in the former check matrix carried out can obtain revising matrix, and the value of every layer of cyclic shift marks the left side in matrix shown in Figure 2.This is revised in the matrix, and the difference of the matrix index of several non-NULL submatrixs of same row is at least 5.Thereby be admitted to after compute node participates in step in the iterative decoding when a Λ value, comprise this decoding step this Λ value within interior 5 decoding steps thereafter and can not be used again.So 4 groups of pipeline registers can insert critical path so far, guarantee that simultaneously the decoding step before it has been finished when a Λ value is sent to compute node operates and is updated.So maximum clock frequency and the decoding rate of decoder are significantly improved.

K. Zhang, X. Huang and Z. Wang had once proposed a kind of concrete decoder hardware design methods based on PLDA in the paper " High-throughput layered decoder implementation for quasi-cyclic LDPC codes " that IEEE J. Sel. Areas Commun. delivers.Each Λ value need be repeated storage for several times in several memory cells in this design, thereby this design needs a large amount of memory cell to store the Λ value.

Summary of the invention

It is few to the objective of the invention is to propose a kind of memory cell, thereby can use less chip area, realizes the ldpc code decoder of higher decoding rate.

The ldpc code decoder that the present invention proposes is based on the decoder of parallel hierarchical decoding algorithm (PLDA).Decoder is stored in chain of registers with the value of Λ among the present invention, and each Λ value only needs storage once, thereby avoids using multiple memory cell, further significantly to reduce the ldpc decoder chip area based on PLDA.

The LDPC that the present invention proposes translates decoder, and based on PLDA, and the data to decode of input is stored in the chain of registers.Decoder uses two such chain of registers (30,31) to form ping-pong structure.Namely when a chain of registers received new data to decode and the data of decoding have been finished in output simultaneously, another chain of registers that contains data to decode was divided into M bar subchain, the row decoding of going forward side by side operation, and M equals the contained submatrix columns of LDPC check matrix; A row submatrix in every corresponding check matrix of subchain, and store the data to decode of this row submatrix correspondence; Carrying out subchain (divide to form by 30 or 31) cyclic shift during deciphering of decoded operation, and be connected and fix with wiring between the compute node (32).

If data to decode uses M1 bit fixed point quantification, code word code length M2 bit to be decoded, and the LDPC check matrix contains M row submatrix, then stores the chain of registers of data to decode and is made up of M1 * M2 register.After chain of registers was divided into M bar subchain, every subchain was by M1 * (M2/M) individual register is formed.A row submatrix in every corresponding check matrix of subchain, and store the data to decode of this row submatrix correspondence.In chain of registers, every M1 register constitutes a memory cell, stores a data to decode.Article one, chain of registers contains M2 memory cell altogether.Divided in the subchain that forms by chain of registers, every M1 register constitutes a memory cell, stores a data to decode.Article one, subchain contains (M2/M) individual memory cell altogether.When subchain participates in decoding, memory cell of each clock cycle ring shift left (or moving to right) of subchain.Guarantee with compute node (32) between wiring be connected and fix.

Description of drawings

Fig. 1 is 1/2 code rate LDPC code check matrix among the 802.16e.

Fig. 2 is the modification matrix of 1/2 code check quasi-cyclic LDPC check matrix among the 802.16e.

The decoder hardware designs based on PLDA that Fig. 3 proposes for the present invention.

Fig. 4 is the associated submatrix of a subchain and, and a compute node.

Fig. 5 is a chain of registers concrete structure, and wherein Λ uses 6 bit quantizations.

Fig. 6 is a subchain concrete structure, and wherein Λ uses 6 bit quantizations.

Number in the figure: the chain of registers of a storage of 30 expressions Λ, this chain of registers is being accepted new data to decode this moment, and the data of decoding have been finished in output simultaneously.The chain of registers of a storage of 31 expressions Λ, this chain of registers is divided into 24 subchains and carries out decoded operation; Chain of registers shown in this chain of registers and the label 30 constitutes ping-pong structure.The 1st subchain of 311 expressions, the 1st row submatrix in the corresponding check matrix.The 2nd subchain of 312 expressions, the 2nd row submatrix in the corresponding check matrix.The 23rd subchain of 3123 expressions, the 23rd row submatrix in the corresponding check matrix.The 24th subchain of 3124 expressions, the 24th row submatrix in the corresponding check matrix.12 compute node of 32 expressions.The 1st compute node of 321 expressions.The 11st compute node of 3211 expressions.The 12nd compute node of 3212 expressions.41 the expression a certain subchain, can be 311 ~ 3124 among any one.42 the expression a certain compute node, can be 321 ~ 3212 among any one.The a certain non-NULL submatrix of 43 expressions.The 1st memory cell in the 51 expression chain of registers is made up of 6 registers.The 2nd memory cell in the 52 expression chain of registers is made up of 6 registers.The 3rd memory cell in the 53 expression chain of registers is made up of 6 registers.The 2302nd memory cell in the 52302 expression chain of registers is made up of 6 registers.The 2303rd memory cell in the 52303 expression chain of registers is made up of 6 registers.The 2304th memory cell in the 52304 expression chain of registers is made up of 6 registers.The 1st memory cell in the 61 expression subchains is made up of 6 registers.The 2nd memory cell in the 62 expression subchains is made up of 6 registers.The 3rd memory cell in the 63 expression subchains is made up of 6 registers.The 94th memory cell in the 694 expression subchains is made up of 6 registers.The 95th memory cell in the 695 expression subchains is made up of 6 registers.The 96th memory cell in the 696 expression subchains is made up of 6 registers.

Embodiment

Further specify the implementation method of circuit below in conjunction with diagram:

Use the LDPC sign indicating number of check matrix correspondence shown in Figure 2 to be example below, describe design of encoder of the present invention.Figure 3 shows that the decoder hardware design structure based on PLDA that the present invention proposes.Check-node and variable node are combined into an independent compute node, totally 12 compute node (32).Each compute node is inserted into 4 groups of pipeline registers and cuts apart this critical path, with the raising system maximum clock frequency of several times.The value of Λ is stored in the chain of registers in the equation [1], and decoder uses two such chain of registers (31), (32) to form ping-pong structure.Every chain contains the value that 2304 register memory cells are stored Λ, and numerical table shows that then each register memory cell needs M register to make up if each Λ value is used the M bit fixed point.When a chain was accepted new data and the data of decoding have been finished in output simultaneously, another chain carried out decoded operation and is divided into 24 subchains (311 ~ 3124), every layer of 24 submatrix in the corresponding check matrix.A row submatrix in every corresponding matrix of subchain, and contain 96 memory cell.

Figure 4 shows that a subchain (41) and an associated non-NULL submatrix (43), and the compute node (42) that the exchanges data relation is arranged with it.Each clock cycle, certain part begins decoding in matrix 96 parts.This part is corresponding some stored Λ values in subchain, and these Λ values are sent to compute node and carry out decoded operation.Once deciphering in two continuous in the iteration steps, the corresponding Λ value of two row continuous in each non-NULL submatrix is sent to compute node.Because all non-NULL submatrixs are to be formed by the unit matrix cyclic shift, therefore with respect to back, need to deliver to unit of the position ring shift right of Λ in subchain of compute node in the current decoding step.In the design of encoder that the present invention proposes, each subchain comprises 96 memory cell, the value of 96 Λ of storage, and unit of every each clock cycle ring shift left of subchain.So sending to as shown in Figure 4, the position of Λ in subchain of arithmetic element in each clock cycle fixes.Each compute node is inserted into 4 groups of pipeline registers and cuts apart this critical path, so send to the position of Λ in subchain of arithmetic element in each clock cycle, 4 units of ring shift left are then for receiving the position of the new _ Λ that is sent here by compute node in the subchain.Thereby the position that receives the new _ Λ that is sent here by compute node in the subchain is also fixing.Therefore, the electric wiring line between compute node and the subchain is fixed.So the memory cell of storage Λ value be connected with the wiring between the compute node be fix and be simplified.

Use the LDPC sign indicating number of check matrix correspondence shown in Figure 2, if the Λ value uses 6 bit fixed point numerical tables to show that then the concrete structure of a chain of registers is seen Fig. 5, the concrete structure of a subchain is seen Fig. 6.Each memory cell is made up of 6 registers among Fig. 5 and Fig. 6.

Claims

1. the ldpc code decoder based on the parallel hierarchical decoding algorithm is characterized in that this design of encoder based on the parallel hierarchical decoding algorithm, and the data to decode of input is stored in the chain of registers; Described decoder uses two chain of registers (30,31) to form ping-pong structure, when chain of registers wherein receives new data to decode and the data of decoding have been finished in output simultaneously, another chain of registers that contains data to decode is divided into M bar subchain, the row decoding of going forward side by side operation, M equals the contained submatrix columns of LDPC check matrix; A row submatrix in every corresponding check matrix of subchain, and store the data to decode of this row submatrix correspondence;

In the described decoder, check-node and variable node are combined into an independent compute node;

In the described decoder, once deciphering in two continuous in the iteration steps, the corresponding Λ value of two row continuous in each non-NULL submatrix is sent to compute node;

In the described decoder, if data to decode uses M1 bit fixed point quantification, code word code length M2 bit to be decoded, and the LDPC check matrix contains M row submatrix, then stores the chain of registers of data to decode and is made up of M1 * M2 register; After chain of registers was divided into M bar subchain, every subchain was by M1 * (M2/M) individual register is formed; In chain of registers, every M1 register constitutes a memory cell, stores a data to decode; Article one, chain of registers contains M2 memory cell altogether; Article one, subchain contains (M2/M) individual memory cell altogether; When subchain participates in decoding, each clock cycle ring shift left of subchain or the memory cell that moves to right, with guarantee with compute node (32) between wiring be connected and fix.

2. ldpc code decoder according to claim 1 is characterized in that carrying out subchain cyclic shift during deciphering of decoded operation, and is connected and fixes with wiring between the compute node (32).