CN102347775A - PLDA (parallel layered decoding algorithm)-based LDPC (low density parity check) decoder - Google Patents

Abstract

The invention belongs to the technical field of integrated circuit design, and in particular relates to an LDPC code decoder based on a parallel layered decoding algorithm. The decoder design is based on a parallel layered decoding algorithm, and the input data to be decoded is stored in the register chain; the decoder uses two register chains to form a ping-pong structure, that is, when one of the register chains receives a new When the data is decoded and the decoded data is output at the same time, another register chain containing the data to be decoded is divided into M sub-chains and decoded. M is equal to the sub-matrix columns contained in the LDPC check matrix number; each sub-chain corresponds to a column of sub-matrices in the parity check matrix, and stores the data to be decoded corresponding to the column of sub-matrices. The invention avoids using too many storage units in the chip design by using the register chain, thereby further reducing the chip area of the decoder based on the parallel layered decoding algorithm and maintaining a high decoding rate.

Description

A Decoder for LDPC Codes Based on Parallel Layered Decoding Algorithm

technical field

The invention belongs to the technical field of integrated circuit design, and in particular relates to an LDPC code decoder based on a parallel layered decoding algorithm.

Background technique

In recent years, LDPC codes have attracted attention due to their excellent error correction performance. The LDPC layered decoding algorithm (Layered Decoding Algorithm, LDA) based on the minimum sum product algorithm can be described by the following equation:

            [1]

[1]

[2]

[3]

In the above formula, α represents the correction factor, and the value is generally around 0.8; q represents the information passed from the variable node to the check node; Λ represents the information stored in the variable node; r represents the information passed from the check node to the variable node. LDA divides the check matrix of LDPC code into several layers vertically. Each decoding iteration is divided into several steps, and each step selects a layer of the matrix for decoding operation. In the decoding operation corresponding to each layer, check nodes and variable nodes execute equations [1], [2] and [3], and thus lead to critical paths with long delays. Inserting several stages of pipeline registers on this critical path to divide it will deteriorate the bit error performance. Because if a Λ value starts to participate in the decoding of a certain layer, the Λ value cannot participate in the decoding of other layers until the decoding of this layer is completed and the Λ value is updated, otherwise the bit error performance will deteriorate. Assuming that K-1 pipeline registers are inserted into the critical path mentioned above to divide it, then the L-th layer needs K clock cycles to complete the decoding. Before the decoding of the L layer is completed, the L+1 layer to the L+K-1 layer successively start decoding. If a certain Λ value corresponding to the L-th layer also appears in a certain layer from the L+1 layer to the L+K-1 layer, the Λ value will be updated before the decoding is completed and the Λ value is updated at the L-th layer. Send it to a certain floor in the L+1 floor to the L+K-1 floor. Note that the larger the value of K, the more frequently this happens, and the worse the bit error performance is. Therefore, it is difficult to divide the critical path using pipeline registers, and the maximum clock frequency and decoding rate of the decoder are limited.

In 2009, K. Zhang, X. Huang and Z. Wang published the paper "High-throughput layered decoder implementation for quasi-cyclic LDPC codes" on IEEE J. Sel. Areas Commun. Parallel Layered Decoding Algorithm (PLDA), and use the 1/2 code rate quasi-cyclic LDPC code in 802.16e to describe PLDA. The check matrix of the LDPC code has 1152 rows and 2304 columns in total, and is divided into 12 layers. The matrix has 96 rows per layer and contains 24 sub-matrices. Submatrix size 96×96. The parity check matrix is shown in FIG. 1, and the sub-matrix labeled I indicates that the sub-matrix is formed by cyclically shifting the unit matrix to the right by I. PLDA divides the parity check matrix into 96 parts. The first part consists of the first row of each layer, the second part consists of the second row of each layer, and so on. These 96 parts are decoded sequentially from part 1 to part 96 in each decoding iteration. Therefore, each decoding iteration can be divided into 96 steps, each step operates on one of the 96 parts of the matrix, and one step is performed per clock cycle. In PLDA each check node and variable node are combined into a single computing node. Since each part of the matrix contains 12 rows, the decoder needs 12 operation nodes. At one step in each iteration, the operation node reads the Λ value from the storage unit, and after performing the operations described in equations [1], [2] and [3], it updates the obtained new Λ value, That is, new_Λ is sent back to the storage unit.

PLDA modifies the parity check matrix of the LDPC code used. The modified matrix corresponding to the check matrix of the 1/2 code rate LDPC code in 802.16e is shown in Figure 2. The modified matrix can be obtained by performing a cyclic right shift operation on each non-empty sub-matrix of each layer in the original parity check matrix, and the magnitude of the cyclic shift of each layer is marked on the left side of the matrix shown in FIG. 2 . In the modified matrix, the matrix label difference of several non-empty sub-matrices in the same column is at least 5. Therefore, when a Λ value is sent to the computing node to participate in one step of iterative decoding, the Λ value will not be used again within the next 5 decoding steps including this decoding step. Therefore, 4 sets of pipeline registers can be inserted into this critical path, while ensuring that when a Λ value is sent to the operation node, it has completed the previous decoding step operation and is updated. Therefore, the maximum clock frequency and decoding rate of the decoder have been significantly improved.

K. Zhang, X. Huang and Z. Wang proposed a specific decoding based on PLDA in the paper "High-throughput layered decoder implementation for quasi-cyclic LDPC codes" published on IEEE J. Sel. Areas Commun. Device hardware design method. In this design, each Λ value needs to be repeatedly stored several times in several memory cells, so this design requires a large number of memory cells to store the Λ value.

Contents of the invention

The purpose of the present invention is to propose an LDPC code decoder which has less memory units, thus can use a smaller chip area and achieve a higher decoding rate.

The LDPC code decoder proposed by the present invention is a decoder based on the Parallel Layered Decoding Algorithm (PLDA). In the present invention, the decoder stores the value of Λ in the register chain, and each value of Λ only needs to be stored once, thereby avoiding the use of too many storage units, and further significantly reducing the chip area of the LDPC decoder based on PLDA. the

The LDPC decoder proposed by the present invention is based on PLDA, and the input data to be decoded is stored in the register chain. The decoder uses two such register chains (30, 31) to form a ping-pong structure. That is, when a register chain receives new data to be decoded and outputs the decoded data at the same time, the other register chain containing data to be decoded is divided into M sub-chains and performs decoding operations. M is equal to LDPC calibration The number of sub-matrix columns contained in the verification matrix; each sub-chain corresponds to a column of sub-matrix in the verification matrix, and stores the data to be decoded corresponding to this sub-matrix; the sub-chain (divided by 30 or 31) that is being decoded The circular shift is performed during decoding, and the wiring connection with the operation node (32) is fixed.

If the data to be decoded is quantized using M1 ratio specific points, the length of the code word to be decoded is M2 bits, and the LDPC check matrix contains M columns of sub-matrices, then the register chain storing the data to be decoded consists of M1×M2 registers. After the register chain is divided into M sub-chains, each sub-chain is composed of M1×(M2/M) registers. Each sub-chain corresponds to a column of sub-matrices in the parity check matrix, and stores data to be decoded corresponding to the column of sub-matrices. In the register chain, every M1 register constitutes a storage unit, which stores a piece of data to be decoded. A register chain contains M2 storage units in total. In the sub-chains divided by the register chain, every M1 registers form a storage unit, which stores a piece of data to be decoded. A sub-chain contains (M2/M) storage units in total. When the sub-chain participates in decoding, the sub-chain rotates left (or right) one storage unit per clock cycle. To ensure that the wiring connection with the computing node (32) is fixed.

Description of drawings

Figure 1 is a 1/2 code rate LDPC code parity check matrix in 802.16e.

Fig. 2 is the modification matrix of the 1/2 code rate quasi-cyclic LDPC parity check matrix in 802.16e.

Fig. 3 is the decoder hardware design based on PLDA proposed by the present invention.

Figure 4 shows a sub-chain, a related sub-matrix, and an operation node.

Fig. 5 is a specific structure of a register chain, where Λ is quantized with 6 bits.

Fig. 6 is a specific structure of a sub-chain, where Λ is quantized with 6 bits.

The reference number in the figure: 30 represents a register chain storing Λ, which is accepting new data to be decoded and outputting the decoded data at the same time. 31 represents a register chain storing Λ, which is divided into 24 sub-chains for decoding operation; this register chain and the register chain shown by label 30 form a ping-pong structure. 311 represents the first sub-chain, which corresponds to the first column of the sub-matrix in the parity check matrix. 312 represents the second sub-chain, corresponding to the second sub-matrix in the parity check matrix. 3123 represents the 23rd sub-chain, which corresponds to the 23rd column of the sub-matrix in the parity check matrix. 3124 represents the 24th sub-chain, which corresponds to the 24th column of the sub-matrix in the parity check matrix. 32 represents 12 computing nodes. 321 represents the first computing node. 3211 represents the eleventh computing node. 3212 represents the twelfth computing node. 41 represents a certain subchain, which can be any one of 311~3124. 42 represents a certain computing node, which can be any one of 321~3212. 43 represents a certain non-empty sub-matrix. 51 represents the first storage unit in the register chain, which consists of 6 registers. 52 represents the second storage unit in the register chain, consisting of 6 registers. 53 represents the third storage unit in the register chain, which consists of 6 registers. 52302 represents the 2302nd storage unit in the register chain, which consists of 6 registers. 52303 represents the 2303rd storage unit in the register chain, which consists of 6 registers. 52304 represents the 2304th storage unit in the register chain, which consists of 6 registers. 61 represents the first storage unit in the sub-chain, consisting of 6 registers. 62 represents the second storage unit in the sub-chain, consisting of 6 registers. 63 represents the third storage unit in the sub-chain, consisting of 6 registers. 694 represents the 94th storage unit in the sub-chain, consisting of 6 registers. 695 represents the 95th storage unit in the sub-chain, consisting of 6 registers. 696 represents the 96th storage unit in the sub-chain, consisting of 6 registers.

Detailed ways

The implementation method of the circuit will be further explained in conjunction with the diagram below:

The following uses the LDPC code corresponding to the parity check matrix shown in FIG. 2 as an example to describe the decoder design of the present invention. Fig. 3 shows the hardware design structure of the decoder based on PLDA proposed by the present invention. The check node and the variable node are combined into a single computing node, and there are 12 computing nodes (32) in total. Each computing node is inserted into 4 sets of pipeline registers to divide this critical path and increase the maximum clock frequency of the system several times. The value of Λ in equation [1] is stored in the register chain, and the decoder uses two such register chains (31), (32) to form a ping-pong structure. Each chain contains 2304 register storage units to store the value of Λ, if each value of Λ is represented by M ratio specific points, then each register storage unit needs M registers to construct. When one chain accepts new data and outputs decoded data at the same time, the other chain performs the decoding operation and is divided into 24 sub-chains (311~3124), corresponding to 24 sub-matrices in each layer of the parity check matrix. Each sub-chain corresponds to a sub-matrix in the matrix and contains 96 storage units.

Fig. 4 shows a sub-chain (41), a non-empty sub-matrix (43) related thereto, and an operation node (42) having a data exchange relationship with it. Each clock cycle, one of the parts of the matrix 96 starts to decode. This part corresponds to several stored Λ values in the sub-chain, and these Λ values are sent to the computing node for decoding operation. In two consecutive steps in one decoding iteration, the Λ values corresponding to two consecutive rows in each non-empty sub-matrix are sent to the operation node. Since all non-empty sub-matrices are formed by cyclic shifting of the identity matrix, compared with the previous step, the position of Λ that needs to be sent to the operation node in the current decoding step in the sub-chain is cyclically shifted to the right by one unit. In the decoder design proposed by the present invention, each sub-chain contains 96 storage units, storing 96 values of Λ, and each sub-chain is shifted to the left by one unit per clock cycle. Therefore, as shown in Fig. 4, the position of Λ sent to the operation unit in each clock cycle in the sub-chain is fixed. Each computing node is inserted into 4 sets of pipeline registers to divide this critical path. Therefore, the position of Λ sent to the computing unit in each clock cycle in the sub-chain is shifted to the left by 4 units in a cycle, and it is the position received by the computing unit in the sub-chain. The position of the new _Λ sent by the node. Therefore, the position of receiving the new _Λ sent by the operation node in the sub-chain is also fixed. Therefore, the electrical wiring connections between computing nodes and sub-chains are fixed. Therefore, the wiring connection between the storage unit storing the Λ value and the computing node is fixed and simplified.

Using the LDPC code corresponding to the parity check matrix shown in Figure 2, if the Λ value is represented by 6-bit specific points, the specific structure of a register chain is shown in Figure 5, and the specific structure of a sub-chain is shown in Figure 6. Each storage unit in Fig. 5 and Fig. 6 is composed of 6 registers.

Claims (3)

1. A LDPC code decoder based on a parallel layered decoding algorithm, characterized in that the decoder design is based on a parallel layered decoding algorithm, and the input data to be decoded is stored in the register chain; The encoder uses two register chains (30, 31) to form a ping-pong structure. When one of the register chains receives new data to be decoded and simultaneously outputs the decoded data, the other register chain contains the registers of the data to be decoded. The chain is divided into M sub-chains, and the decoding operation is performed. M is equal to the number of sub-matrix columns contained in the LDPC check matrix; each sub-chain corresponds to a sub-matrix in the check matrix, and stores the data to be decoded corresponding to the column sub-matrix . 2. The LDPC code decoder according to claim 1, characterized in that the subchain undergoing decoding operation is cyclically shifted during decoding, and the wiring connection with the operation node (32) is fixed. 3. LDPC code decoder according to claim 1, is characterized in that if the data to be decoded uses M1 to quantify than a specific point, the length of the code word to be decoded is M2 bits, and the LDPC parity check matrix contains M column sub-matrixes, Then the register chain storing the data to be decoded is composed of M1×M2 registers; after the register chain is divided into M sub-chains, each sub-chain is composed of M1×(M2/M) registers; in the register chain, every M1 register Constitute a storage unit to store a piece of data to be decoded; a register chain contains M2 storage units in total; in the sub-chains divided by the register chain, each M1 register constitutes a storage unit to store a piece of data to be decoded, and a The sub-chain contains a total of (M2/M) storage units; when the sub-chain participates in decoding, the sub-chain moves one storage unit to the left or right in each clock cycle cycle to ensure the wiring connection with the computing node (32) It is fixed.

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