CN102347332A - Three-dimensional multivalue nonvolatile memory structure - Google Patents
Three-dimensional multivalue nonvolatile memory structure Download PDFInfo
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- CN102347332A CN102347332A CN2010102420038A CN201010242003A CN102347332A CN 102347332 A CN102347332 A CN 102347332A CN 2010102420038 A CN2010102420038 A CN 2010102420038A CN 201010242003 A CN201010242003 A CN 201010242003A CN 102347332 A CN102347332 A CN 102347332A
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Abstract
The invention discloses a three-dimensional multivalue nonvolatile memory structure, which comprises Fin structures, a tunneling dielectric layer, a charge capture layer and a charge barrier layer, and periodic source and drain regions, wherein the Fin structures are connected with a semiconductor substrate; the tunneling dielectric layer, the charge capture layer and the charge barrier layer are formed on the side walls of the Fin structures sequentially; the periodic source and drain regions are formed on the Fin structures; control grid electrodes are exported from a position between adjacent Fin structures; and the grid electrodes in a vertical direction are isolated by the dielectric layer, and sources and drains are exported from the tops of the Fin structures, so three-dimensional integration can be formed. The three-dimensional multivalue nonvolatile memory structure is high in density and easy to integrate and can be implemented by adopting the conventional memory manufacturing process; and popularization and application of the three-dimensional multivalue nonvolatile memory structure is facilitated.
Description
Technical field
The present invention relates to microelectronics manufacturing and memory technology field, relate in particular to a kind of many-valued nonvolatile memory structure with three-dimensional integrated characteristic, localization stored charge.
Background technology
Present microelectronic product mainly is divided into logical device and memory device two big classes, and all need use memory device in nearly all now electronic product, thereby memory device occupies important status at microelectronic.Memory device generally can be divided into volatile storage and nonvolatile memory.The main feature of non-volatility memorizer is under situation about not powering up, also can keep canned data for a long time.The characteristics of its existing read-only memory (ROM) have very high access speed again, and are easy to wipe and rewrite, and power consumption is less.Along with the needs to big capacity, low-power consumption storage such as multimedia application, mobile communication; Non-volatility memorizer; Flash memory (Flash) particularly, the market share of shared semiconductor device becomes increasing, also more and more becomes a kind of considerable type of memory.
Traditional Flash memory is the silica-based nonvolatile memory that adopts the polysilicon membrane floating gate structure, and a defective on the device tunneling medium layer (generally being oxide layer) promptly can form fatal discharge channel.The charge trap-type memory utilizes electric charge localization characteristic stored in the capture layer, realizes discrete charge storage, and the defective on the tunneling medium layer only can cause local electric charge to leak, and makes electric charge keep more stable like this.What is more important is utilized this electric charge localization storage characteristics, can in individual devices, realize a plurality of relatively independent physical store points, thereby realize many-valued storage, fundamentally improves storage density.Traditional Flash memory adopts planar structure, and the Fin structure memory can effectively utilize the side wall surface, forms vertical-channel, increases channel area, thereby obtains more excellent device performance.Existing Fin structure fields effect transistor memory adopts the SOI substrate more, and the Fin structure of preparing is different with backing material, and influence is to the control of CMOS transistor threshold voltage.
Fast development along with microelectric technique; Size of semiconductor device is further scaled; Except to the programming of nonvolatile memory, wipe, keep performance demands improves constantly, thereby realize that the high density storage obtains lower cost and becomes the developing emphasis of nonvolatile memory.Three-dimensional integrated technology is one of effective ways that improve storage density.The patent No. is that the patent of US5825296 has been described a kind of three-dimensional structure read-only memory.The patent No. is that the patent of US20080023747 discloses formation and the preparation method based on the semiconductor storage unit array of many laminated construction.The storage array storage density all has the space that can further improve described in the above patent.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of three-dimensional many-valued nonvolatile memory structure, with the raising storage density, and the multivalued storage that obtained performance is excellent, and can be compatible mutually with conventional silicon planar CMOS technology, reduce cost, be beneficial to extensive use.
(2) technical scheme
For achieving the above object, the invention provides the many-valued nonvolatile memory structure of a kind of three-dimensional, comprising:
The Fin structure that links to each other with Semiconductor substrate;
The tunneling medium layer, electric charge capture layer and the electric charge barrier layer that on the Fin structure side wall, form successively;
At the structrural build up periodic source and drain areas of Fin;
In the middle of adjacent Fin structure, draw control grid electrode, isolated by dielectric layer between gate electrode on the vertical direction, source-drain electrode is drawn by the Fin structural top, forms three-dimensional integrated.
In the such scheme, said Semiconductor substrate is silicon chip or germanium silicon chip.
In the such scheme, said Fin structure forms on substrate, and its material is identical with backing material or by the material of substrate epitaxial.
In the such scheme, be filled with isolated material between the said Fin structure, this isolated material adopts silicon dioxide.
In the such scheme, said tunneling medium layer material is silicon dioxide, high dielectric constant material or is piled up the structure that forms by multilayer material.
In the such scheme, said electric charge capture layer material is silicon nitride, high dielectric constant material or nanocrystalline material.
In the such scheme, said electric charge barrier layer material is silicon dioxide, high dielectric constant material or is piled up the structure that forms by multilayer material.
In the such scheme, said source and drain areas forms by mixing near the Fin body structure surface, and dopant type is opposite with substrate type.
In the such scheme, the doping condition of said source and drain areas is all identical, forms the source and drain areas of symmetry, and along Fin structure length direction periodic distribution.
In the such scheme, said control grid electrode on the substrate dielectric layer, joins with the electric charge barrier layer of Fin structural outside layers between adjacent Fin structure, and electrode material is polysilicon, metal, metal silicide or is piled up the structure that forms by multilayer material.
In the such scheme, said buffer layer plays a part to isolate between adjacent control grid electrode layer, adopts earth silicon material.
In the such scheme, said source-drain electrode is formed on the source and drain areas that mixes by the Fin structural top and draws, and electrode material is polysilicon, metal, metal silicide or is piled up the structure that forms by multilayer material.
(3) beneficial effect
Can find out that from technique scheme the present invention has following beneficial effect:
The many-valued nonvolatile memory structure of three-dimensional provided by the invention; The character of electric charge localization storage in the electric charge capture layer and the spatial character of Fin structure have been fully utilized; In individual devices, obtain a plurality of physical store points; Realize many-valued storage; It is integrated on memory device array, to form three-dimensional, thereby has fundamentally improved storage density.Simultaneously memory of the present invention can obtain more excellent programming, wipe, device performance such as maintenance.Many-valued nonvolatile memory preparation technology of charge trap-type of the present invention and conventional silicon planar CMOS process compatible can adopt the legacy memory array structure integrated, are beneficial to extensive use.
Description of drawings
Fig. 1 to Fig. 6 is the flow chart according to the three-dimensional many-valued nonvolatile memory structure of preparation of the embodiment of the invention;
Fig. 7 is the circuit diagram of overlooking of the many-valued nonvolatile memory structure of three-dimensional provided by the invention;
Fig. 8 is the forward sight circuit diagram of the many-valued nonvolatile memory structure of three-dimensional provided by the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
The many-valued nonvolatile memory structure of three-dimensional provided by the invention; Characteristic based on the electric charge local storage; Has stereochemical structure; Each unit has four physical store points; Thereby realize many-valued characteristic stored; Based on the stereochemical structure of individual devices, can realize that the memory array three-dimensional is integrated, thereby increase substantially storage density.This structure specifically comprises: the Fin structure that links to each other with Semiconductor substrate; The tunneling medium layer, electric charge capture layer and the electric charge barrier layer that on the Fin structure side wall, form successively; At the structrural build up periodic source and drain areas of Fin; In the middle of adjacent Fin structure, draw control grid electrode, isolated by dielectric layer between gate electrode on the vertical direction, source-drain electrode is drawn by the Fin structural top, forms three-dimensional integrated.
Wherein, said Semiconductor substrate is silicon chip or germanium silicon chip.Said Fin structure forms on substrate, and its material is identical with backing material or by the material of substrate epitaxial.Be filled with isolated material between the said Fin structure, this isolated material adopts silicon dioxide.Said tunneling medium layer material is silicon dioxide, high dielectric constant material or is piled up the structure that forms by multilayer material.Said electric charge capture layer material is silicon nitride, high dielectric constant material or nanocrystalline material.Said electric charge barrier layer material is silicon dioxide, high dielectric constant material or is piled up the structure that forms by multilayer material.Said source and drain areas forms by mixing near the Fin body structure surface, and dopant type is opposite with substrate type.The doping condition of said source and drain areas is all identical, forms the source and drain areas of symmetry, and along Fin structure length direction periodic distribution.Said control grid electrode on the substrate dielectric layer, joins with the electric charge barrier layer of Fin structural outside layers between adjacent Fin structure, and electrode material is polysilicon, metal, metal silicide or is piled up the structure that forms by multilayer material.Said buffer layer plays a part to isolate between adjacent control grid electrode layer, adopts earth silicon material.Said source-drain electrode is formed on the source and drain areas that mixes by the Fin structural top and draws, and electrode material is polysilicon, metal, metal silicide or is piled up the structure that forms by multilayer material.
Fig. 1 to Fig. 6 is the flow chart according to the three-dimensional many-valued nonvolatile memory structure of preparation of the embodiment of the invention.Fig. 1 is the process that forms the Fin structure in the present embodiment. Vertical Fin structure 102a and 102b, polycrystalline substance 101 all belong to Semiconductor substrate 110.Semiconductor substrate 110 is silicon chip, germanium silicon chip, other similar semi-conducting materials or the MULTILAYER SUBSTRATE material that comprises silicon epitaxial layers, germanium silicon layer.The technology that forms the Fin structure comprises and forms the method that etching or epitaxial growth etc. behind the hardmask can form vertical Fin shape structure.The variation of Fin structure dimension can realize through the technology adjustment.Fill separator 103 between the Fin structure and adopt depositing technics, material is that silicon dioxide or other have the material of similarity.Signal forms two Fin structures among this figure, and a plurality of Fin structures of preparation form array in the actual process.
Fig. 2 is the process that on the Fin structure side wall, forms tunneling medium layer, electric charge capture layer, electric charge barrier layer in the present embodiment successively.201a and 201b; 202a and 202b lay respectively at Fin structure 102a; The 102b both sides; Be followed successively by tunneling medium layer from the inside to the outside; Electric charge capture layer; Electric charge barrier layer; Wherein the tunneling medium layer material is a silicon dioxide; High-k (high-k) material or pile up structure by multilayer material with similarity; The electric charge capture layer material is a silicon nitride; The high-k material; Nanocrystalline material or other have the material of similarity, and the electric charge barrier layer material is a silicon dioxide; The high-k material; Other has the material of similarity or is piled up the structure with similarity by multilayer material.
Fig. 3 is the process that forms doped region 301 in the present embodiment.Doped region 301 is near Fin body structure surface place, and dopant type is opposite with substrate.Along X1 direction doped region 301 periodic distribution, promptly formed symmetrical source and drain areas.Signal has formed the doped region in two cycles among this figure, forms the doped region that series of periodic distributes along the X1 direction in the actual process.
Fig. 4 is the process that forms gate electrode 401 in the present embodiment.Control grid electrode on the substrate dielectric separator 103, joins with the electric charge barrier layer of Fin structural outside layers between adjacent Fin structure.Electrode material is polysilicon, metal, metal silicide or is piled up the structure with similarity by multilayer material.Illustrated the control grid electrode layer of three parallel arrangements between X2 direction Fin structure, can form a series of control grid electrode arrays in the actual process among this figure.
Fig. 5 is the process that forms three-dimensional stacked gate electrode in the present embodiment.401 deposits of ground floor gate electrode form ground floor spacer medium layer 501, form second layer control grid electrode layer 502, second layer spacer medium layer 503, the 3rd layer of control grid electrode layer 504, the 3rd layer of spacer medium layer 505 successively.Electrode material is polysilicon, metal, metal silicide or is piled up the structure with similarity by multilayer material.The spacer medium layer material is that silicon dioxide or other have the material that can play electrode zone isolation character.Illustrated three layers of control grid electrode layer among this figure, the control grid electrode layer piles up number and can adjust design according to Fin structure height, gate electrode layer thickness, grid zone isolation thickness of dielectric layers in the actual process, is not limited to three layers.
Fig. 6 is the process of source-drain electrode layer 602 in the present embodiment.Spacer medium layer 601 is between device and source-drain electrode layer, and material is that silicon dioxide or other have the material that can play electrode and device zone isolation character.Source-drain electrode is drawn by Fin structural top doped region, and linking to each other along the X2 direction forms electrode layer 602.Electrode material is polysilicon, metal, metal silicide or is piled up the structure with similarity by multilayer material.Illustrated two source-drain electrode layers among this figure, the source-drain electrode layer is the period profile array structure in the actual process on the X1 direction.
Fig. 7 overlooks electrical block diagram for the many-valued nonvolatile memory of three-dimensional provided by the invention.Illustrated four word lines and four bit lines among the figure, the number of word line and bit line is not limited only to four in the actual array.
Fig. 8 is the many-valued nonvolatile memory forward sight of a three-dimensional provided by the invention structural representation.Word line forms and piles up between adjacent Fin structure, and its periphery circuit design has ripe solution.Illustrated three layers of word line stacks among the figure, piled up the number of plies in the actual array configuration and be not limited only to three layers.
From the above; In an embodiment of the present invention; The character of electric charge localization storage in the electric charge capture layer and the spatial character of Fin structure have been fully utilized; In individual devices, obtain a plurality of physical store points; Realize many-valued storage; It is integrated on memory device array, to form three-dimensional, thereby has fundamentally improved storage density.Simultaneously memory of the present invention can obtain more excellent programming, wipe, device performance such as maintenance.Many-valued nonvolatile memory preparation technology of charge trap-type of the present invention and conventional silicon planar CMOS process compatible can adopt the legacy memory array structure integrated, are beneficial to extensive use.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain; Institute is understood that; The above only is a specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. the many-valued nonvolatile memory structure of three-dimensional is characterized in that, comprising:
The Fin structure that links to each other with Semiconductor substrate;
The tunneling medium layer, electric charge capture layer and the electric charge barrier layer that on the Fin structure side wall, form successively;
At the structrural build up periodic source and drain areas of Fin;
In the middle of adjacent Fin structure, draw control grid electrode, isolated by dielectric layer between gate electrode on the vertical direction, source-drain electrode is drawn by the Fin structural top, forms three-dimensional integrated.
2. the many-valued nonvolatile memory structure of three-dimensional according to claim 1 is characterized in that, said Semiconductor substrate is silicon chip or germanium silicon chip.
3. the many-valued nonvolatile memory structure of three-dimensional according to claim 1 is characterized in that said Fin structure forms on substrate, its material is identical with backing material or by the material of substrate epitaxial.
4. the many-valued nonvolatile memory structure of three-dimensional according to claim 1 is characterized in that, is filled with isolated material between the said Fin structure, and this isolated material adopts silicon dioxide.
5. the many-valued nonvolatile memory structure of three-dimensional according to claim 1 is characterized in that, said tunneling medium layer material is silicon dioxide, high dielectric constant material or is piled up the structure that forms by multilayer material.
6. the many-valued nonvolatile memory structure of three-dimensional according to claim 1 is characterized in that said electric charge capture layer material is silicon nitride, high dielectric constant material or nanocrystalline material.
7. the many-valued nonvolatile memory structure of three-dimensional according to claim 1 is characterized in that, said electric charge barrier layer material is silicon dioxide, high dielectric constant material or is piled up the structure that forms by multilayer material.
8. the many-valued nonvolatile memory structure of three-dimensional according to claim 1 is characterized in that, said source and drain areas forms by mixing near the Fin body structure surface, and dopant type is opposite with substrate type.
9. the many-valued nonvolatile memory structure of three-dimensional according to claim 1 is characterized in that the doping condition of said source and drain areas is all identical, forms the source and drain areas of symmetry, and along Fin structure length direction periodic distribution.
10. the many-valued nonvolatile memory structure of three-dimensional according to claim 1; It is characterized in that; Said control grid electrode is between adjacent Fin structure; On the substrate dielectric layer; Join with the electric charge barrier layer of Fin structural outside layers, electrode material is polysilicon, metal, metal silicide or is piled up the structure that forms by multilayer material.
11. the many-valued nonvolatile memory structure of three-dimensional according to claim 1 is characterized in that, said buffer layer plays a part to isolate between adjacent control grid electrode layer, adopts earth silicon material.
12. the many-valued nonvolatile memory structure of three-dimensional according to claim 1; It is characterized in that; Said source-drain electrode is formed on the source and drain areas that mixes by the Fin structural top and draws, and electrode material is polysilicon, metal, metal silicide or is piled up the structure that forms by multilayer material.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298785A (en) * | 2015-05-29 | 2017-01-04 | 旺宏电子股份有限公司 | Semiconductor device and manufacture method thereof |
| CN108417709A (en) * | 2018-02-05 | 2018-08-17 | 复旦大学 | A kind of device cell and operating method integrating multilevel storage and logical operation |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100163968A1 (en) * | 2008-12-31 | 2010-07-01 | Samsung Electronics Co., Ltd. | Semiconductor memory device having insulation patterns and cell gate patterns |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20100163968A1 (en) * | 2008-12-31 | 2010-07-01 | Samsung Electronics Co., Ltd. | Semiconductor memory device having insulation patterns and cell gate patterns |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298785A (en) * | 2015-05-29 | 2017-01-04 | 旺宏电子股份有限公司 | Semiconductor device and manufacture method thereof |
| CN106298785B (en) * | 2015-05-29 | 2019-07-05 | 旺宏电子股份有限公司 | Semiconductor device and its manufacturing method |
| CN108417709A (en) * | 2018-02-05 | 2018-08-17 | 复旦大学 | A kind of device cell and operating method integrating multilevel storage and logical operation |
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Application publication date: 20120208 |