CN103165613A - Semiconductor memory and manufacturing method of the same - Google Patents
Semiconductor memory and manufacturing method of the same Download PDFInfo
- Publication number
- CN103165613A CN103165613A CN2011104128119A CN201110412811A CN103165613A CN 103165613 A CN103165613 A CN 103165613A CN 2011104128119 A CN2011104128119 A CN 2011104128119A CN 201110412811 A CN201110412811 A CN 201110412811A CN 103165613 A CN103165613 A CN 103165613A
- Authority
- CN
- China
- Prior art keywords
- substrate
- type
- dimensional
- raceway groove
- electric charge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
An embodiment of the invention discloses a semiconductor memory device which is a memory unit in a NOR-type flash memory array. The memory unit comprises a substrate, a three-dimensional channel on the substrate and a charge-capturing-type memory stack layer covering the surface of the three-dimensional channel. The charge-capturing-type memory stack layer comprises a tunneling layer, a charge storage layer, a blocking layer and a gate electrode covering the charge-capturing-type memory stack layer. The three-dimensional channel is adopted in the memory unit, and when the area of the memory unit is further reduced, big channel current can still be provided by the three-dimensional channel. In addition, the structure of the charge-capturing-type memory stack layer solves the problem that the size of the structure of a floating gate is hard to reduce.
Description
Technical field
The present invention relates to semiconductor and manufacturing technology, more particularly, relate to a kind of semiconductor memory and manufacture method thereof.
Background technology
Popular along with the Portable personal device, demand to memory further increases, the research of memory technology is become the important directions of information technology research, in order to improve better the reliability of storage density and data storage, Research Emphasis mainly concentrates on non-volatility memorizer gradually.NOR type flash memory is a kind of non-volatility memorizer commonly used, and it has characteristics at a high speed, is generally used in mobile phone and communication chip, as the storage of code.
common NOR type flash memory mostly is the structure of multi-crystal silicon floating bar, as depicted in figs. 1 and 2, Fig. 1 is the domain schematic diagram of the storage array of conventional NOR type floating gate flash memory, Fig. 2 is the schematic diagram of memory cell BB ' direction, the storage array of NOR type floating gate flash memory forms storage array by a plurality of memory cell 100, at word line (WL, word line) direction is grid stacking 102, stacking 102 both sides of grid are source-drain area 104, grid stacking 102 comprise floating boom (floating gate) 102-1 of polysilicon, inter polysilicon dielectric layer (IPD, Inter-Poly Delectric) control gate of 102-2 and polysilicon (contorl gate) 102-3, on a WL, the grid of memory cell 100 connects together, separate by isolating 106 between memory cell channels.For NOR type floating gate flash memory take the floating boom of polysilicon as memory node, be that the principle that channel hot electron injects is stored, grow at grid (AA ' direction) when constantly reducing, can there be serious short-channel effect, therefore, reducing of NOR type floating gate flash memory memory cell area, mainly the grid width by reducing memory cell 100 (BB ' direction) realizes.
Yet, grid width reduce to mean reducing of channel width, and the electric current of raceway groove is directly proportional with channel width, reduce grid width for the area that reduces memory cell, can make channel current also reduce, thereby cause the decline of device drive ability, affect the readwrite performance of device, for existing structure, be difficult to realize simultaneously the increase with channel current of reducing of NOR type floating gate flash memory memory cell area, and for the floating gate structure of polysilicon, because its thickness is larger, also be difficult to further scaled size.
Summary of the invention
The embodiment of the present invention provides a kind of semiconductor memory, can improve large channel current.
For achieving the above object, the embodiment of the present invention provides following technical scheme:
A kind of semiconductor memory, the memory cell in NOR type flash memory storage array comprises:
Substrate;
Three-dimensional raceway groove on substrate;
Cover the electric charge capture formula storage layer stack of three-dimensional channel surface, described electric charge capture formula storage layer stack comprises tunnel layer, charge storage layer, barrier layer, and the gate electrode that covers electric charge capture formula storage layer stack.
Alternatively, described three-dimensional raceway groove is fin type, Ω type or nanowire-type.
Alternatively, described tunnel layer is SiO
2, SiON, high K medium material or their combination.
Alternatively, described charge storage layer is thin floating boom storage medium or electric charge capture storage medium.
Alternatively, described barrier layer is SiO
2, Si
3N
4, Al
2O
3, high K medium material or their combination.
According to a further aspect in the invention, also proposed a kind of manufacture method of semiconductor memory, described device is the memory cell in NOR type flash memory storage array, comprising:
Substrate is provided;
Form three-dimensional raceway groove on described substrate;
Cover three-dimensional channel surface with form electric charge capture formula storage layer stack with and on gate electrode, described electric charge capture formula storage layer stack comprises tunnel layer, charge storage layer and barrier layer.
Alternatively, described three-dimensional raceway groove is fin type, Ω type or nanowire-type.
Alternatively, the step of the three-dimensional raceway groove of the described fin type of formation is:
The described substrate of etching is also filled, and forms isolated area in substrate;
Described isolated area is returned quarter, expose the sidewall of the substrate between described isolated area, to form the three-dimensional raceway groove of fin type.
Compared with prior art, technique scheme has the following advantages:
The semiconductor memory of the embodiment of the present invention, be the memory cell in NOR type flash memory storage array, adopt three-dimensional raceway groove in its memory cell, when the area of memory cell further reduces, three-dimensional raceway groove still can provide large channel current, and by adopting electric charge capture formula storage layer stack structure to solve the problem that floating gate structure is difficult to further minification.
Description of drawings
Shown in accompanying drawing, above-mentioned and other purpose of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
Fig. 1 is the schematic diagram of the NOR type flash memory storage array domain of routine;
Fig. 2 has the BB ' of memory cell of floating gate structure to schematic cross-section in Fig. 1;
Fig. 3 is the structural representation of the memory of the embodiment of the present invention;
Fig. 4-8 are the manufacture process schematic diagram according to the memory of the embodiment of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when the embodiment of the present invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.
as the description in background technology, in NOR type flash memory storage array, in order to reduce to store area, improve integrated level, owing to there being serious short-channel effect, mainly realize by reducing memory cell grid width, grid width reduce to mean reducing of channel width, and the electric current of raceway groove is directly proportional with channel width, reduce grid width for the area that reduces memory cell, can make channel current also reduce, thereby cause the decline of device drive ability, affect the readwrite performance of device, and for the floating gate structure of polysilicon, because its thickness is larger, also be difficult to further scaled size.
For this reason, the invention provides a kind of semiconductor storage unit, be the memory cell in NOR type flash memory storage array, with reference to shown in Figure 3, comprising: substrate 201; Three-dimensional raceway groove 208 on substrate 201; Cover the electric charge capture formula storage layer stack 202 on three-dimensional raceway groove 208 surfaces, described electric charge capture formula storage layer stack 202 comprises tunnel layer 202-1, charge storage layer 202-2, barrier layer 202-3, and the gate electrode 204 that covers electric charge capture formula storage layer stack 202.
In addition, described semiconductor memory also comprises source-drain area (not shown) and isolated area 206, described source-drain area is arranged in the substrate (substrate of vertical gate cross direction) of lotus trapped type storage layer stack both sides, described isolated area 206 is along the substrate that is arranged in three-dimensional raceway groove 208 both sides, bottom on the grid width direction, and the height of isolated area is lower than the height of three-dimensional raceway groove.
In the present invention, the shape of described three-dimensional raceway groove 208 can be fin type (Fin), Ω type or nanowire-type or other three-dimensional shape.
Wherein, this memory adopts the storage organization of electric charge capture formula, comprises the electric charge capture formula storage layer stack 202 that is comprised of tunnel layer 202-1, charge storage layer 202-2 and barrier layer 202-3.Described tunnel layer 202-1 can be SiO
2, SiON, high K medium material or their combination, described accumulation layer 202-2 can be thin floating boom material, namely adopt the floating boom material of super thin metal layer, lamination such as polysilicon, metal, metal nitride, metal silicide etc., in one embodiment, double-deck for TaN 5 nanometers/Poly 5 nanometers, can be also the electric charge capture storage medium, as silicon nanocrystal, metallic nano crystal, Si
3N
4, HfO
2Deng material, described barrier layer 202-3 can be SiO
2, Si
3N
4, Al
2O
3, the dielectric material such as high K medium material, or their combination, electric charge capture formula storage layer stack 202 for example can be ONO (SiO
2-Si
3N
4-SiO
2) structure ANO (Al
2O
3-Si
3N
4-SiO
2) structure, AHO (Al
2O
3-High K-SiO
2) structure and other similar structures, described High k dielectric material (high K medium material) is AL for example
2O
3, HFO
2, TIO
2, different component the doping such as HfAlO, HfSiO, HfSiON after novel High k dielectric material.
Wherein, described gate electrode 204 can be the electric conducting materials such as polysilicon, metal nitride, metal silicide or metal.
This semiconductor memory is as the memory cell 210 in NOR type flash memory storage array, cross section structure schematic diagram shown in Figure 3 is two the adjacent memory cell 210 on same word line, in one embodiment, described semiconductor memory is the memory cell in the storage array shown in Fig. 1, but the layout of memory cell of the present invention in being not limited to.In this embodiment, on a word line, a plurality of memory cell 210 have been comprised, keep apart by isolated area between the three-dimensional raceway groove that the gate electrode 204 of these memory cell links together, memory cell adopts three-dimensional raceway groove and memory cell, be source-drain area in the substrate of the direction vertical with the word line, on the same straight line, source-drain area is bit line (bitline) direction.
Memory in the present invention has adopted three-dimensional raceway groove, during as the memory cell in NOR type flash memory storage array, three-dimensional raceway groove has more channel surface, as shown in Figure 3, increased the effective length of raceway groove, also guarantee enough channel currents when can reduce on the direction of grid width, in addition, solve by adopting lotus trapped type storage layer stack structure the problem that floating gate structure is difficult to further minification.
Above semiconductor memory of the present invention is described in detail, in order to understand better the present invention, the present invention also provides the manufacture method of above-mentioned memory, is described in detail below with reference to the manufacture method of specific embodiment.
The manufacture method of this semiconductor memory, described device are the memory cell in NOR type flash memory storage array, comprising:
Substrate is provided;
Form three-dimensional raceway groove on described substrate;
Cover three-dimensional channel surface with form electric charge capture formula storage layer stack with and on gate electrode, described electric charge capture formula storage layer stack comprises tunnel layer, charge storage layer and barrier layer.
Below in conjunction with specific embodiment, manufacture method is described in detail.
At first, provide substrate 201, with reference to figure 4.
In this embodiment, described Semiconductor substrate 201 is the Si substrate.In other embodiments, described Semiconductor substrate can also include but not limited to other elemental semiconductors or compound semiconductor, as SiGe (SiGe), carborundum, GaAs, indium arsenide or indium phosphide.Designing requirement known according to prior art (for example p-type substrate or N-shaped substrate), substrate can comprise various doping configurations.In addition, can also comprise other devices in substrate.
Then, form three-dimensional raceway groove 208 on described substrate 201, with reference to shown in Figure 5.
In this embodiment, described three-dimensional raceway groove 208 is the fin type, can realize by following steps:
The described silicon substrate 201 of first etching forms groove in silicon substrate 201, then with dielectric material, and silicon dioxide for example, filling groove, and after carrying out planarization, form isolated area 205 in groove, as shown in Figure 4.
Then, described isolated area 205 is returned quarter, namely remove the dielectric material that is partially filled in groove, expose like this sidewall sections of the substrate between described isolated area, be positioned at go back to like this surface that substrate on the isolated area 206 after carving partly has a plurality of exposures, the degree of depth of rollback has also just determined the height h of this fin channel, has just formed the three-dimensional raceway groove 208 of fin type.
In other embodiments, can also proceed the method for oxidation and etching, further form the three-dimensional raceway groove of other shapes, as three-dimensional raceway grooves such as Ω type or nanowire-types.
Then, the surface that covers three-dimensional raceway groove 208 with form electric charge capture formula storage layer stack 202 with and on gate electrode 204, described electric charge capture formula storage layer stack comprises tunnel layer, charge storage layer and barrier layer, with reference to shown in Figure 7.
At first form electric charge capture formula storage layer stack 202, in the present embodiment, adopt the electric charge capture formula storage layer stack of ANO structure, can complete SiO by techniques such as oxidation, deposit, PVD, ALD
2Tunnel oxide 202-1, Si
3N
4Electric charge capture layer 202-2 and Al
2O
3Barrier layer 202-3.In other embodiments, described electric charge capture formula storage layer stack can also adopt tunnel oxide, electric charge capture layer and the barrier layer of other materials to be formed by suitable technique.
Then, form gate electrode 204, in the present embodiment, adopt the process deposit gate electrodes such as PVD, CVD, then, form the word line by etching, arrange as the memory cell in Fig. 1 and word line, being two memory cell adjacent on same word line (BB ' direction in Fig. 1) shown in Fig. 7, is two memory cell (AA ' direction in Fig. 1, source-drain area is not shown) adjacent on same bit line in Fig. 8.
It is to be noted, only described as the key link in the memory preparation of the memory cell of NOR type flash memory storage array herein, drawing connection etc. and can adopting any other conventional manufacturing process to carry out of other source-drain areas and word line, bit line do not given unnecessary details herein.
In addition, memory of the present invention and manufacture method are all to be described with the array arrangement in Fig. 1, but the present invention is not limited to this, and figure arranges for other NOR stencillings, and the memory cell with semiconductor memory of the present invention is still contained by the present invention.
Above the structure of semiconductor memory of the present invention and the embodiment of manufacture method are described in detail, the above is only preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, yet is not to limit the present invention.Any those of ordinary skill in the art, do not breaking away from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (8)
1. semiconductor storage unit, the memory cell in NOR type flash memory storage array is characterized in that, comprising:
Substrate;
Three-dimensional raceway groove on substrate;
Cover the electric charge capture formula storage layer stack of three-dimensional channel surface, described electric charge capture formula storage layer stack comprises tunnel layer, charge storage layer, barrier layer, and the gate electrode that covers electric charge capture formula storage layer stack.
2. semiconductor storage unit according to claim 1, is characterized in that, described three-dimensional raceway groove is fin type, Ω type or nanowire-type.
3. semiconductor storage unit according to claim 1, is characterized in that, described tunnel layer is SiO
2, SiON, high K medium material or their combination.
4. semiconductor storage unit according to claim 1, is characterized in that, described charge storage layer is thin floating boom storage medium or electric charge capture storage medium.
5. semiconductor storage unit according to claim 1, is characterized in that, described barrier layer is SiO
2, Si
3N
4, Al
2O
3, high K medium material or their combination.
6. the manufacture method of a semiconductor storage unit, described device is the memory cell in NOR type flash memory storage array, it is characterized in that, comprising:
Substrate is provided;
Form three-dimensional raceway groove on described substrate;
Cover three-dimensional channel surface with form electric charge capture formula storage layer stack with and on gate electrode, described electric charge capture formula storage layer stack comprises tunnel layer, charge storage layer and barrier layer.
7. manufacture method according to claim 6, is characterized in that, described three-dimensional raceway groove is fin type, Ω type or nanowire-type.
8. manufacture method according to claim 7, is characterized in that, the step that forms the three-dimensional raceway groove of described fin type is:
The described substrate of etching is also filled, and forms isolated area in substrate;
Described isolated area is returned quarter, expose the sidewall of the substrate between described isolated area, to form the three-dimensional raceway groove of fin type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104128119A CN103165613A (en) | 2011-12-12 | 2011-12-12 | Semiconductor memory and manufacturing method of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104128119A CN103165613A (en) | 2011-12-12 | 2011-12-12 | Semiconductor memory and manufacturing method of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103165613A true CN103165613A (en) | 2013-06-19 |
Family
ID=48588562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011104128119A Pending CN103165613A (en) | 2011-12-12 | 2011-12-12 | Semiconductor memory and manufacturing method of the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103165613A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016037399A1 (en) * | 2014-09-10 | 2016-03-17 | 中国科学院微电子研究所 | U-shaped finfet or non-gate structure and manufacturing method thereof |
| CN106206747A (en) * | 2016-09-20 | 2016-12-07 | 上海华力微电子有限公司 | A kind of ONO inter polysilicon dielectric layer structure and preparation method |
| CN107623004A (en) * | 2017-09-06 | 2018-01-23 | 上海华力微电子有限公司 | A kind of 3D SONOS devices and its manufacture method |
| WO2022028161A1 (en) * | 2020-08-06 | 2022-02-10 | 长鑫存储技术有限公司 | Memory and preparation method for memory |
| CN116042789A (en) * | 2017-09-29 | 2023-05-02 | 帕洛根公司 | Nanopore device and method of manufacturing the same |
| US11882689B2 (en) | 2020-08-06 | 2024-01-23 | Changxin Memory Technologies, Inc. | Memory and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020106855A1 (en) * | 2001-02-06 | 2002-08-08 | Hidenori Sato | Method of manufacturing semiconductor device |
| KR20090103055A (en) * | 2008-03-27 | 2009-10-01 | 주식회사 하이닉스반도체 | Flash memory device and manufacturing method thereof |
| CN102163576A (en) * | 2011-03-10 | 2011-08-24 | 上海宏力半导体制造有限公司 | Split-gate flash memory unit and manufacturing method thereof |
-
2011
- 2011-12-12 CN CN2011104128119A patent/CN103165613A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020106855A1 (en) * | 2001-02-06 | 2002-08-08 | Hidenori Sato | Method of manufacturing semiconductor device |
| KR20090103055A (en) * | 2008-03-27 | 2009-10-01 | 주식회사 하이닉스반도체 | Flash memory device and manufacturing method thereof |
| CN102163576A (en) * | 2011-03-10 | 2011-08-24 | 上海宏力半导体制造有限公司 | Split-gate flash memory unit and manufacturing method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016037399A1 (en) * | 2014-09-10 | 2016-03-17 | 中国科学院微电子研究所 | U-shaped finfet or non-gate structure and manufacturing method thereof |
| CN105470254A (en) * | 2014-09-10 | 2016-04-06 | 中国科学院微电子研究所 | U type FinFET NOR gate structure and manufacture method thereof |
| CN105470254B (en) * | 2014-09-10 | 2018-10-02 | 中国科学院微电子研究所 | A kind of U-shaped FinFET nor gates structure and its manufacturing method |
| CN106206747A (en) * | 2016-09-20 | 2016-12-07 | 上海华力微电子有限公司 | A kind of ONO inter polysilicon dielectric layer structure and preparation method |
| CN107623004A (en) * | 2017-09-06 | 2018-01-23 | 上海华力微电子有限公司 | A kind of 3D SONOS devices and its manufacture method |
| CN116042789A (en) * | 2017-09-29 | 2023-05-02 | 帕洛根公司 | Nanopore device and method of manufacturing the same |
| WO2022028161A1 (en) * | 2020-08-06 | 2022-02-10 | 长鑫存储技术有限公司 | Memory and preparation method for memory |
| US11882689B2 (en) | 2020-08-06 | 2024-01-23 | Changxin Memory Technologies, Inc. | Memory and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8786004B2 (en) | 3D stacked array having cut-off gate line and fabrication method thereof | |
| US8674429B2 (en) | Gate structure in non-volatile memory device | |
| US8445954B2 (en) | Three-dimensional semiconductor memory device | |
| JP2020504458A (en) | Memory cell, integrated structure and memory array | |
| US9105737B2 (en) | Semiconductor constructions | |
| US8705274B2 (en) | Three-dimensional multi-bit non-volatile memory and method for manufacturing the same | |
| US8507976B2 (en) | Nonvolatile memory device and method for fabricating the same | |
| US20120061637A1 (en) | 3-d structured nonvolatile memory array and method for fabricating the same | |
| KR101949375B1 (en) | Method for fabricating nonvolatile memory device | |
| CN103165613A (en) | Semiconductor memory and manufacturing method of the same | |
| CN103563085A (en) | Vertical tunneling negative differential resistance devices | |
| JP5823354B2 (en) | Nonvolatile semiconductor memory device and manufacturing method thereof | |
| CN103258860A (en) | Semiconductor memory and manufacturing method thereof | |
| CN104134668A (en) | Memory device and fabrication method and access method thereof | |
| US8779503B2 (en) | Nonvolatile semiconductor memory | |
| CN102315173A (en) | Method for preparing three-dimensional multivalue nonvolatile memory | |
| US20230397399A1 (en) | Semiconductor structure and manufacturing method thereof | |
| KR20080008057A (en) | Fabricating method of non-volatile memory integrate circuit device and non-volatile memory integrate circuit device thereby | |
| CN109920794B (en) | Three-dimensional ferroelectric memory and manufacturing method thereof | |
| US8951881B2 (en) | Methods of fabricating nonvolatile memory devices including voids between active regions and related devices | |
| CN103137860A (en) | Nonvolatile three-dimensional semiconductor memory device and preparing method | |
| CN102479823B (en) | Vertical NROM storage structure and preparation method thereof | |
| CN104124248B (en) | NOR-type flash memory unit for lifting common source region and preparation method thereof | |
| CN102456746B (en) | Nonvolatile semiconductor memory cell, device and preparation method thereof | |
| JP2014003235A (en) | Nonvolatile semiconductor memory device and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130619 |
|
| RJ01 | Rejection of invention patent application after publication |