CN102347238A - Method for manufacturing semiconductor device structure with P-type polysilicon gate - Google Patents
Method for manufacturing semiconductor device structure with P-type polysilicon gate Download PDFInfo
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- CN102347238A CN102347238A CN2010102455060A CN201010245506A CN102347238A CN 102347238 A CN102347238 A CN 102347238A CN 2010102455060 A CN2010102455060 A CN 2010102455060A CN 201010245506 A CN201010245506 A CN 201010245506A CN 102347238 A CN102347238 A CN 102347238A
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Abstract
The invention provides a method for manufacturing a semiconductor device structure with a P-type polysilicon gate. Sheet resistance of the P-type polysilicon gate is a target value. The method comprises the following steps of: providing a substrate on which the P-type polysilicon gate is arranged; forming a gasket material layer and a gap wall material layer on the substrate and the P-type polysilicon gate sequentially, wherein the gasket material layer comprises a first oxide deposited at first deposition temperature, the gap wall material layer comprises a second oxide deposited at second deposition temperature, the first deposition temperature and/or the second deposition temperature are/is set according to the target value; removing a part, positioned above the substrate and the P-type polysilicon gate, of the gap wall material layer; and forming a source and a drain in the substrate on two sides of the P-type polysilicon gate through ion injection and annealing. By the method, the sheet resistance of the P-type polysilicon gate can be independently adjusted to the target value.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of making has the method for the semiconductor device structure of P type polysilicon bar.
Background technology
When using the CMOS technology to make complicated integrated circuit, there are millions of transistors (for example, nmos pass transistor and PMOS transistor) to be formed on the Semiconductor substrate.Each transistor all comprises an input electrode and is called grid, and grid can be processed by the polysilicon gate that mixes.Through the dissimilar conducting particles that in polysilicon gate, mixes, obtain nmos pass transistor and PMOS transistor.
Figure 1A to Fig. 1 D makes the cutaway view of each step in the cmos device structure flow process for adopting conventional method.
Shown in Figure 1A, substrate 101 is provided, nmos area territory 103 and PMOS zone 104 that this substrate 101 has formation thereon and separated each other by fleet plough groove isolation structure 102.Nmos pass transistor will be formed on nmos area territory 103, and the PMOS transistor will be formed on PMOS zone 104.The N type polysilicon bar of nmos pass transistor comprises gate oxide layers 105A and N type gate material layers 106A.The transistorized P type polysilicon bar of PMOS comprises gate oxide layers 105B and P type gate material layers 106B.Then carry out ion implantation technology; Respectively light dope technology is carried out in nmos area territory 103 and PMOS zone 104; Form LDD district 120B, the 120B ' in lightly doped drain (LDD) 120A, 120A ' and the PMOS zone 104 in nmos area territory 103, carry out annealing process then.
Shown in Figure 1B; On substrate, N type polysilicon bar and P type polysilicon bar, form cushioning material layer 109 and spacer material layer, the spacer material layer is carried out clearance wall 108B, the 108B ' that etching forms clearance wall 108A, 108A ' and the PMOS zone 104 in nmos area territory 103.
Shown in Fig. 1 C, on PMOS zone 104, form one deck photoresist layer 121, N type ion implantation technology is carried out in nmos area territory 103, remove photoresist layer 121, with the source/drain electrode 107A that accomplishes nmos area territory 103, the making of 107A '.
Adopt source/ drain electrode 107B, 107B ' (shown in Fig. 1 D) with making source/drain electrode 107A, method making PMOS regional 104 that 107A ' is identical.Omitted the cutaway view of the related device architecture of this step here.Carry out annealing process then.
Shown in Fig. 1 D, remove the cushioning material layer 109 that is not blocked by clearance wall 108A, 108A ' and 108B, 108B ', form the first laying 109A, 109A ' and the second laying 109B, 109B ', accomplish the making of cmos device structure.
For P type polysilicon bar and N type polysilicon bar, its majority carrier kind that plays electric action is different, and the P type polysilicon bar makes the hole become majority carrier through doping B element etc. and realizes conducting function; The N type polysilicon bar then makes electronics become majority carrier through doping N, P element etc. and realizes conducting function.The conductivity principle of two kinds of polysilicon gates is different, even so the P type of under identical process conditions, making and the sheet resistance R of N type polysilicon bar
s(Sheet Resistance) is also inequality, can have the difference of 1%-10% usually.The different electric properties of device that can make with the sheet resistance of N type polysilicon bar of P type are inhomogeneous, and make device speed of service under varying environment inconsistent, thereby cause yields to descend.Therefore, with the difference limit between the sheet resistance of P type and N type polysilicon bar be one of key of realizing the reliable electric property of device in the tolerable error scope.
The sheet resistance of polysilicon gate usually with thickness, grid critical size (CD) and the preceding working procedure of interlayer dielectric layer in thermal effect relevant.Generally speaking, the thickness of interlayer dielectric layer is big more, and the sheet resistance of polysilicon gate is big more; The grid critical size is more little, and the sheet resistance of polysilicon gate is big more; Thermal effect is comparatively complicated to the influence of sheet resistance, in the research of semiconductor technology, remains an insoluble problem.Usually regulate sheet resistance through regulating preceding two influencing factors in the prior art, but in the technology thickness of interlayer dielectric layer and the change amount of grid critical size are difficult to be controlled in 5%, therefore be difficult to accurately sheet resistance transferred to desired value.In addition, thickness and the method for grid critical size of control interlayer dielectric layer can not be regulated the sheet resistance of P type and N type polysilicon bar respectively, so still can't dwindle the difference between the sheet resistance of P type and N type polysilicon bar.
Therefore; Be badly in need of a kind of manufacture method of cmos device structure at present; Can adjust the sheet resistance of one type polysilicon gate separately through this method; And the sheet resistance of polysilicon gate that will this type transfers to desired value; Further, the sheet resistance of the polysilicon gate through adjusting this type dwindles the difference between the sheet resistance of P type and N type polysilicon bar, thereby improves the uniformity of device electric property; Make device speed of service under varying environment even, thereby improve yields.
Summary of the invention
In the summary of the invention part, introduced the notion of a series of reduced forms, this will further explain in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to confirm technical scheme required for protection.
The problem that can't accurately control for the sheet resistance that solves polysilicon gate in the prior art; The present invention provides a kind of making to have the method for the semiconductor device structure of P type polysilicon bar; The sheet resistance of said P type polysilicon bar is a desired value; Said method comprises: substrate is provided, has the P type polysilicon bar on the said substrate; On said substrate and said P type polysilicon bar, form cushioning material layer and spacer material layer successively; Said cushioning material layer comprises first oxide with first depositing temperature deposition, and said spacer material layer comprises second oxide with second depositing temperature deposition; Remove said spacer material layer and be positioned at the part on said substrate and the said P type polysilicon bar; Form source electrode and drain electrode through ion injection and the substrate of annealing in said P type polysilicon bar both sides; Wherein, According to said desired value; Set said first depositing temperature and/or said second depositing temperature; This setting comprises: said first depositing temperature or second depositing temperature are set at said desired value corresponding temperature value on first relation curve of measuring in advance, and said first relation curve is the relation curve between the depositing temperature of sheet resistance and said first oxide or said second oxide of the P type polysilicon bar on the said substrate; Perhaps said first depositing temperature and second depositing temperature all are set at said desired value corresponding temperature value on second relation curve of measuring in advance; Said first depositing temperature is identical with said second depositing temperature; Said second relation curve is the relation curve between the depositing temperature of sheet resistance and said first oxide and said second oxide of the P type polysilicon bar on the said substrate; In said second relation curve; With respect to same sheet resistance, the depositing temperature of said first oxide is identical with the depositing temperature of said second oxide.
The above-mentioned manufacture method of semiconductor device according to the invention structure can be adjusted the sheet resistance of P type polysilicon bar separately, and the sheet resistance of P type polysilicon bar is accurately transferred to desired value.
Preferably; Said first relation curve is obtained by following assay method, and said assay method comprises: the sheet resistance of measuring the P type polysilicon bar respectively through experiment is under the multiple condition and the relation curve between the depositing temperature of said first oxide or said second oxide; And the corresponding relation curve of the residing condition of P type polysilicon bar on selection and the said substrate is as said first relation curve.
Preferably; Said second relation curve is obtained by following assay method, and said assay method comprises: the sheet resistance of measuring the P type polysilicon bar respectively through experiment is under the multiple condition and the relation curve between the depositing temperature of said first oxide and said second oxide; And the corresponding relation curve of the residing condition of P type polysilicon bar on selection and the said substrate is as second relation curve.
Many the relation curves of making under the different condition can the opening relationships curve set, so that when adopting different technology conditions to make semiconductor device, can choose pairing curve quickly and easily, thereby raise the efficiency.
Preferably, according to said desired value, setting said first depositing temperature and/or second depositing temperature is 300-450 ℃.
Preferably, setting said first depositing temperature and/or second depositing temperature is 380-400 ℃.
The depositing temperature that under said temperature, changes first oxide and second oxide does not exert an influence to other condition of manufacturing process basically, promptly takes into account the requirement of sheet resistance adjustable range and production efficiency, can regulate the sheet resistance of P type polysilicon bar again exactly.
Preferably, said first oxide and said second oxide are silica.
All feed silicon source gas and oxide gas when preferably, depositing said first oxide and said second oxide.
Preferably, said silicon source gas is a silane, and said oxide gas is a nitrous oxide.
Preferably, the flow velocity of said silane is between 50-500sccm, and the flow velocity of said nitrous oxide is between 5000-20000sccm.
Pressure when preferably, depositing said first oxide and said second oxide is 1-5Torr.
Pressure when preferably, depositing said first oxide and said second oxide is 2-4Torr.
Also feed protective gas when preferably, depositing said first oxide and said second oxide.
Preferably, said front end device architecture also comprises the N type polysilicon bar.
Preferably, the sheet resistance of said N type polysilicon bar is R, and said desired value is 95%R～105%R.
Preferably, said desired value is 99%R～101%R.
In the semiconductor device of for example CMOS; Sheet resistance through adjustment P type polysilicon bar dwindles the difference between the sheet resistance of P type and N type polysilicon bar; Thereby improve the uniformity of device electric property, make device speed of service under varying environment even, thereby improve yields.
Preferably, said method also comprises: remove the part that is positioned in the said cushioning material layer on said substrate and the said P type polysilicon bar, make to accomplish whole transistor
Description of drawings
Attached drawings of the present invention is used to understand the present invention at this as a part of the present invention.Execution mode of the present invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 D makes the cutaway view of each step in the cmos device structure flow process for adopting conventional method;
Fig. 2 is for making the method flow diagram of the semiconductor device structure with P type polysilicon bar according to the present invention;
Fig. 3 is P type polysilicon bar sheet resistance of one embodiment of the present invention and the relation curve between the oxidate temperature.
Embodiment
In the description hereinafter, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and be able to enforcement.In other example,, describe for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention makes semiconductor device structure with P type polysilicon bar.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Better embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
In the manufacture process of semiconductor device structure, the spacer material layer in the clearance wall structure and the deposition of cushioning material layer are used vapour deposition, for example chemical vapour deposition (CVD) or physical vapour deposition (PVD) etc. usually.Some differences can appear along with the change of technology in the structure of spacer material layer and cushioning material layer.For instance, in the 45nm technology node, cushioning material layer is one deck oxide normally, and the spacer material layer then comprises one deck oxide skin(coating) that forms earlier and one deck silicon nitride that forms subsequently; In the 55nm technology node, cushioning material layer is oxide and nitride layer normally, and the structure of spacer material layer is identical with structure in the 45nm technology.In the process that the applicant finds to adopt chemical gaseous phase depositing process to form the clearance wall structure; The depositing temperature of oxide can produce certain influence to the sheet resistance of P type polysilicon bar in spacer material layer and the cushioning material layer, but the sheet resistance of N type polysilicon bar is not had influence basically.
Fig. 2 is for making the method flow diagram of the semiconductor device structure with P type polysilicon bar according to the present invention.
In step 201, substrate is provided, have the P type polysilicon bar on this substrate, in cmos device structure for example, can also have the N type polysilicon bar on the substrate.Said substrate can comprise but be not limited at least a in the following material of mentioning: for example silicon, silicon-on-insulator (silicon on insulator; SOI), insulator laminated silicon (stacked silicon on insulator; SSOI), insulator laminated SiGe (stacked SiGe on insulator; S-SiGeOI), germanium on insulator silicon (SiGe on insulator; SiGeOI) and germanium on insulator (Ge on insulator, GeOI).
In step 202, on substrate and P type polysilicon bar, form cushioning material layer and spacer material layer successively.The present invention adopts the method for chemical vapour deposition (CVD) to form spacer material layer and cushioning material layer.As, can adopt low-pressure chemical vapor deposition (LPCVD) method or plasma enhanced chemical vapor deposition (PECVD) method etc.Wherein, Said cushioning material layer comprises first oxide with first depositing temperature deposition; Said spacer material layer comprises second oxide with second depositing temperature deposition; Wherein, According to the sheet resistance of P type polysilicon bar the desired value that will reach, set first depositing temperature and/or second depositing temperature.
The applicant finds; Though under the different techniques node; The concrete structure of cushioning material layer and spacer material layer is slightly different; But the sheet resistance of P type polysilicon bar can be regular with the depositing temperature of oxide in cushioning material layer and the spacer material layer to be changed, and promptly the sheet resistance of P type polysilicon bar reduces with the rising of depositing temperature.But the change of oxidate temperature does not exert an influence to the sheet resistance of N type polysilicon bar basically.Therefore, method of the present invention can be only adjusted the sheet resistance of the polysilicon gate of a type (P type), and makes it reach desired value.
First oxide and second oxide are silica (SiO among the present invention
2), the reacting gas that wherein forms silica comprises the silicon source gas that can be used for grow oxide, like silane (SiH
4), disilane (Si
2H
6) etc., and oxide gas, like nitrous oxide (N
2O) etc.Pressure in diluting reaction gas and/or the maintenance reaction chamber can also add protective gas, for example helium, argon gas etc. in the deposition process.The flow velocity of concrete protective gas can wait to confirm according to the flow velocity of reacting gas, pressure in the reaction chamber.In order to take into account the requirement of sheet resistance adjustable range and production efficiency, set first depositing temperature usually and/or second depositing temperature is 300-450 ℃, be preferably 380-400 ℃.In the deposition oxide process, the pressure in the reaction chamber is in the 1-5Torr scope, as being 1,2,3,4 or 5Torr etc.In addition, the concrete thickness of first oxide and second oxide is by the specific requirement decision of this device.
According to the sheet resistance of P type polysilicon bar the desired value that will reach, set first depositing temperature and/or second depositing temperature.Particularly, according to said desired value, set first depositing temperature or second depositing temperature; Perhaps according to said desired value, setting first depositing temperature and second depositing temperature is same temperature value.
Set the step of the depositing temperature of first oxide or second oxide; Comprise: first depositing temperature or second depositing temperature are set at said desired value corresponding temperature value on first relation curve of measuring in advance; Wherein, first relation curve is the relation curve between the depositing temperature of sheet resistance and first oxide or second oxide of the P type polysilicon bar on the above-mentioned substrate.
Wherein, First relation curve obtains through following assay method; Said assay method comprises: the relation curve of the sheet resistance of measuring the P type polysilicon bar respectively through experiment between the depositing temperature of (for example, under the different film thicknesses, under the differential responses gas, under the flow velocity of differential responses gas, different pressures inferior) under the multiple condition and first oxide or second oxide; And the corresponding relation curve of the residing condition of P type polysilicon bar on selection and the above-mentioned substrate is as first relation curve.
The depositing temperature of setting first oxide and second oxide is the step of same temperature value; Comprise: first depositing temperature and second depositing temperature all are set at said desired value corresponding temperature value on second relation curve of measuring in advance; Wherein, second relation curve is the relation curve between the depositing temperature of sheet resistance and first oxide and second oxide of the P type polysilicon bar on the above-mentioned substrate.In second relation curve, with respect to same sheet resistance, the depositing temperature of first oxide is identical with the depositing temperature of second oxide.
Wherein, second relation curve obtains through following assay method, and said assay method comprises: the sheet resistance of measuring the P type polysilicon bar respectively through experiment is under the multiple condition and the relation curve between the depositing temperature of first oxide and second oxide; And the corresponding relation curve of the residing condition of P type polysilicon bar on selection and the above-mentioned substrate is as second relation curve.
In step 203, the spacer material layer is carried out etching, remove the spacer material layer and be positioned at the part on substrate and the P type polysilicon bar, form clearance wall with both sides at the P type polysilicon bar.
In step 204, form source electrode and drain electrode through ion injection and the substrate of annealing in P type polysilicon bar both sides.At first carry out ion and inject formation source/drain electrode in the substrate of P type polysilicon bar both sides; Then, carry out annealing process, to activate dopant ion.
In step 205, be positioned at the part on substrate and the P type polysilicon bar in the removal cushioning material layer, form laying, thereby accomplish the making of semiconductor device structure.
Method of the present invention can also be applied to comprise the semiconductor device of N type polysilicon bar, and for example the cmos device structure is adjusted the sheet resistance of P type polysilicon bar, and the sheet resistance of N type polysilicon bar is not exerted an influence basically.When also being formed with the N type polysilicon bar on the substrate; Part steps in the subsequent technique also need be carried out adaptive adjustment; For example cushioning material layer and spacer material layer are formed on substrate, P type polysilicon bar and the N type polysilicon bar; Form clearance wall, formation source/drain electrode or the like in the substrate of P type polysilicon bar and N type polysilicon bar both sides at P type polysilicon bar and N type polysilicon bar both sides.
In the cmos device structure,, can adopt method of the present invention to regulate the sheet resistance of P type polysilicon bar, with the difference between the sheet resistance that reduces N type and P type polysilicon bar in order to keep the uniformity of device.If the sheet resistance of N type polysilicon bar is R, according to technologic needs, this moment, desired value can be 95%R～105%R.In order further to reduce the difference between P type and the N type polysilicon bar sheet resistance, said desired value can be 99%R～101%R.
To describe the step of measuring relation curve in detail according to one embodiment of the present invention below.
At first, through the sheet resistance of measuring P type polysilicon bar and many relation curves between the depositing temperature in first oxide and second oxide, wherein first oxide is identical with the temperature of second oxide.This step will be carried out many group experiments, wherein, need keep other parameter constant when measuring every relation curve, and only the depositing temperature of oxide changes.After cushioning material layer and spacer material layer deposition, spacer material layer etching, doping formation source/drain electrode and annealing, measure the sheet resistance of P type polysilicon bar respectively.Because the present invention only discusses the influence of the depositing temperature of oxide to the sheet resistance of P type polysilicon bar, therefore be not described in detail for other step.In addition, cushioning material layer and spacer material layer deposition comprises the deposition of oxide and the deposition of nitride.Wherein, the deposition of nitride can adopt technological means well known in the art, therefore repeats no more.
According to one embodiment of the present invention, the reacting gas that generates first oxide and second oxide is silane and nitrous oxide, and its concrete reaction equation is:
SiH
4+ N
2O → SiO
2+ accessory substance
The flow velocity of silane is between 50-500sccm, and the flow velocity of nitrous oxide is between 5000-20000sccm, and wherein, sccm is under the standard state, just 1 atmospheric pressure, 1 cubic centimetre of (1cm of 25 degrees centigrade of following per minutes
3/ min) flow velocity.In this execution mode, do not add protective gas during deposited polycrystalline silicon thin film.Depositing temperature is adjusted in 380-400 ℃ of scope, as being 380 ℃, 390 ℃ and 400 ℃ etc.In the deposition oxide process, pressure is between 2-4Torr.Only to the 45nm technology node, wherein, the thickness of first oxide and second oxide is respectively 10-50 dust and 100-200 dust to this execution mode.
According to above-mentioned steps, obtain relation curve shown in Figure 3.As shown in Figure 3, abscissa is the depositing temperature of first oxide and second oxide among the figure, and ordinate is the sheet resistance of P type polysilicon bar.Data point 301 is for testing each data point of the pairing sheet resistance of different deposition temperatures that obtains, the linear relationship of straight line 302 for obtaining according to each data point match.Along with the oxidate temperature constantly raises, the sheet resistance of the P type polysilicon bar of generation is more and more littler.
Then, according to desired value, confirm the depositing temperature of first oxide and second oxide according to this relation curve.For example; When desired value is 760 ohm, and the sheet resistance of P type polysilicon bar can all be set at the depositing temperature of two kinds of oxides 387 ℃ when being 750 ohm; Make the sheet resistance of P type polysilicon bar can increase to 760 ohm, thereby the sheet resistance of P type polysilicon bar is transferred to desired value.When desired value is 760 ohm; And the sheet resistance of P type polysilicon bar is when being 770 ohm; The depositing temperature of two kinds of oxides all can be set at 387 ℃, make the sheet resistance of P type polysilicon bar can be reduced to 760 ohm, thereby the sheet resistance of P type polysilicon bar is transferred to desired value.Therefore, in an execution mode of manufacture method of the present invention, also comprise: on substrate, form after the P type polysilicon bar, the sheet resistance of this P type polysilicon bar is measured, to obtain initial sheet resistance.Then,, first depositing temperature and/or second depositing temperature are set, to obtain to have the semiconductor device structure that sheet resistance is the P type polysilicon bar of desired value based on this initial sheet resistance and said relation curve.
According to the embodiment of the present invention; Between 380-400 ℃, adjust the depositing temperature of first oxide and second oxide simultaneously; And the depositing temperature of first oxide and second oxide equates; The excursion of the sheet resistance of P type polysilicon bar is 750-770 ohm; Therefore can between ± 20 ohm, finely tune the sheet resistance of P type polysilicon bar, thereby the sheet resistance of P type polysilicon bar is accurately transferred to desired value.The method of another execution mode according to the present invention; The depositing temperature of individual setting first oxide or second oxide; Can in littler scope, finely tune the sheet resistance of P type polysilicon bar, reduce the amplitude of fine setting, to improve the accuracy of P type polysilicon bar sheet resistance.
In manufacture method of the present invention, through setting first depositing temperature and/or second depositing temperature, can regulate the sheet resistance of P type polysilicon bar, and the sheet resistance of N type polysilicon bar is not almost influenced.The mechanism of above-mentioned phenomenon is comparatively complicated, and the inventor thinks, because silicon source gas and oxide gas reaction generate in the process of oxide, can produce the accessory substance that comprises hydrogen, and the hydrogen of generation has part and remains in the oxide skin(coating).In subsequent anneal technology, hydrogen constantly spreads in the P type polysilicon bar, is diffused into the position of the boron of the hydrogen possibility substitute doping in the P type polysilicon bar, and then influences the sheet resistance of P type polysilicon bar.Specifically, when depositing temperature raise, the hydrogen of generation was easier to from oxide, overflow; Therefore the concentration that is diffused in the P type polysilicon bar reduces; Substituted boron is less, and promptly the concentration of excess carrier is higher in the P type polysilicon bar, so the sheet resistance of P type polysilicon bar is less.Otherwise when depositing temperature reduced, the hydrogen of generation was not easy from oxide, to overflow relatively; Therefore the concentration that is diffused in the P type polysilicon bar raises; Substituted boron is more, and promptly the concentration of excess carrier is lower in the P type polysilicon bar, so the sheet resistance of P type polysilicon bar is bigger.
Method of the present invention can be adjusted the sheet resistance of P type polysilicon bar separately, and the sheet resistance of P type polysilicon bar is transferred to desired value.Further; In cmos device structure for example; Sheet resistance by adjustment P type polysilicon bar dwindles the difference between the sheet resistance of P type and N type polysilicon bar; Can be used for when less deviation occurring between the sheet resistance of P type and N type polysilicon bar (usually in tens of ohms); Set first depositing temperature and/or second depositing temperature; Realize fine setting easily and flexibly to the sheet resistance of P type polysilicon bar; Make difference between P type and the N type polysilicon bar sheet resistance in the tolerable scope; Thereby improve the uniformity of device electric property; Make device speed of service under varying environment even, improve yields.
Have according to the semiconductor device structure of execution mode manufacturing as stated and can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, like random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, like programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products; In various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated through above-mentioned execution mode, but should be understood that, above-mentioned execution mode just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described execution mode scope.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-mentioned execution mode, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (16)
1. a making has the method for the semiconductor device structure of P type polysilicon bar, and the sheet resistance of said P type polysilicon bar is a desired value, and said method comprises:
Substrate is provided, has the P type polysilicon bar on the said substrate;
On said substrate and said P type polysilicon bar, form cushioning material layer and spacer material layer successively; Said cushioning material layer comprises first oxide with first depositing temperature deposition, and said spacer material layer comprises second oxide with second depositing temperature deposition;
Remove said spacer material layer and be positioned at the part on said substrate and the said P type polysilicon bar;
Form source electrode and drain electrode through ion injection and the substrate of annealing in said P type polysilicon bar both sides,
Wherein, according to said desired value, set said first depositing temperature and/or said second depositing temperature, this setting comprises:
Said first depositing temperature or second depositing temperature are set at said desired value corresponding temperature value on first relation curve of measuring in advance, and said first relation curve is the relation curve between the depositing temperature of sheet resistance and said first oxide or said second oxide of the P type polysilicon bar on the said substrate; Perhaps
Said first depositing temperature and second depositing temperature all are set at said desired value corresponding temperature value on second relation curve of measuring in advance; Said first depositing temperature is identical with said second depositing temperature; Said second relation curve is the relation curve between the depositing temperature of sheet resistance and said first oxide and said second oxide of the P type polysilicon bar on the said substrate; In said second relation curve; With respect to same sheet resistance, the depositing temperature of said first oxide is identical with the depositing temperature of said second oxide.
2. the method for claim 1 is characterized in that, said first relation curve is obtained by following assay method, and said assay method comprises:
The sheet resistance of measuring the P type polysilicon bar respectively through experiment is under the multiple condition and the relation curve between the depositing temperature of said first oxide or said second oxide; And
The corresponding relation curve of the residing condition of P type polysilicon bar on selection and the said substrate is as said first relation curve.
3. the method for claim 1 is characterized in that, said second relation curve is obtained by following assay method, and said assay method comprises:
The sheet resistance of measuring the P type polysilicon bar respectively through experiment is under the multiple condition and the relation curve between the depositing temperature of said first oxide and said second oxide; And
The corresponding relation curve of the residing condition of P type polysilicon bar on selection and the said substrate is as second relation curve.
4. like each described method among the claim 1-3, it is characterized in that according to said desired value, setting said first depositing temperature and/or second depositing temperature is 300-450 ℃.
5. method as claimed in claim 4 is characterized in that, setting said first depositing temperature and/or second depositing temperature is 380-400 ℃.
6. like each described method among the claim 1-3, it is characterized in that said first oxide and said second oxide are silica.
7. method as claimed in claim 6 is characterized in that, all feeds silicon source gas and oxide gas when depositing said first oxide and said second oxide.
8. method as claimed in claim 7 is characterized in that, said silicon source gas is a silane, and said oxide gas is a nitrous oxide.
9. method as claimed in claim 8 is characterized in that, the flow velocity of said silane is between 50-500sccm, and the flow velocity of said nitrous oxide is between 5000-20000sccm.
10. method as claimed in claim 7 is characterized in that, the pressure when depositing said first oxide and said second oxide is 1-5Torr.
11. method as claimed in claim 10 is characterized in that, the pressure when depositing said first oxide and said second oxide is 2-4Torr.
12. like claim 1 or 7 described methods, it is characterized in that, also feed protective gas when depositing said first oxide and said second oxide.
13., it is characterized in that said front end device architecture also comprises the N type polysilicon bar like each described method among the claim 1-3.
14. method as claimed in claim 13 is characterized in that, the sheet resistance of said N type polysilicon bar is R, and said desired value is 95%R～105%R.
15. method as claimed in claim 14 is characterized in that, said desired value is 99%R～101%R.
16. the method for claim 1 is characterized in that, said method also comprises: remove the part that is positioned in the said cushioning material layer on said substrate and the said P type polysilicon bar.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010245506 CN102347238B (en) | 2010-07-30 | 2010-07-30 | Method for manufacturing semiconductor device structure with P-type polysilicon gate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105529249A (en) * | 2016-02-29 | 2016-04-27 | 上海华力微电子有限公司 | Polycrystal silicon preparation method |
| CN109213086A (en) * | 2017-06-29 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Process system and manufacturing method thereof |
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| JPS56167323A (en) * | 1980-05-27 | 1981-12-23 | Nec Corp | Manufacture of semiconductor device |
| US5620922A (en) * | 1994-03-18 | 1997-04-15 | Seiko Instruments Inc. | Method for fabricating CMOS device having low and high resistance portions and wire formed from a single gate polysilicon |
| US5633523A (en) * | 1994-04-28 | 1997-05-27 | Ricoh Company, Ltd. | Complementary mis semiconductor device of dual gate structure having a silicide layer including a thinned portion |
| CN101577224A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Method for forming gate oxide |
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| JPS56167323A (en) * | 1980-05-27 | 1981-12-23 | Nec Corp | Manufacture of semiconductor device |
| US5620922A (en) * | 1994-03-18 | 1997-04-15 | Seiko Instruments Inc. | Method for fabricating CMOS device having low and high resistance portions and wire formed from a single gate polysilicon |
| US5633523A (en) * | 1994-04-28 | 1997-05-27 | Ricoh Company, Ltd. | Complementary mis semiconductor device of dual gate structure having a silicide layer including a thinned portion |
| CN101577224A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Method for forming gate oxide |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105529249A (en) * | 2016-02-29 | 2016-04-27 | 上海华力微电子有限公司 | Polycrystal silicon preparation method |
| CN109213086A (en) * | 2017-06-29 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Process system and manufacturing method thereof |
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