CN102339785A - Method for manufacturing metal damascene structure - Google Patents
Method for manufacturing metal damascene structure Download PDFInfo
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- CN102339785A CN102339785A CN2010102307478A CN201010230747A CN102339785A CN 102339785 A CN102339785 A CN 102339785A CN 2010102307478 A CN2010102307478 A CN 2010102307478A CN 201010230747 A CN201010230747 A CN 201010230747A CN 102339785 A CN102339785 A CN 102339785A
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Abstract
The invention discloses a method for manufacturing a metal damascene structure. The method comprises the following steps of: providing a semiconductor substrate; sequentially forming an etching stop layer and a dielectric layer on the semiconductor substrate; forming a metal silicide layer on the dielectric layer; forming an opening by etching the metal silicide layer and the dielectric layer, wherein the opening exposes the surface of the etching stop layer; forming a filling layer in the opening and on the metal silicide layer, wherein the filling layer fills up the opening; forming a trench by etching part of the filling layer, the metal silicide layer and part of the dielectric layer, wherein the position of the trench corresponds to the position of the opening; etching the rest of the filling layer and the etching stop layer exposed by the opening till the semiconductor substrate is exposed; and forming a metal layer in the opening and the trench so as to form the metal damascene structure. According to the method for manufacturing the metal damascene structure disclosed by the invention, the phenomenon of rounded top angle for trenches can be prevented, and the etching stop layer is prevented from being destructed by etching gas.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly relate to a kind of manufacturing approach of metal damascene structure.
Background technology
Along with the raising of semiconductor device integrated level, the use of multiple layer metal interconnection line is more and more wider.As a rule, the resistance of the metal level of multiple layer metal interconnection line is low more, and then the reliability of semiconductor device is high more, and performance is good more.Because the resistance of metallic copper is lower, be suitable as very much the multiple layer metal interconnection line, but come patterning because of metallic copper is difficult to utilize traditional chemical wet etching technology, therefore develop and damascene process An.Said damascene process An forms groove (trench) and opening (via) in advance in dielectric layer, then with electric conducting material for example copper fill said groove and opening.The technology of said damascene process An focuses on forming groove and opening; Exist two kinds of methods to make the groove and the opening of metal damascene structure at present; First method is to define groove on the top of dielectric layer earlier, defines opening then, and this method is because the density of groove is quite high; Make the surface irregularity of the photoresist layer be used to define opening, had a strong impact on the resolution of exposure imaging technology; Another kind method is in dielectric layer, to define opening earlier, utilizes photoresist layer to define groove then.
Specifically please refer to Figure 1A～1F, it is the generalized section of each step corresponding construction of the manufacturing approach of existing metal damascene structure, and the manufacturing approach of this metal damascene structure is to form groove after forming opening earlier.
With reference to Figure 1A, at first, Semiconductor substrate 100 is provided, be formed with metal line in the said Semiconductor substrate 100; Then, on Semiconductor substrate 100, form etching stop layer 110 and dielectric layer 120 successively.
With reference to Figure 1B, then, carry out chemical wet etching technology, in said dielectric layer 120, to form opening 120a, said opening 120a exposes said etching stop layer 110 surfaces.
With reference to figure 1C, afterwards, form packed layer 130 in said opening 120a and on the dielectric layer 120, said packed layer 130 fills up said opening 120a.
With reference to figure 1D; Thereafter; Etched portions packed layer 130 forms groove 120b with part dielectric layer 120; The position of said groove 120b is corresponding with the position of opening 120a, and the degree of depth of said groove 120b is less than the degree of depth of opening 120a, and the cross-sectional width of said groove 120b is greater than the cross-sectional width of opening 120a.
With reference to figure 1E, then, remaining packed layer in the said opening 120a of etching, the packed layer on the dielectric layer 120 is also etched away fully simultaneously; Then, the etching stop layer 110 that etching opening 120a exposes is until exposing Semiconductor substrate 100.
With reference to figure 1F, and combine Figure 1A to Fig. 1 E, last, in said opening 120a and groove 120b, form metal level 140, to form metal damascene structure, the material of said metal level 140 is preferably copper.
Yet; In actual production, find, when utilizing said method to form metal damascene structure, following problem can occur: at first; In the process that forms groove 120b; Because the destruction that the etching stop layer 110 that opening 120a is exposed also can receive etching gas makes that the metal line in the Semiconductor substrate 100 comes out, and influences the electric property of semiconductor device; In addition; Shown in Fig. 1 F; In the process of etched portions packed layer 130 and part dielectric layer 120, the destruction that the dielectric layer 120 of hoping to keep also receives etching gas easily makes the drift angle sphering of groove 120b; When the metal level 140 of follow-up formation is filled into the groove 120b of drift angle sphering, very easily cause short circuit between the adjacent metal layer 140.
Summary of the invention
The objective of the invention is to, a kind of manufacturing approach of metal damascene structure is provided, destroy with the gas that is etched of etching stop layer in the process of avoiding forming groove, and prevent the phenomenon of groove drift angle sphering, avoid the adjacent metal layer to be short-circuited.
For solving the problems of the technologies described above, the present invention provides a kind of manufacturing approach of metal damascene structure, may further comprise the steps: Semiconductor substrate is provided; On said Semiconductor substrate, form etching stop layer and dielectric layer successively; On said dielectric layer, form metal silicide layer; Said metal silicide layer of etching and dielectric layer form opening, and said opening exposes the etching stopping laminar surface; In said opening and on the metal silicide layer, form packed layer, said packed layer fills up said opening; Etched portions packed layer, metal silicide layer and part dielectric layer form groove, and the position of said groove is corresponding with the position of said opening; The etching stop layer that remaining packed layer of etching and said opening expose is until exposing Semiconductor substrate; In said opening and said groove, form metal level, to form metal damascene structure.
Optional, in the manufacturing approach of said metal damascene structure, the material of said metal silicide layer is a kind of or its combination in cobalt silicide, nickel silicide, tungsten silicide, Titanium silicide, the tantalum silicide.Said metal silicide layer is to utilize the mode of chemical vapour deposition (CVD) or physical vapour deposition (PVD) to form.Said metal silicide layer utilizes the sputter mode to form.The thickness of said metal silicide layer is 50～
Optional, in the manufacturing approach of said metal damascene structure, the material of said etching stop layer is a kind of or its combination in silicon nitride, silicon oxynitride or the carborundum.
Optional, in the manufacturing approach of said metal damascene structure, before forming metal silicide layer on the said dielectric layer, also be included in and form first cover layer on the said dielectric layer.Also comprise said first cover layer of etching in the step of said metal silicide layer of etching and dielectric layer.The said first tectal material is a kind of or its combination in silicon dioxide, silicon nitride or the silicon oxynitride.
Optional, in the manufacturing approach of said metal damascene structure, before said metal silicide layer of etching and the dielectric layer, also be included in and form second cover layer on the said metal silicide layer.Also comprise said second cover layer of etching in the step of said metal silicide layer of etching and dielectric layer.The said second tectal material is a silicon oxynitride.
The present invention provides a kind of manufacturing approach of metal damascene structure, may further comprise the steps: Semiconductor substrate is provided; On said Semiconductor substrate, form etching stop layer and dielectric layer successively; On said dielectric layer, form metal silicide layer; The said dielectric layer of said metal silicide layer of etching and part forms opening; In said opening and on the metal silicide layer, form packed layer, said packed layer fills up said opening; Etching packed layer and metal silicide layer form groove, and the position of said groove is corresponding with the position of opening; Said dielectric layer of etching and etching stop layer are until exposing said Semiconductor substrate; In said opening and said groove, form metal level, to form metal damascene structure.
Optional; In the manufacturing approach of said metal damascene structure; The material of said metal silicide layer is a kind of or its combination in cobalt silicide, nickel silicide, tungsten silicide, Titanium silicide, the tantalum silicide; Said metal silicide layer is to utilize the mode of chemical vapour deposition (CVD) or physical vapour deposition (PVD) to form; Said metal silicide layer utilizes the sputter mode to form, and the thickness of said metal silicide layer is 50～
Optional, in the manufacturing approach of said metal damascene structure, the material of said etching stop layer is a kind of or its combination in silicon nitride, silicon oxynitride or the carborundum.
Optional; In the manufacturing approach of said metal damascene structure; Before forming metal silicide layer on the said dielectric layer; Also be included in and form first cover layer on the said dielectric layer, also comprise said first cover layer of etching in the step of said metal silicide layer of etching and the said dielectric layer of part, the said first tectal material is a kind of or its combination in silicon dioxide, silicon nitride or the silicon oxynitride.
Optional; In the manufacturing approach of said metal damascene structure; Before said metal silicide layer of etching and the said dielectric layer of part; Also be included in and form second cover layer on the said metal silicide layer, also comprise said second cover layer of etching in the step of said metal silicide layer of etching and the said dielectric layer of part, the said second tectal material is a silicon oxynitride.
Compared with prior art, the manufacturing approach of metal damascene structure provided by the invention has the following advantages:
The manufacturing approach of said metal damascene structure forms metal silicide layer on dielectric layer; Utilizing etching technics to form in the process of groove; Because the etching selection ratio between dielectric layer and the metal silicide layer is higher; Can avoid the dielectric layer of the metal silicide layer below gas that is etched to destroy, prevent the phenomenon of groove drift angle sphering, avoid the adjacent metal layer to be short-circuited; In addition, because the existence of said metal silicide layer, help preventing that the etching stop layer gas that in the process that forms groove, is etched from destroying.
Description of drawings
Figure 1A to Fig. 1 F is the generalized section of each step corresponding construction of the manufacturing approach of existing metal damascene structure;
The flow chart of the manufacturing approach of the metal damascene structure that Fig. 2 is provided for the embodiment of the invention one;
Fig. 3 A to Fig. 3 H is the generalized section of each step corresponding construction of the manufacturing approach of the metal damascene structure that provided of the embodiment of the invention one;
The flow chart of the manufacturing approach of the metal damascene structure that Fig. 4 is provided for the embodiment of the invention two;
Fig. 5 A to Fig. 6 G is the generalized section of each step corresponding construction of the manufacturing approach of the metal damascene structure that provided of the embodiment of the invention two.
Embodiment
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.Need to prove that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is; A kind of manufacturing approach of metal damascene structure is provided, and the manufacturing approach of said metal damascene structure forms metal silicide layer on dielectric layer, is utilizing etching technics to form in the process of groove; Because the etching selection ratio between dielectric layer and the metal silicide layer is higher; Can avoid the dielectric layer of the metal silicide layer below gas that is etched to destroy, prevent the phenomenon of groove drift angle sphering, avoid the adjacent metal layer to be short-circuited; In addition, because the existence of said metal silicide layer, help preventing that the etching stop layer gas that in the process that forms groove, is etched from destroying.
Embodiment one
Please refer to Fig. 2, the flow chart of the manufacturing approach of the metal damascene structure that it is provided for the embodiment of the invention one, in conjunction with being somebody's turn to do figure, this method may further comprise the steps:
Step S210 provides Semiconductor substrate;
Step S220 forms etching stop layer and dielectric layer successively on said Semiconductor substrate;
Step S230 forms metal silicide layer on said dielectric layer;
Step S240, said metal silicide layer of etching and dielectric layer form opening, and said opening exposes the etching stopping laminar surface;
Step S250 forms packed layer in said opening and on the said metal silicide layer, said packed layer fills up said opening;
Step S260, etched portions packed layer, metal silicide layer and part dielectric layer form groove, and the position of said groove is corresponding with the position of said opening;
Step S270, the etching stop layer that remaining packed layer of etching and said opening expose is until exposing said Semiconductor substrate;
Step S280 forms metal level in said opening and said groove, to form metal damascene structure.
Please refer to 3A～3H, the generalized section of each step corresponding construction of the manufacturing approach of the metal damascene structure that it is provided for the embodiment of the invention one.
Shown in Fig. 3 A, at first, Semiconductor substrate 300 is provided, be formed with metal line in the said Semiconductor substrate 300.Because the present invention relates generally to the manufacture craft of metal damascene structure, thus will not introduce the process that in Semiconductor substrate 300, forms metal line, but those skilled in the art are still this and know.
Shown in Fig. 3 B, then, on said Semiconductor substrate 300, form etching stop layer 310 and dielectric layer 320 successively.Said etching stop layer 310 can be used for preventing metal diffusing in the metal line in dielectric layer 320, and in addition, said etching stop layer 310 can prevent also that in follow-up etching process of carrying out the metal lines in the Semiconductor substrate 300 are etched.
The material of said etching stop layer 310 can be a silicon nitride, and the dielectric layer 320 of itself and follow-up formation has good adhesive force property.It is understandable that, the material of said etching stop layer 310 can also be other can barrier metal the material of diffusion, for example, silicon oxynitride or carborundum etc.The thickness of said etching stop layer 310 can be for 300～and it can form through modes such as chemical vapour deposition (CVD)s
.Said dielectric layer 320 materials are preferably advanced low-k materials, postpone with the resistance capacitance that reduces its parasitic capacitance and metallic copper resistance.Preferable, it is the silicon oxide carbide of black diamond (black diamond) that said dielectric layer 320 adopts the trade mark of Material Used (Applied Materials) company, it can form through modes such as chemical vapour deposition (CVD)s.
Continue with reference to figure 3B, committed step of the present invention is on said dielectric layer 320, to form metal silicide layer 340.The material of said metal silicide layer 340 is a kind of or its combination in any in cobalt silicide, nickel silicide, tungsten silicide, Titanium silicide, the tantalum silicide.The mode of said metal silicide layer 340 chemical vapour deposition (CVD)s capable of using or physical vapour deposition (PVD) forms.Preferably, said metal silicide layer 340 utilizes the sputter mode to form.The thickness of said metal silicide layer 340 is relevant with the etching selection ratio between metal silicide layer 340 and the dielectric layer 320; When etching selection ratio is high more; The thickness of said metal silicide layer 340 is thin more, and certainly, the thickness of said metal silicide layer 340 must be enough to stop etching gas; To avoid in the subsequent etching process gas that is etched of the dielectric layer below the metal silicide layer 340 to destroy; Prevent the phenomenon of groove drift angle sphering, avoid the adjacent metal layer to be short-circuited, and prevent that etching stop layer 310 gas that in forming the process of groove, is etched from destroying.In the present embodiment, the thickness of said metal silicide layer 340 is preferably 50～
In the present embodiment, before forming metal silicide layer 340 on the dielectric layer 320, on dielectric layer 320, form first cover layer 330 in advance.The material of said first cover layer 330 is a kind of or its combinations in silicon dioxide, silicon nitride or the silicon oxynitride.Said first cover layer 330 can be used to protect hardness and the less dielectric layer 320 of dielectric constant; And; The grinding that said first cover layer 330 can be used as the follow-up chemical mechanical milling tech that carries out stops layer, and said first cover layer 330 can form through modes such as chemical vapour deposition (CVD)s.
In the present embodiment, before said metal silicide layer 340 of etching and the dielectric layer 320, also be included in and form second cover layer 350 on the said metal silicide layer 340.The material of said second cover layer 350 is preferably silicon oxynitride.Said second cover layer 350 is in order to antireflection in the follow-up exposure process that carries out, to improve the resolution of exposure imaging technology.
Shown in Fig. 3 C, then, the said metal silicide layer 340 of etching forms opening 320a with dielectric layer 320, and said opening 320a penetrates dielectric layer 320 fully, until exposing said etching stop layer 310 surfaces.In the present embodiment, also comprise said first cover layer 330 of etching and second cover layer 350 in the step of said metal silicide layer 340 of etching and dielectric layer 320.
Shown in Fig. 3 D, afterwards, form packed layer 360 in said opening 320a and on the metal silicide layer 340, said packed layer 360 fills up said opening 320a.The bottom antireflective coating that said packed layer 360 can be made up of the organic polymer of liquid state, said packed layer 360 can prevent in the follow-up exposure process that carries out that the reflex of said opening 320a bottom and evenness are to the influence of groove side surface profile.Subsequently, on said packed layer 360, form patterned light blockage layer 370.
Shown in Fig. 3 E, then, be mask with said patterned light blockage layer 370, etched portions packed layer 360 and metal silicide layer 340.In the present embodiment, in the time of the said metal silicide layer of etching 340, also etching first cover layer 330 and second cover layer 350.
Shown in Fig. 3 F, to continue the said dielectric layer 320 of etched portions and form groove 320b, the position of said groove 320b is corresponding with the position of said opening 320a, and said groove 320b is communicated with opening 320a.Because the etching selection ratio between said dielectric layer 320 and the metal silicide layer 340 is higher; Can avoid the dielectric layer 320 of the said metal silicide layer 340 belows gas that is etched to destroy; Prevent the phenomenon of groove drift angle sphering, avoid the adjacent metal layer to be short-circuited; And help preventing that etching stop layer 310 gas that in the process that forms groove 320b, is etched from destroying.In the present embodiment, in the said dielectric layer 320 of etching, said second cover layer 350 is etched away fully.
Shown in Fig. 3 G, then, the remaining packed layer 360 of etching, simultaneously, the packed layer on the dielectric layer 320 is also removed fully; Next, remove the etching stop layer 310 that said opening 320a exposes, until the surface that exposes said Semiconductor substrate 300.
Shown in Fig. 3 H; At last, on said dielectric layer 320, in the opening 320a and form metal in the groove 320b, utilize chemical mechanical milling tech to remove the metal on the dielectric layer 320 then; Thereby in opening 320a and groove 320b, form metal level 370; And then the formation metal damascene structure, the metal line in said metal level 370 and the Semiconductor substrate 300 electrically connects, and the material of said metal level 370 is preferably copper.
Embodiment two
Please refer to Fig. 4, the flow chart of the manufacturing approach of the metal damascene structure that it is provided for the embodiment of the invention two, in conjunction with being somebody's turn to do figure, this method may further comprise the steps:
Step S410 provides Semiconductor substrate;
Step S420 forms etching stop layer and dielectric layer successively on said Semiconductor substrate;
Step S430 forms metal silicide layer on said dielectric layer;
Step S440, the said dielectric layer of said metal silicide layer of etching and part forms opening;
Step S450 forms packed layer in said opening and on the metal silicide layer, said packed layer fills up said opening;
Step S460, etching packed layer and metal silicide layer form groove, and the position of said groove is corresponding with the position of opening;
Step S470, said dielectric layer of etching and etching stop layer are until exposing said Semiconductor substrate;
Step S480 forms metal level in said opening and said groove, to form metal damascene structure.
Please refer to 5A～5G, the generalized section of each step corresponding construction of the manufacturing approach of the metal damascene structure that it is provided for the embodiment of the invention two.
Shown in Fig. 5 A, at first, Semiconductor substrate 500 is provided, be formed with metal line in the said Semiconductor substrate 500.
Shown in Fig. 5 B, then, on said Semiconductor substrate 500, form etching stop layer 510 and dielectric layer 520 successively.Then, on said dielectric layer 520, form metal silicide layer 540.
In the present embodiment, before forming metal silicide layer 540 on the said dielectric layer 520, on dielectric layer 520, form first cover layer 530 in advance.Before said metal silicide layer 540 of etching and dielectric layer 520, also be included in and form second cover layer 550 on the said metal silicide layer 540.
Shown in Fig. 5 C, afterwards, the said metal silicide layer 540 of etching forms opening 520a with the said dielectric layer 520 of part.Be that with the embodiment of the invention one difference in the present embodiment, said opening 520a does not penetrate said dielectric layer 520 fully.
Shown in Fig. 5 D, thereafter, form packed layer 560 in said opening 520a and on the metal silicide layer 540, said packed layer 560 fills up said opening 520a, and on said packed layer 560, forms patterned light blockage layer 570.
Shown in Fig. 5 E, then, be mask with patterned light blockage layer 570, etching packed layer 560 forms groove 520b with metal silicide layer 540, and the position of said groove 520b is corresponding with the position of opening 520a.
Need to prove, in the present embodiment, in the time of the said metal silicide layer of etching 540, also comprise said first cover layer 530 of etching and second cover layer 550.
Shown in Fig. 5 F, then, the said dielectric layer 520 of etching, and the said etching stop layer 510 of etching are until the surface that exposes said Semiconductor substrate 500.
Shown in Fig. 5 G; At last, on dielectric layer 520, in the opening 520a and form metal in the groove 520b, utilize chemical mechanical milling tech to remove the metal on the dielectric layer 520 then; Thereby in opening 520a and groove 520b, form metal level 570, and then form metal damascene structure.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (24)
1. the manufacturing approach of a metal damascene structure comprises:
Semiconductor substrate is provided;
On said Semiconductor substrate, form etching stop layer and dielectric layer successively;
On said dielectric layer, form metal silicide layer;
Said metal silicide layer of etching and dielectric layer form opening, and said opening exposes the etching stopping laminar surface;
In said opening and on the metal silicide layer, form packed layer, said packed layer fills up said opening;
Etched portions packed layer, metal silicide layer and part dielectric layer form groove, and the position of said groove is corresponding with the position of said opening;
The etching stop layer that remaining packed layer of etching and said opening expose is until exposing Semiconductor substrate;
In said opening and said groove, form metal level, to form metal damascene structure.
2. the manufacturing approach of metal damascene structure as claimed in claim 1 is characterized in that, the material of said metal silicide layer is a kind of or its combination in cobalt silicide, nickel silicide, tungsten silicide, Titanium silicide, the tantalum silicide.
3. the manufacturing approach of metal damascene structure as claimed in claim 1 is characterized in that, said metal silicide layer is to utilize the mode of chemical vapour deposition (CVD) or physical vapour deposition (PVD) to form.
4. the manufacturing approach of metal damascene structure as claimed in claim 3 is characterized in that, said metal silicide layer utilizes the sputter mode to form.
5. the manufacturing approach of metal damascene structure as claimed in claim 1; It is characterized in that the thickness of said metal silicide layer is 50～
6. the manufacturing approach of metal damascene structure as claimed in claim 1 is characterized in that, the material of said etching stop layer is a kind of or its combination in silicon nitride, silicon oxynitride or the carborundum.
7. the manufacturing approach of metal damascene structure as claimed in claim 1 is characterized in that, before forming metal silicide layer on the said dielectric layer, also is included in and forms first cover layer on the said dielectric layer.
8. the manufacturing approach of metal damascene structure as claimed in claim 7 is characterized in that, also comprises said first cover layer of etching in the step of said metal silicide layer of etching and dielectric layer.
9. the manufacturing approach of metal damascene structure as claimed in claim 7 is characterized in that, the said first tectal material is a kind of or its combination in silicon dioxide, silicon nitride or the silicon oxynitride.
10. the manufacturing approach of metal damascene structure as claimed in claim 1 is characterized in that, before said metal silicide layer of etching and the dielectric layer, also is included in and forms second cover layer on the said metal silicide layer.
11. the manufacturing approach of metal damascene structure as claimed in claim 10 is characterized in that, also comprises said second cover layer of etching in the step of said metal silicide layer of etching and dielectric layer.
12. the manufacturing approach of metal damascene structure as claimed in claim 10 is characterized in that, the said second tectal material is a silicon oxynitride.
13. the manufacturing approach of a metal damascene structure comprises:
Semiconductor substrate is provided;
On said Semiconductor substrate, form etching stop layer and dielectric layer successively;
On said dielectric layer, form metal silicide layer;
The said dielectric layer of said metal silicide layer of etching and part forms opening;
In said opening and on the metal silicide layer, form packed layer, said packed layer fills up said opening;
Etching packed layer and metal silicide layer form groove, and the position of said groove is corresponding with the position of opening;
Said dielectric layer of etching and etching stop layer are until exposing said Semiconductor substrate;
In said opening and said groove, form metal level, to form metal damascene structure.
14. the manufacturing approach of metal damascene structure as claimed in claim 13 is characterized in that, the material of said metal silicide layer is a kind of or its combination in cobalt silicide, nickel silicide, tungsten silicide, Titanium silicide, the tantalum silicide.
15. the manufacturing approach of metal damascene structure as claimed in claim 10 is characterized in that, said metal silicide layer is to utilize the mode of chemical vapour deposition (CVD) or physical vapour deposition (PVD) to form.
16. the manufacturing approach of metal damascene structure as claimed in claim 15 is characterized in that, said metal silicide layer utilizes the sputter mode to form.
17. the manufacturing approach of metal damascene structure as claimed in claim 13; It is characterized in that the thickness of said metal silicide layer is 50～
18. the manufacturing approach of metal damascene structure as claimed in claim 13 is characterized in that, the material of said etching stop layer is a kind of or its combination in silicon nitride, silicon oxynitride or the carborundum.
19. the manufacturing approach of metal damascene structure as claimed in claim 13 is characterized in that, before forming metal silicide layer on the said dielectric layer, also is included in and forms first cover layer on the said dielectric layer.
20. the manufacturing approach of metal damascene structure as claimed in claim 19 is characterized in that, also comprises said first cover layer of etching in the step of said metal silicide layer of etching and the said dielectric layer of part.
21. the manufacturing approach of metal damascene structure as claimed in claim 19 is characterized in that, the said first tectal material is a kind of or its combination in silicon dioxide, silicon nitride or the silicon oxynitride.
22. the manufacturing approach of metal damascene structure as claimed in claim 13 is characterized in that, before said metal silicide layer of etching and the said dielectric layer of part, also is included in and forms second cover layer on the said metal silicide layer.
23. the manufacturing approach of metal damascene structure as claimed in claim 22 is characterized in that, also comprises said second cover layer of etching in the step of said metal silicide layer of etching and the said dielectric layer of part.
24. the manufacturing approach of metal damascene structure as claimed in claim 22 is characterized in that, the said second tectal material is a silicon oxynitride.
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| CN2010102307478A CN102339785A (en) | 2010-07-16 | 2010-07-16 | Method for manufacturing metal damascene structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112071804A (en) * | 2020-09-17 | 2020-12-11 | 长江存储科技有限责任公司 | Semiconductor device and manufacturing method thereof |
| CN112271254A (en) * | 2020-10-27 | 2021-01-26 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
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| US20030087514A1 (en) * | 2001-11-02 | 2003-05-08 | Tang Sanh Dang | Hard mask damascene process used to form a semiconductor device |
| CN1812074A (en) * | 2004-12-08 | 2006-08-02 | 三星电子株式会社 | Methods for forming interconnecting structure and semiconductor devices |
| US20070054486A1 (en) * | 2005-09-05 | 2007-03-08 | Ta-Hung Yang | Method for forming opening |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030087514A1 (en) * | 2001-11-02 | 2003-05-08 | Tang Sanh Dang | Hard mask damascene process used to form a semiconductor device |
| CN1812074A (en) * | 2004-12-08 | 2006-08-02 | 三星电子株式会社 | Methods for forming interconnecting structure and semiconductor devices |
| US20070054486A1 (en) * | 2005-09-05 | 2007-03-08 | Ta-Hung Yang | Method for forming opening |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112071804A (en) * | 2020-09-17 | 2020-12-11 | 长江存储科技有限责任公司 | Semiconductor device and manufacturing method thereof |
| CN112271254A (en) * | 2020-10-27 | 2021-01-26 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
| CN112271254B (en) * | 2020-10-27 | 2021-12-28 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
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