CN102332309B

CN102332309B - DRAM (Dynamic Random Access Memory) source synchronization test method and circuit

Info

Publication number: CN102332309B
Application number: CN 201110201791
Authority: CN
Inventors: 李进; 郝福亨
Original assignee: Shandong Sinochip Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2011-07-19
Filing date: 2011-07-19
Publication date: 2013-09-18
Anticipated expiration: 2031-07-19
Also published as: CN102332309A

Abstract

The invention provides a DRAM (Dynamic Random Access Memory) source synchronization test method and circuit solving the technical problems of complexity and low reliability of a test way in the prior art. The circuit is integrated in a DRAM and can precisely measure source synchronization time parameters, and whether the parameters accord with a code standard can be tested through running once. When the test circuit is activated, driving circuits and receiving circuits of a DQ (Data Strobe) base pin and a DQS (Data Strobe Signal) base pin are opened simultaneously. The test circuit comprises an adjustable delay unit, a DQS edge can be moved relative to a DQ edge, and the adjustable delay unit is arranged before the receiving circuit of the DQS base pin; the adjustable delay unit can also be placed behind the receiving circuit of the DQS base pin, and the DQ base pin receives a DQS in a delay way. By using the DRAM source synchronization test method and circuit, a source synchronization test function which can not be realized by a test machine can be restructured effectively; and the advantages of simplicity and convenience in test operation and better precision and reliability areachieved.

Description

The method of testing that a kind of DRAM source is synchronous and test circuit thereof

Technical field

The present invention relates to a kind of DRAM source synchronous method of testing and test circuit thereof.

Background technology

In high-speed DRAM (dynamic RAM) interface, DQS (data gating) signal uses (per 4 or 8 DQ cooperate 1 couple of DQS) with DQ (data) signal.When read operation, DRAM generates DQS and DQ signal.Memory Controller Hub receives the DQS signal, and with DQS signal latch DQ (this mode is called as source synchronous selection pass).In order to guarantee operate as normal, clearly stipulated DQS and DQ time relationship (parametric t DQSQ, tQH).

In the internal memory production test, must detect these parameters and make comparisons with product specification.Owing to reasons such as reception signal lags, tester table can't use an input signal to remove to latch the signal that other receive as gating signal.Can only be with remove to latch respectively DQS signal and DQ signal based on the gating signal of tester table clock signal.This restriction makes tester table can not reappear the real operative scenario of DRAM, and then the measurement of tDQSQ and tQH is also inaccurate.

Commercially available test macro all is to use alternative method to reduce the restriction that can not use the DRAM output signal to be brought as gating signal at present.

Advantest 5501 test macros (Advantest T5501) use the gating group.With one group independently latch signal store the state (for example the time interval be 50ps) of input signal on trickle time at intervals.The gating group is respectively applied for DQS signal and DQ signal.But the gating group remains based on the tester table clock signal.

Can detect the upturned position of DQ signal by this group gating signal, equally also can detect the upturned position of respective cycle DQS signal.Can calculate corresponding parametric t DQSQ of each cycle and tQH by these two results.

The precision of this kind measuring method is subject to the interval between this group gating signal.This group gating signal need cover the upturned position of DQS and DQ signal simultaneously.Because the existence of shake, DQS and DQ signal are all changing constantly with respect to the position of tester table clock signal (CLK), and the change in location between DQS and the DQ is less relatively.Tester table is operated in the CLK territory, so the gating group need cover whole DQS or the DQ shake zone possible with respect to CLK.Otherwise can't detect the upturned position of DQS and DQ signal.

Need place gating signal with very high density in order to obtain higher measuring accuracy, need to have wideer scope to go to cover possible shake zone on the other hand.Both are in conjunction with just requiring each gating group that a large amount of gating signals will be arranged.This requirement makes whole test system very complicated, expensive.

Hui Ruijie V93000 test macro uses another kind of software algorithm to obtain tDQSQ and tQH.Tester table measures DQS and DQ signal with single gating signal, and gating signal is based on the tester table clock signal.Certain tDQSQ of interval or tQH value between the gating signal of DQS and the gating signal of DQ.Keep between the gating signal at interval constant synchronous change gating signal with respect to the position of tester table clock signal then.Record the test result of each mobile gating signal in each test period.In aftertreatment, once test result is qualified with needing only in one-period, just thinks that the test result in this cycle is qualified (eliminating the influence that shake brings).

This method has been brought some problems.At first be because the introducing of sweep test makes the test duration significantly increase; Secondly because each mobile measurement result of each cycle all needs to store and since the restriction of storage space can only measure portion test period.The most important thing is that the result who finally provides too optimizes.Because as long as once qualifiedly just think that test result is qualified, other defective might be because DQS/DQ causes with respect to the shake of CLK, also might be that the parametric t DQSQ that arranges or tQH do not satisfy and cause.Under the extreme case, do not satisfy cause defective except once sporadic qualified other are parameter, it is qualified that net result still can be thought.

Summary of the invention

The present invention aims to provide a kind of DRAM source synchronous method of testing and test circuit thereof, to solve background technology test mode complexity, technical matters that reliability is not high.

Technical scheme of the present invention is as follows:

The method of testing that a kind of DRAM source is synchronous may further comprise the steps:

(1) DRAM is set to test pattern, makes to read the path and write the path to be activated simultaneously;

(2) in reading the path, the clock signal driving data exports the DQ pin to by FIFO, and driving DQS pin sends gating signal;

(3) gating signal sent of the data that receive of step (2) DQ pin and DQS pin directly goes back to and writes the path; DQS signal gating DQ pin writes data;

(4) data that write of DQ pin are compared by the former data that FIFO exports the DQ pin to step (2) after latching, and judge whether the data that write by this DQ pin are correct, and whether qualified, obtain test result if namely judging this DQ pin;

Read the setting of delaying time between writing in the path DQ pin and DQS pin of path or step (3) in above-mentioned steps (2).

Above-mentioned time-delay setting is that the clock signal that drives the DQS pin is arranged clock delay, make DQS along with respect to DQ along movement; Or the gating signal that the DQS pin is sent arranges clock delay, the gating signal that DQ pin time-delay reception DQS pin is sent.

After in the above-mentioned steps (4) two data being compared, can pass through latch cicuit output state information, two data differences even, then latch cicuit set shows that this DQ pin is defective.

If want to try to achieve time relationship definite between each DQ pin and the DQS pin, can be by regulating the clock delay time, repeatedly scanning, and then try to achieve the DQS of this dram chip and the time parameter of DQ.

The present invention also provides a kind of source synchronism detection circuit that is arranged at dram chip inside, comprises the FIFO, data latches, comparison module and the status information latch that arrange separately corresponding to each DQ pin; Reading the path and writing the path and be in state of activation simultaneously of this source synchronism detection circuit reads the path or writes the path to be provided with adjustable time delay unit; Reading on the path, clock signal unit output terminal is connected with the DQS pin with DQ pin drive end respectively, and the output terminal of FIFO is connected with corresponding DQ pin data terminal; Writing on the path, DQ pin data terminal is connected with corresponding data latches with the DQS pin, the output terminal of data latches and the output terminal of FIFO are connected to comparison module (comparing with the former data that export the DQ pin to FIFO in this clock period), and the comparison module output terminal is connected to the status information latch to output test result.

Above-mentioned adjustable time delay unit is arranged between clock signal output terminal and the DQS pin or is arranged on the DQS gating path.

Also can consider in each DQ pin or DQS pin, all to arrange separately adjustable time delay unit.

The present invention has the following advantages:

1, test operation is easy, and precision, reliability are better.

2, can effectively reconstruct the source synchronism detection function that tester table can't be realized.This circuit is activated in product test, and it will record the phenomenon of any violation tDQSQ and tQH standard.The result can by the test pattern interface read and be used for after aftertreatment or decision-making.

Description of drawings

Fig. 1 is for reading path synoptic diagram (path is write in the dotted line representative);

Fig. 2 is for writing path synoptic diagram (path is read in the dotted line representative);

Fig. 3 is structure principle chart of the present invention;

Fig. 4 is the definition of time parameter tDQSQ among the present invention and tQH.

Embodiment

The present invention provides an additional test circuit in DRAM inside, this circuit can effectively reconstruct the source synchronism detection function that tester table can't be realized.This circuit is activated in product test, and it will record the phenomenon of any violation tDQSQ and tQH standard.The result can by the test pattern interface read and be used for after aftertreatment or decision-making.

The present invention is one and is integrated in the circuit that source parameter lock in time can accurately be measured in DRAM inside that the single operation just can test out parameter and whether meet codes and standards.When this test circuit is activated, open driving circuit and the receiving circuit of DQ pin and DQS pin simultaneously.This test circuit comprises adjustable time delay unit, can be with respect to DQ along mobile DQS edge, and this adjustable time delay unit is positioned at before the DQS pin driving circuit; Adjustable time delay unit also can be placed on after the DQS pin receiving circuit, and the time-delay of DQ pin receives the DQS signal.

" alignment+relatively " module is by the corresponding FIFO of each DQ pin, and storage outputs to the data of DQ pin, and with receive data and compare to judge whether receive data correct." alignment+compare " module also can be in other optional positions in DRAM internal data path.Also can the join together data of more a plurality of DQ pins.And may multiplexing built-in test comparator circuit.

The result is to latch cicuit (status information latch) in " alignment+compare " module output, is used for the fail message that record " alignment+compare " produces.Canned data can test interface be read.Latch cicuit can test interface reset.

When beginning to test at every turn, activate simultaneously and read the path and write the path, reseting lock storaging circuit is adjusted clock delay to the codes and standards value, moves test procedure, reads the information of status information latch stores, to judge whether relevant parameter meets code requirement.

Can carry out repeatedly sweep test, change the delay time of adjustable time delay unit, repeat the testing process of last clock period, can record the concrete numerical value (by---failure border) of measured parameter.

What Fig. 1 showed is common block diagram and corresponding source parameter-definition lock in time of reading the path of DRAM.The clock signal driving data that tester table or Memory Controller Hub provide outputs to the DQ pin by FIFO (fifo buffer).Data are alignd with the clock signal edge.Clock signal is exported by the DQS pin.

The DQS signal is in the gating signal of Memory Controller Hub end as data, so the time relationship between DQS and the DQ is very important.Parametric t DQSQ and tQH have been defined for this reason.

Fig. 2 shows be DRAM common write the path.DQS and DQ are as the input supervisor.The DQS pin receives the gating signal of being sent by Memory Controller Hub and is used for DQ pin, the input signal (source synchronous selection pass) that gating DQ pin receives as clock signal.Therefore the edge of the data strobe signal that Memory Controller Hub sends aligns with the mid point of data signal data eye pattern, does not need time-delay can directly be used for the gated data signal.

Fig. 3 is a kind of realization of the present invention.A special test pattern is set in DRAM inside.When this test pattern is activated, read the path and write the path to be activated simultaneously.DQS and DQ data output to respective pin by chip internal when read operation.Owing to write the path and also be in state of activation, the output data receive again, and the DQS signal of input can be used for gated data.

In the CLK path, add an adjustable delay unit, can adjust the temporal distance of DQS and DQ (can make the DQS edge by DQ data eye (data-eye) by changing time-delay).Measure for tDQSQ, time-delay is set to the maximal value that standard allows.If mean DQ and DQS complete matching in general operation, DQS has been delayed time the tDQSQ time now, and data can correctly be latched.If under certain conditions, the DQ data are delayed time to be exported above the tDQSQ time, and gating appears at the moment that data are being overturn, and the data of mistake might be latched.

After latching, the data that receive deliver to " alignment relatively " module.The only work when source synchronism detection function is activated of this module.This functions of modules is storage output data and makes comparisons with the reception data that obtain afterwards.Do not do any action if two data are identical, if different, it is improper to mean that the time-delay of DQS gating signal arranges, and misdata is latched.This moment is with inefficacy latch of set.This inefficacy latch can reset when test procedure begins or by the test pattern interface.Sensing latch device content illustrated that tested time parameter does not meet code requirement in test process if latch is set when test procedure finished.For each data pins arranges an inefficacy latch, can pick out specifically is which pin is defective.

Delay unit is set to different values, and the repeated test flow process is carried out sweep test, can obtain the explicit value of tDQSQ.Delay unit is set to the standard permissible value, and the operation test once then can detect measured parameter and whether meet code requirement.

The precision of this measuring method is subject to RX path.The RX path of this method is just generally write the path.So potential inaccuracy can go out by measurement parameter detecting input time, and can compensate the output parameter of final measurement with this.Specifically can measure each DQ in advance, the DQS pin is write the path time parameter, is used for compensating when late time data is handled writing the error that the imperfect designing institute in path brings.

Claims

1. method of testing that the DRAM source is synchronous may further comprise the steps:

2. method according to claim 1 is characterized in that:

Reading the setting of delaying time in the path in step (2), is that the clock signal that drives the DQS pin is arranged clock delay, make DQS along with respect to DQ along movement;

Writing the setting of delaying time in the path in step (3), is that the gating signal that the DQS pin sends is arranged clock delay, makes the time-delay of DQ pin receive the gating signal that the DQS pin sends.

3. method according to claim 2 is characterized in that:

After in the step (4) two data being compared, by latch cicuit output state information, two data differences even, then latch cicuit set shows that this DQ pin is defective.

4. method according to claim 3 is characterized in that: by regulating the clock delay time, repeatedly scan, and then try to achieve the DQS of this dram chip and the time parameter of DQ.

5. be arranged at the source synchronism detection circuit of dram chip inside, it is characterized in that: comprise the FIFO, data latches, comparison module and the status information latch that arrange separately corresponding to each DQ pin; Reading the path and writing the path and be in state of activation simultaneously of this source synchronism detection circuit reads the path or writes the path to be provided with adjustable time delay unit; Reading on the path, clock signal unit output terminal is connected with the DQS pin with DQ pin drive end respectively, and the output terminal of FIFO is connected with corresponding DQ pin data terminal; Writing on the path, DQ pin data terminal is connected with corresponding data latches with the DQS pin, and the output terminal of data latches and the output terminal of described FIFO are connected to comparison module, and the comparison module output terminal is connected to the status information latch to output test result.

6. source according to claim 5 synchronism detection circuit, it is characterized in that: the described path of reading is provided with adjustable time delay unit, specifically is to be arranged between clock signal output terminal and the DQS pin; The described path of writing is provided with adjustable time delay unit, specifically is to be arranged on the DQS gating path.