CN106997784B - Dynamic random access memory and test method for carrying system thereof - Google Patents
Dynamic random access memory and test method for carrying system thereof Download PDFInfo
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- CN106997784B CN106997784B CN201610051207.0A CN201610051207A CN106997784B CN 106997784 B CN106997784 B CN 106997784B CN 201610051207 A CN201610051207 A CN 201610051207A CN 106997784 B CN106997784 B CN 106997784B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56004—Pattern generation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5606—Error catch memory
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Abstract
The invention provides a test method, is used for testing the system carrying dynamic random access memory, the above-mentioned method includes while the dynamic random access memory is operated in the test mode, every a predetermined interval time, add a variable quantity to the output signal of one of a plurality of different output pins of the dynamic random access memory, or the input signal of one of a plurality of different input pins of the dynamic random access memory; recording the time of adding the output signal of the output pin or the input signal of the input pin into the variation and the variation to test data; and when the system fails, finding out the corresponding input pin or output pin and the variation when the system fails according to the test data.
Description
Technical Field
The present invention relates to a test method, and more particularly to a test method for a system with a dynamic random access memory.
Background
The current system with dram is commonly used in notebook computers, personal computers or mobile devices. When the compatibility problem occurs between the system and the loaded dram, generally, it is not possible to effectively find out which pins (pins) of the loaded dram the compatibility problem occurs, and the cause of the compatibility problem occurs at the pins.
Because the pin and the reason for the compatibility problem cannot be found out effectively, the debugging process for the compatibility problem will consume much time and cost, and further cause burden to the whole research and development process.
Disclosure of Invention
In order to solve the problem of debugging the pin with compatibility problem, the invention provides a dynamic random access memory and a test method for carrying the system.
The invention provides a dynamic random access memory, which comprises a plurality of input pins and a plurality of output pins; a main circuit coupled to the input pins and the output pins; and a control circuit, when the dynamic random access memory operates in a test mode, the control circuit outputs the main circuit to the output signal of one of the plurality of different output pins or adds a variation to the input signal received by the main circuit from one of the plurality of different input pins at a predetermined interval time. The control circuit records the output signals of the output pins and the input signals of the input pins, the time for adding the variation and the variation.
The invention provides a test method of a system carrying a dynamic random access memory, which comprises the steps of adding a variation quantity to an output signal of one of a plurality of different output pins of the dynamic random access memory or an input signal of one of a plurality of different input pins of the dynamic random access memory at intervals of a preset interval when the dynamic random access memory operates in a test mode; recording the time of adding the output signals of the output pins or the input signals of the input pins into the variation and the variation to test data; and when the system fails, finding out the corresponding input pin or output pin and the variation when the system fails according to the test data.
In an embodiment, the testing method of the system with a dynamic random access memory further includes calculating an accumulated receiving number of times that the dynamic random access memory receives the refresh signal (refresh); and setting the time required by the DRAM to receive the refresh signals of the predetermined number as the predetermined interval time when the accumulated receiving times accords with the predetermined number.
In another embodiment, the method for testing the system with the dram further includes finding out the variation corresponding to the system failure according to a lookup table, and determining a probability of the variation corresponding to the system failure in an operation mode other than the test mode.
The embodiment of the invention can find out the pin and the variation quantity of the dynamic random access memory causing the problem based on the time point of the compatibility problem or the failure according to the test data stored in the dynamic random access memory when the dynamic random access memory and an electronic system carried by the dynamic random access memory have the compatibility problem or the failure when the dynamic random access memory operates in a test mode, thereby clearly defining the position and the reason of the problem.Drawings
FIG. 1 is a diagram of a DRAM according to an embodiment of the present invention.
FIG. 2A is a diagram illustrating an operation of adjusting an input pin of a DRAM according to an embodiment of the present invention.
FIG. 2B is a diagram illustrating an operation of adjusting output pins of a DRAM according to an embodiment of the present invention.
FIG. 3 is a timing diagram illustrating adjusting the delay of the input pin of the DRAM according to one embodiment of the present invention.
FIG. 4 is a timing diagram illustrating the adjustment of the signal strength of the input pin of the DRAM according to an embodiment of the present invention.
FIGS. 5A and 5B are flow charts of testing a system with a DRAM according to an embodiment of the invention.
Reference numerals:
100-dynamic random access memory
101-main circuit
102-control Circuit
103-I/O pin
1011-1013 input pin
1021-1023 output pin
t0-t 3-time point
R1-R3, T1-T3-primary signal
D-amount of variation
300-timing diagram
301-charge 303-input signal
td-time delay
400-timing diagram
401-403-input signal
Vd-voltage deviation value
500A, 500B-flow charts
501 step 505-
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
FIG. 1 is a diagram of a dynamic random access memory 100 according to an embodiment of the invention. The DRAM 100 includes a main circuit 101, a control circuit 102 and an input/output pin 103, and the input/output pin 103 includes input pins 1011-1013 and output pins 1021-1023. The main circuit 101 is coupled to the input/output pin 103 through the control circuit 102.
In some embodiments, the dram 100 is mounted to an electronic system, and when the dram 100 operates in a test mode, the control circuit 102 adds a variation to the input signal received by the main circuit 101 from one of the input pins 1011-1013 at predetermined time intervals, as shown in fig. 2A (the test mode starts at time t 1); or adding the variation to the output signal outputted from the main circuit 101 to one of the output pins 1021-1023, as shown in FIG. 2B (the test mode starts at time t 1); the control circuit 102 records the signals of the input pins 1011-1013 and the signals of the output pins 1021-1023, and adds the time point of the variation and the variation.
In fig. 2A, the test mode starts at time t1, and the input pins 1011 to 1013 are respectively added with a variance D at time t1 to t3, and the time interval between time t1 and time t3 is the predetermined interval. Taking the input pin 1011 as an example, the control circuit 102 sends the original signal R1 received by the input pin 1011 to the main circuit 101 at time points t2 and t 3; at time t1, the original signal R1 received by the input pin 1011 is added with the variance D, and then transmitted to the main circuit 101, and at the same time, the time t1 at which the signal of the input pin 1011 is added with the variance D and the variance D are recorded into a test data. As shown in FIG. 2A, the control circuit 102 adds the variance D to the original signals R1, R2, or R3 received by one of the input pins 1011-1013 at predetermined intervals, so as to test the influence of the variance D on the respective input pins 1011-1013 at different time points. The control circuit 102 further records the time point when the signals of the input pins 1011-1013 are added to the variation D and the variation D to the test data, so as to find out the input pin and the variation D causing the compatibility problem or the failure between the electronic system and the dram 100 according to the test data when the compatibility problem or the failure occurs between the electronic system and the dram 100.
In fig. 2B, the test mode starts at time t1, the output pins 1021-1023 add the variance D at time t1-t3, and the time interval between adjacent time points of time t1-t3 is the predetermined interval. Taking the output pin 1021 as an example, the control circuit 102 sends the original signal T1 sent by the main circuit 101 to the output pin 1021 at time points T1 and T2; at time T3, the original signal T1 sent by the main circuit 101 is added with the variance D, and then transmitted to the output pin 1021, and at the same time, the time T3 when the signal at the output pin 1021 is added with the variance D and the variance D are recorded into the test data. As shown in FIG. 2B, the control circuit 102 adds the variation D to the original signals T1, T2, or T3 sent by the main circuit 101 to one of the output pins 1021-1023 at predetermined intervals, so as to test the influence of the variation D on the respective output pins 1021-1023 at different time points. The control circuit 102 further records the time point when the signals of the output pins 1021-1023 are added to the variation D and the variation D to the test data, so as to find out the output pin and the variation D causing the compatibility problem or the failure of the electronic system and the DRAM 100 according to the test data when the compatibility problem or the failure of the electronic system and the DRAM 100 occurs.
In some embodiments, when the dram 100 is operated in the test mode, the control circuit 102 may add the variation D to the signal of one of the i/o pins 103 after every predetermined interval in any order, and record the time point when the signal of the respective pin of the i/o pins 103 is added to the variation D and the variation D to the test data. In some embodiments, when the dram 100 is operated in a test mode, the signals of all the pins of the i/o pins 103 are added with the variance D at the predetermined interval by the above method, and the time point when the signal of the pin is added with the variance D and the variance D are recorded into the test data respectively.
In some embodiments, the predetermined time is defined by a timing circuit of the control circuit 102 when the dram 100 is operating in the test mode. In other embodiments, the predetermined time is generated by a counter circuit of the control circuit 102 when the dram 100 is operating in the test mode, the counter circuit counts a cumulative number of times of receiving the refresh signal (refresh) from the electronic system by the dram 100, wherein the counter circuit sets the time required for the dram 100 to receive the predetermined number of refresh signals as the predetermined interval time when the cumulative number of times of receiving meets a predetermined number. In some embodiments, the predetermined interval is a period of time that is artificially recognizable when the dram 100 is operated in the test mode, such as five minutes, but the invention is not limited thereto.
In some embodiments, the variance D is a signal time delay. FIG. 3 is a timing diagram 300 illustrating the adjustment of the signal delay of the input pin of the DRAM 100 according to one embodiment of the present invention. In fig. 3, the test mode starts at time t1, and the time interval between time t1 and time t3 is the predetermined interval, and the input signal 301 of the input pin 1011, the input signal 302 of the input pin 1012 and the input signal 303 of the input pin 1013 are added with a variance by the control circuit 102 at time t1 to time t3, respectively. In this embodiment, the variance is a signal time delay td, and the control circuit 102 records the time point when the signal of the input pins 1011-1013 is added to the signal time delay td and the signal time delay td to a test data. In this embodiment, when the dram 100 is operating in the test mode, if the compatibility problem or failure occurs between the electronic system and the dram 100, the input pin and the signal time delay td that cause the compatibility problem or failure between the electronic system and the dram 100 can be found according to the test data.
In some embodiments, when the dram 100 is operated in the test mode, one of the output pins of the dram 100 may also add the signal time delay td after every predetermined time interval through the control circuit 102, and the control circuit 102 records the test data with the time point at which the signal of the output pin is added to the signal time delay td and the signal time delay td.
In some embodiments, the variation D is a current offset or a voltage offset. FIG. 4 is a timing diagram 400 illustrating the adjustment of the offset voltage of the voltage signal at the input pin of the DRAM 100 according to an embodiment of the present invention. In fig. 4, the test mode starts at time t1, and the time interval between time t1 and time t3 is the predetermined interval, and the input signal 401 at the input pin 1011, the input signal 402 at the input pin 1012, and the input signal 403 at the input pin 1013 are varied by the control circuit 102 at time t1 to t 3. In this embodiment, the variation is a voltage deviation Vd, and the control circuit 102 records the time point of the voltage signal at the input pins 1011-1013 to the voltage deviation Vd and the voltage deviation Vd to a test data. In this embodiment, when the dram 100 is operating in the test mode, if the compatibility problem or failure occurs between the electronic system and the dram 100, the input pin and the voltage offset Vd, which cause the compatibility problem or failure between the electronic system and the dram 100, can be found according to the test data.
In some embodiments, when the dram 100 operates in the test mode, one of the output pins of the dram 100 may also add the voltage deviation Vd after every predetermined time interval by the control circuit 102, and the control circuit 102 records the test data with the time point at which the signal of the output pin is added to the voltage deviation Vd and the voltage deviation Vd, respectively.
In some embodiments, when the dram 100 is operated in the test mode, the variation of the signals added to the different pins of the i/o pin 103 by the control circuit 102 may be of different nature, and the control circuit 102 records the time point at which the signals of the i/o pin 103 are varied and the variation to the test data respectively. For example, when the dram 100 is operating in the test mode, the control circuit 102 may add a signal time delay to a signal at one of the input pins 103; after the predetermined interval, the control circuit 102 may add the voltage offset or the current offset to the signal of the other input pin or the output pin of the input/output pin 103.
In some embodiments, when the dram 100 is operated in the test mode, if the control circuit 102 adds a variation amount of the signal of the input/output pin 103 to cause a compatibility problem or a failure between the electronic system and the dram 100, the signal of the input/output pin 103 of the dram 100 can be found according to a lookup table, and after the electronic system is started, the probability of the variation amount occurring in an operation mode other than the test mode (i.e., the probability of the dram 100 causing the failure of the electronic system) of the dram 100 is determined, so as to obtain the yield of the dram 100 applied to the electronic system in an operation mode other than the test mode.
In some embodiments, the lookup table is generated by measuring signals at input/output pins of a predetermined number of the same dram (e.g., the same dram as dram 100) under a predetermined mode of operation of a test system. Then, the maximum deviation (i.e. variation) of the signals of the input/output pins of the plurality of drams and the probability of the occurrence of the plurality of variations are recorded and made into the lookup table, and the lookup table is used for corresponding to the variation and the occurrence probability of the variation.
FIG. 5A is a flowchart 500A illustrating a test procedure of a system with a DRAM according to an embodiment of the present invention. In step 501, an electronic system with a dram is turned on and the dram is operated in a test mode. In step 502, a variance is set. In step 503, at predetermined intervals, the dram adds the variation to one of the input/output pins of the dram, and records the time point when the signal of each input/output pin is added to the variation and the variation to test data; and at the same time, detecting whether the electronic system carrying the dynamic random access memory is invalid, if the electronic system is not invalid, the step is entered into 502; if the electronic system fails, step 504 is performed. In step 504, the input/output pins and the variation causing the failure of the electronic system are found from the test data according to the time point of the failure of the electronic system.
FIG. 5B is a flowchart 500B illustrating the testing of a system with a DRAM according to an embodiment of the present invention. Steps 501 to 503 are the same as fig. 5A, and are not described herein again. The content of step 505, in addition to the content of step 504 of fig. 5A, further includes obtaining a signal of the input/output pin of the dram according to a lookup table, and determining a probability of the variation when the dram is applied to the electronic system in an operation mode other than the test mode after the electronic system is started.
Some embodiments provided by the present invention can find out pins and variation of the dram causing problems based on a time point of occurrence of a compatibility problem or a failure according to a test data stored in the dram when the dram and an electronic system mounted thereon have the compatibility problem or the failure while the dram is operating in a test mode, thereby clearly defining a location and a cause of the problem.
Although the present invention has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A dynamic random access memory, comprising:
a plurality of input pins and a plurality of output pins;
a main circuit coupled to the input pins and the output pins; and
a control circuit, when the DRAM is operated in a test mode, the main circuit outputs the output signal of one of the output pins to be different or adds a variation to the input signal received by the main circuit from one of the input pins to be different at a predetermined interval;
the control circuit records the time when the output signals of the output pins or the input signals of the input pins are added into the variation and the variation to test data;
wherein the test data is configured to indicate an input pin or an output pin causing the DRAM failure and the variation amount based on a time point when the DRAM failure occurred.
2. The dynamic random access memory of claim 1,
the control circuit further comprises a counter circuit for counting an accumulated receiving frequency of the DRAM receiving the refresh signal;
the counter circuit sets the time required by the DRAM to receive the refresh signals of the preset number as the preset interval time when the accumulated receiving times accords with the preset number.
3. The dram of claim 1 wherein the variation is a current offset or a voltage offset.
4. The dynamic random access memory of claim 1 wherein the variation is a signal time delay.
5. A method for testing a system having a dynamic random access memory mounted thereon, comprising:
when the dynamic random access memory is operated in a test mode, adding a variation quantity to an output signal of one of a plurality of different output pins of the dynamic random access memory or an input signal of one of a plurality of different input pins of the dynamic random access memory at intervals of a preset interval;
recording the time of adding the output signals of the output pins or the input signals of the input pins into the variation and the variation to test data; and
when the system fails, the input pin or the output pin causing the system failure and the variation are found out from the test data according to the time point of the system failure.
6. The method of claim 5, further comprising:
calculating an accumulated receiving frequency of the DRAM receiving the refresh signal; and
when the accumulated receiving times accords with a predetermined number, the time required by the DRAM to receive the refresh signals of the predetermined number is set as the predetermined interval time.
7. The method of claim 5, further comprising:
and finding out the signals of the output pins and the input pins of the dynamic random access memory according to a lookup table according to the variation corresponding to the system failure, wherein the probability of the variation corresponding to the system failure occurs in an operation mode except the test mode.
8. The method as claimed in claim 5, wherein the variation is a current offset or a voltage offset.
9. The method of claim 5, wherein the variance is a signal time delay.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1714295A (en) * | 2002-10-29 | 2005-12-28 | 艾罗弗莱克斯国际有限公司 | A method of and apparatus for testing for integrated circuit contact defects |
| CN101034127A (en) * | 2006-02-16 | 2007-09-12 | 奇梦达股份公司 | Verifying individual probe contact using shared tester channels |
| CN101226777A (en) * | 2007-01-15 | 2008-07-23 | 华邦电子股份有限公司 | Storage apparatus and apparatus with reduced test stitch as well as test approach thereof |
| CN102332309A (en) * | 2011-07-19 | 2012-01-25 | 山东华芯半导体有限公司 | DRAM (Dynamic Random Access Memory) source synchronization test method and circuit |
| CN202205465U (en) * | 2011-07-19 | 2012-04-25 | 西安华芯半导体有限公司 | Circuit for testing DRAM (Dynamic Random Access Memory) source synchronization |
| JP4952260B2 (en) * | 2007-01-12 | 2012-06-13 | 横河電機株式会社 | Memory test equipment |
| CN103390432A (en) * | 2012-05-08 | 2013-11-13 | 三星电子株式会社 | Architecture, system and method for testing resistive type memory |
-
2016
- 2016-01-26 CN CN201610051207.0A patent/CN106997784B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1714295A (en) * | 2002-10-29 | 2005-12-28 | 艾罗弗莱克斯国际有限公司 | A method of and apparatus for testing for integrated circuit contact defects |
| CN101034127A (en) * | 2006-02-16 | 2007-09-12 | 奇梦达股份公司 | Verifying individual probe contact using shared tester channels |
| JP4952260B2 (en) * | 2007-01-12 | 2012-06-13 | 横河電機株式会社 | Memory test equipment |
| CN101226777A (en) * | 2007-01-15 | 2008-07-23 | 华邦电子股份有限公司 | Storage apparatus and apparatus with reduced test stitch as well as test approach thereof |
| CN102332309A (en) * | 2011-07-19 | 2012-01-25 | 山东华芯半导体有限公司 | DRAM (Dynamic Random Access Memory) source synchronization test method and circuit |
| CN202205465U (en) * | 2011-07-19 | 2012-04-25 | 西安华芯半导体有限公司 | Circuit for testing DRAM (Dynamic Random Access Memory) source synchronization |
| CN103390432A (en) * | 2012-05-08 | 2013-11-13 | 三星电子株式会社 | Architecture, system and method for testing resistive type memory |
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