CN102323959A - Acquisition card for time-resolved photon counting imaging - Google Patents

Abstract

The invention relates to an acquisition card for time-resolved photon counting imaging, comprising a photon arrival timing signal generation circuit, a pulse peak synchronous acquisition unit, a start signal generation circuit, a constant temperature crystal oscillator clock circuit, a programmable logic device, a digital signal processor, a time digital The converter chip and the communication interface circuit, the input terminal of the pulse peak acquisition unit is connected to the output terminal of the detector, the pulse peak acquisition unit communicates with the programmable logic device, and the output terminal of the detector is input to the programmable logic device through the photon arrival timing signal generation circuit. In the logic device, the output end of the start signal generation circuit is connected with the programmable logic device and the time-to-digital converter chip, and the output end of the constant temperature crystal oscillator clock circuit is connected with the programmable logic device and the time-to-digital converter chip. The invention solves the lack of a photon counting imaging method with time resolution in the existing photon counting methods, and the invention has the advantages of high time resolution and high space resolution.

Description

Acquisition Cards for Time-Resolved Photon Counting Imaging

technical field

The invention relates to the field of low-light imaging technology, in particular to an acquisition card for time-resolved photon counting imaging in the photon counting imaging technology in the low-light imaging technology field.

Background technique

With the wide application of low-light imaging in astronomical observation, satellite remote sensing, biomedical imaging and other fields, the sensitivity requirements for low-light imaging detection are getting higher and higher. Photon counting imaging is an imaging method for extremely weak targets with extremely high Therefore, the photon counting imaging method can be applied in many fields, such as astronomical observation, satellite remote sensing, biomedical imaging, nuclear radiation imaging, space ultraviolet imaging, etc. The detectors currently used for photon counting imaging mainly consist of photomultiplier tubes (PMTs), single photon avalanche diodes (SPADs), and microchannel plates (MCPs). Among them, photomultiplier tube (PMT) and avalanche photodiode (APD) belong to unit detectors, so optical-mechanical scanning is required to realize imaging, and the real-time imaging, time resolution, and spatial resolution are not high. Based on the microchannel plate (MCP), which has an area array structure, photon counting imaging can be realized through position-sensitive anode readout, which has the advantages of high signal-to-noise ratio, high sensitivity, wide dynamic range, and good drift resistance. For example, based on microchannel plate ( The position-sensitive anode detector of MCP) is mainly composed of cascaded MCP and position-sensitive anode. The photon counting imaging method of the position-sensitive anode detector based on MCP is that when the detector detects a photon, the position-sensitive anode outputs multiple electronic pulse signals. Multiple pulse signals pass through the electronic readout system to measure the position coordinates of the detected photons. After a certain period of time accumulation, a large number of photon position coordinate data are measured, and photon counting images are synthesized according to the photon counting at different positions. Position-sensitive anodes mainly include Wedge and Strip Anode, Vernier Anode, Cross Strip Anode, Multi-Anode Microchannel Array (MAMA) and Resistive Anode, etc. Literature (FENGBing , KANG Ke-Jun, WANG Kui-Lu, et al.Nucl.Instrum.Meth.A, 2004, 535:546) reported multi-anode microchannel array (MAMA) photon counting imaging. Literature (Lapington J S, Sanderson B, Worth L B C, et al. Nucl. Instr. Meth A, 2002, 447: 250) reported photon counting imaging using a vernier position sensitive anode. Literature (MIAO Zhen-hua, ZHAOBao-sheng, ZHANG Xing-hua, et al. Chinese Physics Letters, 2008, 25(7), 2698) reported photon counting imaging using WSA anode. The patent (application number: 200710018631.6 single photon counting imager) uses a three-electrode WSA anode for photon counting imaging. However, it adopts waveform digital counting, collects multiple pulse signals output by the anode for full waveform acquisition, and then uses software for peak detection. Since this method needs to collect a large amount of useless data, the counting rate is not high.

In the literature reported so far, no time-resolved photon counting is involved. Time-resolved photon counting imaging, because it can reflect the transformation process of imaging targets over time, has very important scientific research value and can be applied to more fields, such as fluorescence lifetime imaging, biological and medical imaging, lidar, ultraviolet Early warning, diffusion optical tomography, single-molecule fluorescence spectroscopy, time-resolved fluorescence microscopy, etc.

Contents of the invention

In order to solve the lack of a time-resolved photon counting imaging method in the existing photon counting methods, the present invention proposes an acquisition card for time-resolved photon counting imaging.

Technical solution of the present invention is as follows:

The acquisition card for time-resolved photon counting imaging is special in that the acquisition card includes a photon arrival timing signal generation circuit, a pulse peak synchronous acquisition unit, a start signal generation circuit, a constant temperature crystal oscillator clock circuit (OCXO), a programmable Logic device (FPGA), digital signal processor (DSP), time-to-digital converter chip (TDC) and communication interface circuit,

The input terminal of the pulse peak acquisition unit is connected to the output end of the detector, and the pulse peak acquisition unit communicates with the programmable logic device,

The output end of the detector is input to the programmable logic device (FPGA) through the photon arrival timing signal generation circuit,

The output end of described start signal generating circuit is connected with programmable logic device (FPGA) and time-to-digital converter chip (TDC),

The output end of the constant temperature crystal oscillator clock circuit (OCXO) is connected with a programmable logic device (FPGA) and a time-to-digital converter chip (TDC),

The time-to-digital converter chip (TDC) communicates with a programmable logic device (FPGA),

The digital signal processor (DSP) and the programmable logic device (FPGA) communicate with each other, and the programmable logic device (FPGA) is connected with the computer through a communication interface circuit.

The above-mentioned photon arrival timing signal generating circuit includes a multi-channel pulse summation circuit, a peak detection circuit, a low threshold comparison circuit, a high threshold comparison circuit and a D flip-flop F1, and the multi-channel pulse summation circuit is an operation connected in a summation form Amplifier U1, the input terminal of the operational amplifier U1 receives multiple pulse signals output by the detector, and the output summation signal of the operational amplifier U1 is sent to the peak detection circuit, the low threshold comparison circuit and the high threshold comparison circuit respectively; The detection circuit is composed of a resistor R4, a capacitor C1 and a first comparator U2; the low threshold comparison circuit is composed of a first potentiometer R5 and a second comparator U3; the high threshold comparison circuit is composed of a second potentiometer R6 and a second comparator U3 Three comparators U4 are composed; the peak detection circuit outputs to the CLK end of the D flip-flop F1, the low threshold comparison circuit outputs to the D end of the D flip-flop F1, and the Q end of the D flip-flop F1 outputs a photon arrival timing signal, the The Q terminal of the D flip-flop F1 passes through the first NOT gate U6 and the second NOT gate U7 in turn, and then the output signal of the high threshold comparison circuit passes through the OR gate U5, and the output terminal of the OR gate U5 is connected to the RST terminal of the D flip-flop F1 .

The above-mentioned pulse peak acquisition unit includes multiple parallel pulse peak acquisition circuits, and the pulse peak acquisition circuit includes sequentially series-connected peak hold chips, amplifiers and A/D converters, the amplifier adopts a follower mode, and all A/D conversion The output terminal of the device is connected to the conversion terminal CLK, and the holding terminal of the peak holding chip is connected to the discharge terminal.

The above-mentioned programmable logic device (FPGA) includes a peak acquisition control unit, a position decoding unit, a time measurement unit, a data cache unit and a communication control unit;

The peak value acquisition control unit is used to control the pulse peak value acquisition unit to perform peak synchronous measurement of the input pulse peak value, and transmit the measured peak value data to the position decoding unit;

The position decoding unit is used to cooperate with a digital signal processor (DSP) to solve the position coordinate data of the photon;

The time measurement unit cooperates with a time-to-digital converter chip (TDC) to measure the arrival time data of photons;

The data cache unit is used to store the position coordinate data of the photon and the arrival time data of the photon;

The communication control unit is used to control the data cache unit to send the photon arrival time data and photon position coordinate data to the computer.

The above-mentioned time measurement unit includes a counter, a control logic unit and a time calculation unit, the photon arrival timing signal, the start signal of the start signal generation circuit and the synchronization signal input control logic unit, the clock signal of the constant temperature crystal oscillator clock circuit, and the start signal of the start signal generation circuit 1. The control signal of the control logic unit is input to the counter, and the time-to-digital converter chip (TDC), the counter and the output end of the control logic unit are connected to the time calculation unit.

The clock signal of the above-mentioned constant temperature crystal oscillator clock circuit is input to the start end of the time-to-digital converter chip (TDC), the start signal of the start signal generation circuit is input to the stop1 end of the time-to-digital converter chip (TDC), and the photon arrival timing signal is input to the time-to-digital converter Chip (TDC) stop2 terminal.

The above-mentioned constant temperature crystal oscillator clock circuit (OCXO) adopts MDB59P3T, the peak holding chip is a PKD01 chip, the A/D converter is an AD9240 chip, and the time-to-digital converter chip (TDC) is a TDC-GPX chip.

The advantages that the present invention has:

1. With time-resolved photon counting imaging, the present invention continuously records the arrival time of photons and the position coordinates of photons. The photon counting image of any time slice can be reconstructed through data processing, and then reflect the change process of the imaging target over time.

2. The time resolution is high. The measurement of photon arrival time in the present invention adopts the method of combining coarse time measurement and fine time measurement. The coarse time of photon arrival is measured by counting the high-frequency stability constant temperature crystal oscillator clock circuit, and the fine time of photon arrival is measured by using a high-precision time-to-digital converter chip TDC. Photon arrival time measurements can achieve tens of picosecond precision. The time resolution of photon counting imaging can achieve the measurement accuracy of photon arrival time.

3. The spatial resolution is high. The present invention adopts the peak value holder chip PKD01 and the 14-bit A/D converter chip AD9240 to form the peak value acquisition circuit, which can obtain the pulse with higher precision than the peak value acquisition circuit formed by the sample holder. Peak, so as to more accurately solve the position coordinates of the detected photons, and then obtain a higher resolution photon counting image.

4. The photon counting rate is high. The present invention uses a peak hold device to hold the pulse peak value. After the photon is detected to arrive at the timing signal, the A/D converter is started to perform a collection. The collection value is the peak value instead of collecting the entire pulse waveform. After coming down, find the peak value by calculation. So a pulse peak only needs to be collected once. Therefore, the amount of data and the operation process are greatly reduced, so it has a very high counting rate.

5. High integration level. The present invention uses FPGA to realize peak acquisition control, position decoding, time measurement, data buffering and transmission, and has very high integration level and flexibility.

6. Fast processing speed. Through the cooperation of FPGA and DSP to realize position decoding, FPGA controls data flow and performs simple operations, and DSP realizes floating-point number operations, which has a very high processing speed.

7. Wide range of applications. The acquisition card for time-resolved photon counting imaging involved in the present invention can be widely used in fluorescence lifetime imaging, biological and medical imaging, laser radar, ultraviolet early warning, diffusion optical tomography and single-molecule fluorescence spectroscopy , time-resolved fluorescence microscopy and other fields.

Description of drawings

Fig. 1 is the schematic diagram of the acquisition card used for time-resolved imaging of the present invention;

Fig. 2 is the schematic diagram of photon arrival timing signal generation circuit of the present invention;

Fig. 3 is the timing diagram that photon arrival timing signal of the present invention produces;

Fig. 4 is the principle diagram of multi-channel pulse peak synchronous acquisition unit of the present invention;

Fig. 5 is the timing diagram of multi-channel pulse peak synchronous acquisition of the present invention;

Fig. 6 is the circuit diagram of starting signal generation of the present invention;

Fig. 7 is the circuit diagram of the constant temperature crystal oscillator clock of the present invention;

Fig. 8 is the operating principle diagram of FPGA peak acquisition control unit, position decoding unit, time measurement unit, data cache and transmission of the present invention;

Fig. 9 is a schematic diagram of the continuous measurement of photon arrival time in the present invention;

Fig. 10 is a sequence diagram of continuous measurement of photon arrival time in the present invention;

Fig. 11 is a time-resolved photon counting image obtained by using the acquisition card of the present invention.

Detailed ways

The acquisition card for time-resolved imaging of the present invention will now be described in conjunction with the accompanying drawings. This example uses an MCP detector based on a WSA position-sensitive anode detector as an example for illustration. WSA position sensitive anode has 3 anode outputs W, S, Z. When a photon is detected, the detector will output three pulse signals.

Fig. 1 is the principle block diagram of the acquisition card of time-resolved imaging, and imaging system comprises imaging object, optical system, based on the position-sensitive anode detector of MCP, three-way pre-amplification and shaping main amplifier, the time-resolved imaging involved in the present invention Acquisition card (inside the frame) and computer.

The imaging target is imaged to the input surface of the detector through the optical system. When a photon is detected, the detector outputs three pulse signals. Three quasi-Gaussian pulses are input to the acquisition card of the present invention. The acquisition card of the present invention measures the position coordinates of the photons and the arrival time of the photons, and sends them to the computer. Computers process data. Reconstruct photon counting imaging of different time slices.

The acquisition card includes photon arrival timing signal generation circuit, three-way pulse peak synchronous acquisition circuit, start signal generation circuit, constant temperature crystal oscillator clock circuit (OCXO), programmable logic device FPGA, digital signal processor DSP, time-to-digital converter chip TDC chip and communication interface circuits.

Fig. 2 is a schematic diagram of the photon timing signal generation circuit, U1 is an operational amplifier, connected in the form of in-phase summation, and sums the three pulse signals output by the main amplifier. The summed signals are respectively input to the peak detection circuit realized by connecting the resistor R4, the capacitor C1 and the first comparator U2, the low threshold comparison circuit realized by the first potentiometer R5 and the second comparator U3, and the low threshold comparison circuit realized by the second potentiometer R6 and a high-threshold comparison circuit implemented by the third comparator U4. The D flip-flop F1 is a D flip-flop with setting and clearing terminals, the low threshold comparison output is input to the D terminal of the D flip-flop F1, and the peak detection output is input to the CLK terminal of the D flip-flop F1. The first U6 and the second U7 are NOT gates for delaying the signal output from the Q terminal of the D flip-flop. The high-threshold comparison output and the Q terminal delay signal are input to the reset RST terminal of the D flip-flop F1 after passing through the OR gate U5. The output signal of the Q terminal of the D flip-flop F1 is a photon arrival timing signal.

Figure 3 is a timing diagram of the generation of photon arrival timing signals, because the pulse output by the detector not only represents the detection of a single photon, but also includes small-amplitude pulses caused by noise, and large-amplitude pulses caused by high-energy particles and pulse accumulation. The photon arrival timing signal generation method is, when the pulse amplitude of the summed signal output is between the high threshold and the low threshold, the Q terminal of the D flip-flop F1 outputs a square wave pulse signal, and the square wave pulse signal is the photon arrival timing signal, which means that a photon is detected, and when the pulse amplitude of the summed signal output is less than the low threshold or greater than the high threshold, the photon time timing signal is not output.

Fig. 4 is a schematic circuit diagram of the pulse peak acquisition unit, each channel includes a peak hold chip, and passes through a follower connected by an amplifier and a high-precision A/D converter. The peak hold chip adopts the PKD01 chip of ADI Company, and the A/D converter adopts the AD9240 chip of ADI Company. The pins 1 and 14 of the three-way peak hold chip are connected together as the input end of the peak synchronous release signal, and the CLK of the three-way A/D conversion chip AD9240 are connected together as the A/D synchronous conversion signal.

Figure 5 is a timing diagram of synchronous acquisition of the peak values of the three pulses. After the three-way pulse signal enters the peak value and holds 0-2, the peak holder keeps the peak value of the pulse. At the same time, the three-way pulse signal enters the photon and arrives at the timing signal generating circuit. If the summed pulse peak value is between the low threshold and the high threshold , a photon arrival timing signal will be generated. Then when the FPGA on the acquisition card detects the photon arrival timing signal, the FPGA outputs an A/D synchronous conversion signal to drive three A/D converters to collect the peak values held by the three peak holders. After the acquisition, the FPGA output peak values are synchronously dropped Amplify the signal, so that the three peak holders release the peak value synchronously, so as to maintain the peak value of the next three input pulses. On the fourth rising edge of the A/D synchronous conversion signal, the three A/D converters output three pulse peak data to the FPGA.

Figure 6 is the start signal generation circuit, the output signal changes from low level to high level after pressing the button S. The rising edge of the signal represents the start time, and the start signal is input to the FPGA and to the stop1 terminal of the TDC chip.

Figure 7. The constant temperature crystal oscillator clock circuit (OCXO) adopts the MDB59P3T of the American MMDC-TECH company. The constant temperature crystal oscillator clock circuit (OCXO) generates a clock with high frequency stability and inputs it to the FPGA and to the start terminal of the TDC chip.

Fig. 8 is the structure schematic diagram of programmable logic device (FPGA), comprises peak acquisition control unit, position decoding unit, time measurement unit, data cache unit and communication control unit, and peak acquisition control unit is used for the input of pulse peak acquisition circuit The pulse peak value is measured, and the measured peak value data is transmitted to the position decoding unit; the position decoding unit is used to cooperate with the digital signal processor (DSP) to solve the position coordinate data of the photon, and the time measurement unit and the time-to-digital converter chip (TDC ) cooperate to measure the time-of-arrival data of the photon, and the data cache unit is used to store the position coordinate data and the time-of-arrival data of the photon; the communication control unit is used to control the data cache unit to store the time-of-arrival data and the photon The location coordinate data is sent to the computer. After the start signal, when the photon arrives at the timing signal, the peak value acquisition control realizes the measurement of the peak value of the three input pulses. The measured three-way peak data is input to the position decoding unit, and the position decoding module cooperates with the DSP to obtain the position coordinates of the photons. The DSP is connected to the FPGA and works with the FPGA. According to the collected multi-channel pulse peak data, the position coordinates of the photons are solved. The method of calculating the position of the photon by the WSA position-sensitive anode is as follows:

X＝(2×Q1)/(Q1+Q2+Q3) Y＝(2×Q2)/(Q1+Q2+Q3)

The time measurement unit cooperates with the time-to-digital converter chip to measure the arrival time of the photon, and the photon position coordinate data and photon arrival time data are stored in the data buffer unit FIFO in a synchronous manner. The data in the data cache unit FIFO is sent to the computer through the USB20.0 interface circuit under the control of the communication control unit.

FPGA controls data flow and performs simple calculations, and DSP implements complex calculations, such as division and floating-point calculations.

Figure 9 is a schematic diagram of the continuous measurement of photon arrival time, and the time measurement module implemented by FPGA is inside the dotted line frame. The time measurement module includes a counter, control logic and time calculation unit. The time measurement module cooperates with a time-to-digital converter chip (TDC) to measure the arrival time of photons. The clock signal of the OCXO is input to the start terminal of the TDC chip, the start signal is input to the stop1 terminal of the TDC, and the photon arrival timing signal is input to the stop2 terminal of the TDC.

Fig. 10 Timing sequence for continuous measurement of photon arrival time. The measurement of photon arrival time adopts the method of combining coarse time measurement and fine time measurement. After the start signal is generated by manual triggering, the rising edge of the start signal clears the counter. The stop1 channel of the TDC measures the time interval t ₀ between the rising edge of the start signal and the output pulse of the OCXO. Under the control of the controller, the counter outputs "0" and t ₀ output by the TDC represent the unified starting time of the arrival time of all photons.

When the signal is started, the counter counts the clock output by the constant temperature crystal oscillator clock circuit OCXO. When a photon arrives at the timing signal, the stop2 channel of the TDC measures the rising edge of the photon timing signal and the latest output pulse of the constant temperature crystal oscillator clock circuit (OCXO). The time interval t, t represents the fine time of photon arrival. At this time, the count value T in the counter represents the rough arrival time of the photon. Therefore, the photon arrival time can be expressed by

Photon arrival time = Tn+tn-t ₀ (n=1, 2, 3...)

The time calculation module calculates the arrival time of photons according to the above formula. The photon arrival time is stored in the data buffer unit FIFO under the control of the control logic.

The photon position coordinate data and photon arrival time data are stored in the FIFO buffer in a synchronous manner. The data in the FIFO buffer is sent to the computer through the USB20.0 interface circuit under the control of the USB communication control module. Develop computer software to process photon position coordinate data and photon arrival time data. The computer data processing method is, according to the photon arrival time data collected continuously, the position coordinate data of arriving photons within any time interval from the start signal to any time interval can be found , reconstruct the photon counting image, so as to obtain the photon counting image at different times, and realize time-resolved photon counting imaging. Time resolution allows for the measurement accuracy of photon arrival times.

Time-to-digital converter chip (TDC) is the TDC-GPX chip of German ACAM Company, and the precision of TDC-GPX chip can reach 10ps, so with the method of the present invention, time-resolved photon counting imaging can reach the time resolution of 10 picoseconds.

Fig. 11 is a time-resolved photon counting image obtained by using the acquisition card of the present invention, and the imaging target is a photon counting image at different times of the resolution plate.

This example uses the WSA position-sensitive anode detector based on the MCP detector as an example to illustrate. The WSA anode has three outputs, so the input of the acquisition card in the example of the present invention is three. There are three pulse peak acquisition circuits in the acquisition card, and there are three pairs of outputs A circuit that sums input pulses to generate a timing signal. Embodiments of the present invention cannot be assumed to be limited to MCP detectors with WSA anodic position sensitive anodic readout. If the position-sensitive anode of the detector is the vernier anode, the input of the acquisition card is nine channels. There are nine-channel pulse peak acquisition circuits in the acquisition card, and there is a circuit for summing the nine-channel input pulses to generate a timing signal. The position-sensitive anode is a resistor. The anode, the input of the acquisition card is four channels, and there are four channels of pulse peak acquisition circuits in the acquisition card, and there is a circuit for summing the four input pulses to generate a timing signal. Under the premise of not departing from the concept of the present invention, some simple deduction and transformation should be considered as the protection scope of the present invention.

Claims (7)

1. The acquisition card for time-resolved photon counting imaging is characterized in that: the acquisition card includes photon arrival timing signal generation circuit, pulse peak synchronous acquisition unit, start signal generation circuit, constant temperature crystal oscillator clock circuit (OCXO), programmable Logic device (FPGA), digital signal processor (DSP), time-to-digital converter chip (TDC) and communication interface circuit, The input terminal of the pulse peak acquisition unit is connected to the output end of the detector, and the pulse peak acquisition unit communicates with the programmable logic device, The output end of the detector is input to the programmable logic device (FPGA) through the photon arrival timing signal generation circuit, The output end of described start signal generating circuit is connected with programmable logic device (FPGA) and time-to-digital converter chip (TDC), The output end of the constant temperature crystal oscillator clock circuit (OCXO) is connected with a programmable logic device (FPGA) and a time-to-digital converter chip (TDC), The time-to-digital converter chip (TDC) communicates with a programmable logic device (FPGA), The digital signal processor (DSP) and the programmable logic device (FPGA) communicate with each other, and the programmable logic device (FPGA) is connected with the computer through a communication interface circuit. 2. The acquisition card for time-resolved photon counting imaging according to claim 1, wherein the photon arrival timing signal generation circuit includes a multi-channel pulse summation circuit, a peak detection circuit, a low threshold comparison circuit, a high Threshold comparison circuit and D flip-flop (F1), the multi-channel pulse summation circuit is an operational amplifier (U1) connected in a summation form, and the input terminal of the operational amplifier (U1) receives the multi-channel pulse output by the detector signal, the operational amplifier (U1) output summing signal is sent to the peak detection circuit, low threshold comparison circuit and high threshold comparison circuit respectively; the peak detection circuit is composed of resistor (R4), capacitor (C1) and the first (U2); the low threshold comparison circuit is composed of the first potentiometer (R5) and the second comparator (U3); the high threshold comparison circuit is composed of the second potentiometer (R6) and the third comparator (U4 ) composition; the peak value detection circuit is output to the CLK end of the D flip-flop (F1), the low threshold comparison circuit is output to the D end of the D flip-flop (F1), and the Q end of the D flip-flop (F1) outputs the photon arrival timing signal , the Q terminal of the D flip-flop (F1) passes through the first NOT gate (U6) and the second NOT gate (U7) in turn, and then the output signal of the high threshold comparison circuit passes through the OR gate (U5), or the OR gate ( The output terminal of U5) is connected to the RST terminal of the D flip-flop (F1). 3. The acquisition card for time-resolved photon counting imaging according to claim 1 or 2, wherein the pulse peak acquisition unit includes multiple parallel pulse peak acquisition circuits, and the pulse peak acquisition circuit includes sequentially A peak hold chip, an amplifier and an A/D converter are connected in series, the amplifier adopts a follower mode, the output terminals of all A/D converters are connected to the conversion terminal CLK, and the hold terminal of the peak hold chip is connected to the discharge terminal . 4. The acquisition card for time-resolved photon counting imaging according to claim 3, characterized in that: said programmable logic device (FPGA) comprises a peak acquisition control unit, a position decoding unit, a time measurement unit, and a data buffer unit and communication control unit; The peak value acquisition control unit is used to control the pulse peak value acquisition unit to perform peak synchronous measurement of the input pulse peak value, and transmit the measured peak value data to the position decoding unit; The position decoding unit is used to cooperate with a digital signal processor (DSP) to solve the position coordinate data of the photon; The time measurement unit cooperates with a time-to-digital converter chip (TDC) to measure the arrival time data of photons; The data cache unit is used to store the position coordinate data of the photon and the arrival time data of the photon; The communication control unit is used to control the data cache unit to send the photon arrival time data and photon position coordinate data to the computer. 5. The acquisition card for time-resolved photon counting imaging according to claim 4, characterized in that: the time measurement unit includes a counter, a control logic unit and a time calculation unit, and photon arrival timing signal, start signal generation circuit Start signal and synchronization signal input control logic unit, clock signal of constant temperature crystal oscillator clock circuit, start signal of start signal generating circuit, control signal input counter of control logic unit, time-to-digital converter chip (TDC), counter and control logic unit The output terminal is connected with the time calculation unit. 6. The acquisition card for time-resolved photon counting imaging according to claim 5, characterized in that: the clock signal of the constant temperature crystal oscillator clock circuit is input to the start end of the time-to-digital converter chip (TDC), and the signal generation circuit is started The start signal of the photons is input to the stop1 terminal of the time-to-digital converter chip (TDC), and the photon arrival timing signal is input to the stop2 terminal of the time-to-digital converter chip (TDC). 7. The acquisition card for time-resolved photon counting imaging according to claim 6, characterized in that: the constant temperature crystal oscillator clock circuit (OCXO) adopts MDB59P3T, the peak holding chip is a PKD01 chip, and the A/D The converter is an AD9240 chip, and the time-to-digital converter chip (TDC) is a TDC-GPX chip.

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