CN102323959A - Acquisition card for time-resolved photon counting imaging - Google Patents
Acquisition card for time-resolved photon counting imaging Download PDFInfo
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Abstract
The invention relates to an acquisition card for time-resolved photon counting imaging, which comprises a photon arrival timing signal generating circuit, a pulse peak value synchronous acquisition unit, a starting signal generating circuit, a constant-temperature crystal oscillator clock circuit, a programmable logic device, a digital signal processor, a time digital converter chip and a communication interface circuit, wherein the input end of the pulse peak value acquisition unit is connected with the output end of a detector, the pulse peak value acquisition unit is communicated with the programmable logic device, the output end of the detector is input to the programmable logic device through the photon arrival timing signal generating circuit, the output end of the starting signal generating circuit is connected with the programmable logic device and the time digital converter chip, and the output end of the constant-temperature crystal oscillator clock circuit is connected with the programmable logic device and the time digital converter chip. The invention solves the problem that the existing photon counting method lacks a photon counting imaging method with time resolution, and has the advantages of high time resolution and high spatial resolution.
Description
Technical field
The present invention relates to the low-light level imaging technical field, particularly be used for the capture card of time resolution photon counting imaging in the low-light level imaging technical field in the photon counting imaging technique.
Background technology
Be imaged on extensive applications such as astronomical sight, satellite remote sensing, biomedical imaging along with the low light level; Sensitivity requirement to low light level imaging detection is increasingly high, and the photon counting imaging is a kind of formation method of atomic weak target, has high sensitivity; Therefore the photon counting formation method can be applicable to many fields; Like astronomical sight, satellite remote sensing, biomedical imaging, nuclear radiation imaging, space ultraviolet imagery etc.The detector that is used for the photon counting imaging at present is mainly by photomultiplier (PMT), single-photon avalanche diode (SPAD), microchannel plate (MCP) etc.Wherein, photomultiplier (PMT), avalanche photo diode (APD) belong to single-element detector, therefore need optical mechaical scanning just can be embodied as picture, the real-time of imaging, and time resolution, spatial discrimination are not high.Has face battle array structure based on microchannel plate (MCP); Read through position-sensitive anode; Realization photon counting imaging has advantages such as signal to noise ratio (S/N ratio) height, highly sensitive, wide dynamic range, anti-drift are good. as mainly forming by cascade MCP and position-sensitive anode based on the position-sensitive anode detector of microchannel plate (MCP).Position-sensitive anode detector photon counting formation method based on MCP is that when detector detected a photon, position-sensitive anode was exported the multichannel electronic pulse signal.The multiplex pulse signal can be measured the position coordinates that detects photon through the electronics read-out system.Through the regular hour accumulation, measure the position coordinate data of a large amount of photons, according to the photon counting of diverse location, synthetic photon counting image.Position-sensitive anode mainly contains spline shape anode (Wedge and Strip Anode), vernier anode (Vernier Anode), intersection anode (Cross Strip Anode) and multianode micro channel array (MAMA) and resistance anode (Resistive anode) etc. document (FENG Bing; KANG Ke-Jun; WANG Kui-Lu; Et al.Nucl.Instrum.Meth.A, 2004,535:546) report multianode micro channel array (MAMA) photon counting imaging.Document (Lapington J S, Sanderson B, Worth L B C, et al.Nucl.Instr.Meth A, 2002,447:250) reported the photon counting imaging of adopting the vernier position-sensitive anode.Document (MIAO Zhen-hua, ZHAO Bao-sheng, ZHANG Xing-hua, et al.Chinese Physics Letters, 2008,25 (7), 2698) has been reported the photon counting imaging of adopting the WSA anode.(application number: what 200710018631.6 single photon counting formatters) adopt is that three electrode WSA anodes carry out the photon counting imaging to patent.But its adopts waveform digitization counting, anode is exported the multiplex pulse signal carry out all-wave shape and gather, and utilizes software to carry out peak value then and detects.Because this method will be gathered mass data amount gibberish, so counting rate is not high.
In the document of report, do not relate to the time resolution photon counting at present.Has time-resolved photon counting imaging; Owing to can reflect imageable target conversion process in time, therefore have very important scientific research value, can be applied to more field; Like fluorescence lifetime imaging; Biology and medical imaging, laser radar, ultraviolet early warning, diffuse optical chromatography and single molecular fluorescence spectrum, time-resolved fluorescence are micro-etc.
Summary of the invention
Have time-resolved photon counting formation method in order to solve to lack in the existing Photoncounting methods, the present invention proposes a kind of capture card that is used for the imaging of time resolution photon counting.
Technical solution of the present invention is following:
The capture card that is used for the imaging of time resolution photon counting; Its special character is: said capture card comprises that photon arrives timing signal generator circuit, peak value of pulse synchronous acquisition unit, commencing signal generation circuit, constant-temperature crystal oscillator clock circuit (OCXO), PLD (FPGA), digital signal processor (DSP), time-to-digit converter chip (TDC) and communication interface circuit
The output terminal of the input termination detector of said peak value of pulse collecting unit, said peak value of pulse collecting unit intercoms with PLD mutually,
The output terminal of said detector arrives timing signal generator circuit through photon and is input to PLD (FPGA),
The output terminal that said commencing signal produces circuit is connected with time-to-digit converter chip (TDC) with PLD (FPGA),
The output terminal of said constant-temperature crystal oscillator clock circuit (OCXO) is connected with time-to-digit converter chip (TDC) with PLD (FPGA),
Said time-to-digit converter chip (TDC) intercoms with PLD (FPGA) mutually,
Said digital signal processor (DSP) intercoms with PLD (FPGA) mutually, and said PLD (FPGA) is connected with computing machine through communication interface circuit.
Above-mentioned photon arrives timing signal generator circuit and comprises multiplex pulse summing circuit, peak detection circuit, low threshold value comparator circuit, high threshold comparator circuit and d type flip flop F1; Said multiplex pulse summing circuit is the operational amplifier U1 that connects into the summation form; The multiplex pulse signal of the input end pick-up probe output of said operational amplifier U1, said operational amplifier U1 output summing signal sends to peak detection circuit, low threshold value comparator circuit and high threshold comparator circuit respectively; Said peak detection circuit is made up of resistance R 4, capacitor C 1 and the first comparer U2; Said low threshold value comparator circuit is made up of the first potentiometer R5 and the second comparer U3; Said high threshold comparator circuit is made up of the second potentiometer R6 and the 3rd comparer U4; Peak detection circuit exports the CLK end of d type flip flop F1 to; Low threshold value comparator circuit exports the D end of d type flip flop F1 to; The Q end output photon of said d type flip flop F1 arrives timing signal; The Q of said d type flip flop F1 end successively through behind the first not gate U6, the second not gate U7 again with the output signal of high threshold comparator circuit all through or door U5, or the RST of the output termination d type flip flop F1 of door U5 holds.
Above-mentioned peak value of pulse collecting unit comprises the peak value of pulse Acquisition Circuit of multi-channel parallel; Said peak value of pulse Acquisition Circuit comprises that the peak value of series connection successively keeps chip, amplifier and A/D transducer; Said amplifier adopts the follower mode; The output terminal of all A/D transducers links to each other with conversion end CLK, and said peak value keeps the maintenance end of chip to link to each other with the bleed off end.
Above-mentioned PLD (FPGA) comprises peak value acquisition controlling unit, position decoding unit, time measuring unit, data buffer storage unit and communication control unit;
Said peak value acquisition controlling unit is used for gating pulse peak value collecting unit the peak value of pulse of being imported is carried out the peak value synchro measure, and the peak-data of measuring is transferred to the position decoding unit;
Said position decoding unit is used for cooperating the position coordinate data that solves photon with digital signal processor (DSP);
Said time measuring unit cooperates with time-to-digit converter chip (TDC), measures data time of arrival of photon;
Said data buffer storage unit is used to store data time of arrival of the position coordinate data and the photon of photon;
Said communication control unit be used for the control data buffer unit with photon time of arrival data and the position coordinate data of photon send to computing machine.
Above-mentioned time measuring unit comprises counter, steering logic unit and time calculating unit; Photon arrives the commencing signal and the synchronizing signal input control logic unit of timing signal, commencing signal generation circuit; The clock signal of constant-temperature crystal oscillator clock circuit, commencing signal produce the commencing signal of circuit, the control signal enter counter of steering logic unit, and the output terminal of time-to-digit converter chip (TDC), counter and steering logic unit is connected with time calculating unit.
The start end of the clock signal digital quantizer input time chip (TDC) of above-mentioned constant-temperature crystal oscillator clock circuit; Commencing signal produces the stop1 end of the commencing signal digital quantizer input time chip (TDC) of circuit, and photon arrives the stop2 end of timing signal digital quantizer input time chip (TDC).
Above-mentioned constant-temperature crystal oscillator clock circuit (OCXO) adopts MDB59P3T, and it is the PKD01 chip that said peak value keeps chip, and said A/D transducer is the AD9240 chip, and said time-to-digit converter chip (TDC) is the TDC-GPX chip.
The advantage that the present invention had:
1, have the imaging of time resolution photon counting, the present invention is through the time of arrival of continuous recording photon and the position coordinates of photon.Can rebuild the photon counting image of random time sheet through data processing, and then reflect imageable target process over time.
2, temporal resolution is high, the method that the measurement of photon of the present invention time of arrival adopts thick time measurement and thin time measurement to combine.Through the thick time of high frequency degree of stability constant-temperature crystal oscillator clock circuit being counted measurement of photon arrive, the thin time of adopting split-second precision digital quantizer chip TDC to come measurement of photon to arrive.Photon measurement time of arrival can reach the precision of tens psecs.The time resolution of photon counting imaging can reach the photon measuring accuracy of time of arrival.
3, spatial resolution is high; The present invention adopts peak-holding circuit chip PKD01 and 14 s' A/D converter chip AD9240 to form the peak value Acquisition Circuit; The peak value Acquisition Circuit that Billy forms with sampling holder; Can more high-precisionly obtain the peak value of pulse, thereby solve the position coordinates that detects photon more accurately, and then obtain more high-resolution photon counting image.
4, photon count rate is high; The present invention utilizes peak-holding circuit that peak value of pulse is maintained, wait detect photon and arrive timing signal after, start the A/D transducer and once gather; The collection value is exactly a peak value, rather than collects the back to whole pulse waveform through calculating peaking.So a peak value of pulse only need be gathered once.Therefore reduce data volume and calculating process greatly, therefore had very high counting rate.
5, integrated level is high, and the present invention adopts FPGA to realize peak value acquisition controlling, position decoding, time measurement, metadata cache and transmission, has very high integrated level and dirigibility.
6, processing speed is fast.Cooperate the realization position decoding through FPGA and DSP, the FPGA control data flows and carries out simple calculations, and DSP realizes floating point arithmetic, has very high processing speed.
7, applied range; The capture card that is used for the imaging of time resolution photon counting involved in the present invention can be widely used in fluorescence lifetime imaging, biology and medical imaging; Laser radar, field such as ultraviolet early warning, diffuse optical chromatography and single molecular fluorescence spectrum, time-resolved fluorescence are micro-.
Description of drawings
Fig. 1 is used for the schematic diagram of the capture card of time resolution imaging for the present invention;
Fig. 2 arrives the schematic diagram of timing signal generator circuit for photon of the present invention;
Fig. 3 arrives the sequential chart of timing signal for generating for photon of the present invention;
Fig. 4 is a multiplex pulse peak value synchronous acquisition of the present invention unit schematic diagram;
Fig. 5 is the sequential chart of multiplex pulse peak value synchronous acquisition of the present invention;
Fig. 6 produces circuit diagram for commencing signal of the present invention;
Fig. 7 is a constant-temperature crystal oscillator clocking scheme of the present invention;
Fig. 8 is the fundamental diagram of FPGA peak value acquisition controlling of the present invention unit, position decoding unit, time measuring unit, metadata cache and transmission;
The schematic diagram of Fig. 9 photon of the present invention continuous coverage time of arrival;
The sequential chart of Figure 10 photon of the present invention continuous coverage time of arrival;
The time resolution photon counting image of Figure 11 for adopting capture card of the present invention to obtain.
Embodiment
Combine accompanying drawing to explain that the present invention is used for the capture card of time resolution imaging, it is that example describes that this instance adopts based on MCP detector WSA position-sensitive anode detector at present.The WSA position-sensitive anode has 3 anode output W, S, Z.When detecting a photon, detector will be exported three road pulse signals.
Fig. 1 is the capture card theory diagram of time resolution imaging, and imaging system comprises that imageable target, optical system, the position-sensitive anode detector based on MCP, three tunnel preposition amplifications and shaping are mainly put, capture card that is used for the time resolution imaging (part in the frame) and computing machine involved in the present invention.
Imageable target is through the input face of optical system imaging to detector; When detecting a photon; Detector is exported three road pulse signals, and three road pulse signals become three tunnel accurate Gauss pulses through three road prime amplifiers and shaping are main after putting, three tunnel accurate Gauss pulses inputs capture card of the present invention.Capture card of the present invention is measured position coordinates and photon time of arrival of photon, and sends to computing machine.Computing machine passes through data processing.Rebuild the photon counting imaging of different time sheet.
Capture card comprises that photon arrives timing signal generator circuit, three road peak value of pulse synchronous acquisition circuits, commencing signal generation circuit, constant-temperature crystal oscillator clock circuit (OCXO), PLD FPGA, digital signal processor DSP, time-to-digit converter chip TDC chip and communication interface circuit.
Fig. 2 is described photon timing signal generator circuit schematic diagram, and U1 is an operational amplifier, connects into the form of homophase summation, and three road pulse signals of main amplifier output are sued for peace.Signal after the summation is imported respectively by resistance R 4, capacitor C 1 and the first comparer U2 and is connected the peak detection circuit realized, realizes low threshold value comparator circuit and the high threshold comparator circuit of being realized by the second potentiometer R6 and the 3rd comparer U4 by the first potentiometer R5 and the second comparer U3.D type flip flop F1 is the d type flip flop that has set and clear terminal, and low threshold ratio is the D end of output input d type flip flop F1, and peak value detects the CLK end of output input d type flip flop F1.The one U6 and the 2nd U7 are not gate, are used for the signal of d type flip flop Q end output is postponed.High threshold relatively export with Q end inhibit signal through or door U5 after be input to d type flip flop F1 zero clearing RST hold.The Q end output signal of d type flip flop F1 is that photon arrives timing signal.
Fig. 3 is that photon arrives the sequential chart of timing signal for generating, because the pulse of detector output except representative detects single photon, also comprises the pulse significantly that the pulse by a small margin that caused by noise and high energy particle and pulse pile-up cause.Photon arrives the timing signal for generating method; The pulse height of the signal output after summation is between high threshold and low threshold value; Then the Q of d type flip flop F1 end is exported square-wave pulse signal, and this square-wave pulse signal is that photon arrives timing signal, and representative detects a photon; When the pulse height of the signal output after the summation during less than low threshold value or greater than high threshold, output photon time timing signal not then.
Fig. 4 is the circuit theory diagrams of peak value of pulse collecting unit, and each road comprises that peak value keeps chip, through follower and the high-precision a/d converter that is connected into by amplifier.Peak value keeps chip to adopt the PKD01 chip of ADI company, the AD9240 chip of A/D converter using ADI company.Three road peak values keep 1 pin and 14 pins of chip to connect together as the input end of the synchronous bleed off signal of peak value, and the CLK of three road A/D conversion chip AD9240 connects together as the synchronous figure signal of A/D.
Fig. 5 is the synchronous acquisition sequential chart of three road peak value of pulses.After three road pulse signals enter into peak value maintenance 0-2; Peak-holding circuit maintains the peak value of pulse, and simultaneously, three road pulse signals input photon arrives timing signal generator circuit; If the peak value of pulse after the summation between low threshold value and high threshold, will produce photon and arrive timing signal.Then when the FPGA on the capture card detects photon arrival timing signal; The synchronous figure signal of FPGA output A/D drives three A/D converters and gathers the peak value that three peak-holding circuits keep; After having gathered; The synchronous bleed off signal of FPGA output peak value makes three synchronous bleed off peak values of peak-holding circuit, to keep the peak value of three road input pulses next time.At the 4th rising edge of the synchronous figure signal of A/D, three A/D transducers are exported three road peak value of pulse data to FPGA.
Fig. 6 is that commencing signal produces circuit, press the button S after output become high level signal by low level.The signal rising edge is represented the zero hour, and commencing signal is input to FPGA and the stop1 end that is input to the TDC chip.
Fig. 7 constant-temperature crystal oscillator clock circuit (OCXO) adopts the MDB59P3T of U.S. MMDC-TECH company, and the clock that constant-temperature crystal oscillator clock circuit (OCXO) produces high frequency stability is input to FPGA and the start end that is input to the TDC chip.
Fig. 8 is the structural representation of PLD (FPGA); Comprise peak value acquisition controlling unit, position decoding unit, time measuring unit, data buffer storage unit and communication control unit; Peak value acquisition controlling unit is used for the peak value of pulse that paired pulses peak value Acquisition Circuit imported to be measured, and the peak-data of measuring is transferred to the position decoding unit; The position decoding unit is used for cooperating the position coordinate data that solves photon with digital signal processor (DSP); Time measuring unit cooperates with time-to-digit converter chip (TDC); Measure data time of arrival of photon, said data buffer storage unit is used to store data time of arrival of the position coordinate data and the photon of photon; Said communication control unit be used for the control data buffer unit with photon time of arrival data and the position coordinate data of photon send to computing machine.Behind commencing signal, when photon arrives timing signal and arrives, the peak value acquisition controlling realize the peak value of three tunnel pulses of input is measured.Three tunnel peak-data input position decoding units of measuring, the position decoding module cooperates the position coordinates that solves photon with DSP.DSP links to each other with FPGA, with the FPGA cooperating, according to the multiplex pulse peak-data of gathering, solves the position coordinates of photon, and the method for the calculating photon position of WSA position-sensitive anode is:
X＝(2×Q1)/(Q1+Q2+Q3) Y＝(2×Q2)/(Q1+Q2+Q3)
Time measuring unit cooperates with the time-to-digit converter chip, measures the time of arrival of photon, and the position coordinate data of photon and photon data time of arrival are deposited data buffer storage unit FIFO in a synchronous manner.Data among the data buffer storage unit FIFO through the USB20.0 interface circuit, send to computing machine under the control of communication control unit.
The FPGA control data flows and carries out simple calculations, and DSP realizes complex calculation, like division and floating point arithmetic.
Fig. 9 is the schematic diagram of photon continuous coverage time of arrival, realizes the time measurement module for FPGA in the dotted line wire frame.The time measurement module comprises counter, steering logic and time calculating unit.The time measurement module cooperates with time-to-digit converter chip (TDC), measures the time of arrival of photon.The start end of the clock signal input TDC chip of OCXO, the stop1 end among the commencing signal input TDC, photon arrive the stop2 end among the timing signal input TDC.
The sequential of Figure 10 photon continuous coverage time of arrival.The method that the measurement of photon time of arrival adopts thick time measurement and thin time measurement to combine.After manual triggers produced commencing signal, the rising edge of commencing signal carried out zero clearing to counter, and the stop1 channel measurement of TDC goes out the time interval t of commencing signal rising edge and OCXO output pulse
0, under the control of controller, calculate " 0 " of number device output and the t of TDC output
0, the unified time-out of representing all photons time of arrival constantly.
Behind commencing signal; Counter is counted the clock of constant-temperature crystal oscillator clock circuit OCXO output; When a photon arrives timing signal arrival; The stop2 channel measurement of TDC goes out photon timing signal rising edge and constant-temperature crystal oscillator clock circuit (OCXO) is exported the time interval t of pulse recently, the thin time that on behalf of photon, t arrive.The thick time that on behalf of photon, the count value T in this hour counter arrive.Therefore the time of photon arrival can be represented with following formula
Time of arrival=the Tn+tn-t of photon
0(n=1,2,3 ...)
The Time Calculation module calculates the time that photon arrives according to following formula.The time that under the control of steering logic, photon is arrived is deposited data buffer storage unit FIFO.
The position coordinate data of photon and photon data time of arrival are deposited the FIFO buffer memory in a synchronous manner.Data in the FIFO buffer memory through the USB20.0 interface circuit, send to computing machine under the control of usb communication control module.Development computer software is handled the position coordinate data and photon data time of arrival of photon; And Methods of Computer Date Processing does; According to photon data time of arrival of continuous acquisition, the position coordinate data of the photon of the arrival in can finding from commencing signal to any time at intervals is rebuild the photon counting image; Thereby obtain different photon counting images constantly, realize the imaging of time resolution photon counting.Time resolution can be arrived the photon measuring accuracy of time of arrival.
Time-to-digit converter chip (TDC) is the TDC-GPX chip of German ACAM company, TDC-GPX chip precision can reach 10ps, therefore use method of the present invention, time resolution photon counting to form images and can reach the temporal resolution of 10 psecs.
The time resolution photon counting image of Figure 11 for adopting capture card of the present invention to obtain, imageable target are the different photon counting images constantly of resolving power test target.
It is that example describes that this instance adopts based on MCP detector WSA position-sensitive anode detector; The WSA anode has three tunnel outputs; Therefore instance capture card of the present invention be input as three the tunnel, three road peak value of pulse Acquisition Circuit are arranged in the capture card, have summation to produce the circuit of timing signal to three road input pulses.Can not assert that embodiment of the present invention only limits to the MCP detector that WSA anode position-sensitive anode is read.If the position-sensitive anode of detector is the vernier anode; Then capture card be input as nine the tunnel, nine road peak value of pulse Acquisition Circuit are arranged in the capture card, the circuit that nine road input pulses summations is produced timing signal is arranged; Position-sensitive anode is the resistance anode; Capture card be input as four the tunnel, four road peak value of pulse Acquisition Circuit are arranged in the capture card, the circuit that four road input pulses summations is produced timing signal is arranged.Under the prerequisite that does not break away from the present invention's design, carry out some simple deductions and conversion, all should be regarded as protection domain of the present invention.
Claims (7)
1. the capture card that is used for the imaging of time resolution photon counting; It is characterized in that: said capture card comprises that photon arrives timing signal generator circuit, peak value of pulse synchronous acquisition unit, commencing signal generation circuit, constant-temperature crystal oscillator clock circuit (OCXO), PLD (FPGA), digital signal processor (DSP), time-to-digit converter chip (TDC) and communication interface circuit
The output terminal of the input termination detector of said peak value of pulse collecting unit, said peak value of pulse collecting unit intercoms with PLD mutually,
The output terminal of said detector arrives timing signal generator circuit through photon and is input to PLD (FPGA),
The output terminal that said commencing signal produces circuit is connected with time-to-digit converter chip (TDC) with PLD (FPGA),
The output terminal of said constant-temperature crystal oscillator clock circuit (OCXO) is connected with time-to-digit converter chip (TDC) with PLD (FPGA),
Said time-to-digit converter chip (TDC) intercoms with PLD (FPGA) mutually,
Said digital signal processor (DSP) intercoms with PLD (FPGA) mutually, and said PLD (FPGA) is connected with computing machine through communication interface circuit.
2. the capture card that is used for the imaging of time resolution photon counting according to claim 1; It is characterized in that: said photon arrives timing signal generator circuit and comprises multiplex pulse summing circuit, peak detection circuit, low threshold value comparator circuit, high threshold comparator circuit and d type flip flop (F1); Said multiplex pulse summing circuit is the operational amplifier (U1) that connects into the summation form; The multiplex pulse signal of the input end pick-up probe output of said operational amplifier (U1), said operational amplifier (U1) output summing signal sends to peak detection circuit, low threshold value comparator circuit and high threshold comparator circuit respectively; Said peak detection circuit is made up of resistance (R4), electric capacity (C1) and first comparer (U2); Said low threshold value comparator circuit is made up of first potentiometer (R5) and second comparer (U3); Said high threshold comparator circuit is made up of second potentiometer (R6) and the 3rd comparer (U4); Peak detection circuit exports the CLK end of d type flip flop (F1) to; Low threshold value comparator circuit exports the D end of d type flip flop (F1) to; The Q end output photon of said d type flip flop (F1) arrives timing signal; The Q of said d type flip flop (F1) end successively through behind first not gate (U6), second not gate (U7) again with the output signal of high threshold comparator circuit all through or door (U5), or the RST of the output termination d type flip flop (F1) of door (U5) holds.
3. the capture card that is used for the imaging of time resolution photon counting according to claim 1 and 2; It is characterized in that: said peak value of pulse collecting unit comprises the peak value of pulse Acquisition Circuit of multi-channel parallel; Said peak value of pulse Acquisition Circuit comprises that the peak value of series connection successively keeps chip, amplifier and A/D transducer; Said amplifier adopts the follower mode, and the output terminal of all A/D transducers links to each other with conversion end CLK, and said peak value keeps the maintenance end of chip to link to each other with the bleed off end.
4. the capture card that is used for the imaging of time resolution photon counting according to claim 3, it is characterized in that: said PLD (FPGA) comprises peak value acquisition controlling unit, position decoding unit, time measuring unit, data buffer storage unit and communication control unit;
Said peak value acquisition controlling unit is used for gating pulse peak value collecting unit the peak value of pulse of being imported is carried out the peak value synchro measure, and the peak-data of measuring is transferred to the position decoding unit;
Said position decoding unit is used for cooperating the position coordinate data that solves photon with digital signal processor (DSP);
Said time measuring unit cooperates with time-to-digit converter chip (TDC), measures data time of arrival of photon;
Said data buffer storage unit is used to store data time of arrival of the position coordinate data and the photon of photon;
Said communication control unit be used for the control data buffer unit with photon time of arrival data and the position coordinate data of photon send to computing machine.
5. the capture card that is used for the imaging of time resolution photon counting according to claim 4; It is characterized in that: said time measuring unit comprises counter, steering logic unit and time calculating unit; Photon arrives the commencing signal and the synchronizing signal input control logic unit of timing signal, commencing signal generation circuit; The clock signal of constant-temperature crystal oscillator clock circuit, commencing signal produce the commencing signal of circuit, the control signal enter counter of steering logic unit, and the output terminal of time-to-digit converter chip (TDC), counter and steering logic unit is connected with time calculating unit.
6. the capture card that is used for the imaging of time resolution photon counting according to claim 5; It is characterized in that: the start end of the clock signal digital quantizer input time chip (TDC) of said constant-temperature crystal oscillator clock circuit; Commencing signal produces the stop1 end of the commencing signal digital quantizer input time chip (TDC) of circuit, and photon arrives the stop2 end of timing signal digital quantizer input time chip (TDC).
7. the capture card that is used for the imaging of time resolution photon counting according to claim 6; It is characterized in that: said constant-temperature crystal oscillator clock circuit (OCXO) adopts MDB59P3T; It is the PKD01 chip that said peak value keeps chip; Said A/D transducer is the AD9240 chip, and said time-to-digit converter chip (TDC) is the TDC-GPX chip.
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| CN 201110152840 CN102323959B (en) | 2011-06-09 | 2011-06-09 | Acquisition card for time-resolved photon counting imaging |
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| CN 201110152840 CN102323959B (en) | 2011-06-09 | 2011-06-09 | Acquisition card for time-resolved photon counting imaging |
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| CN106687825A (en) * | 2014-09-02 | 2017-05-17 | 皇家飞利浦有限公司 | Window-based spectrum measurement in a spectral ct detector |
| CN110618111A (en) * | 2018-06-19 | 2019-12-27 | 克洛纳测量技术有限公司 | Measuring device and method for the time-resolved measurement of a measurement signal |
| CN110865057A (en) * | 2019-11-06 | 2020-03-06 | 天津大学 | Non-uniform time-to-digital converter applied to fluorescence lifetime imaging |
| CN111856485A (en) * | 2020-06-12 | 2020-10-30 | 深圳奥锐达科技有限公司 | Distance measuring system and measuring method |
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| CN102798589A (en) * | 2012-05-22 | 2012-11-28 | 山东理工大学 | High-speed photon correlator with large dynamic range |
| CN106687825A (en) * | 2014-09-02 | 2017-05-17 | 皇家飞利浦有限公司 | Window-based spectrum measurement in a spectral ct detector |
| CN105758532B (en) * | 2016-02-24 | 2018-11-20 | 成都麟鑫泰来科技有限公司 | Faint optical measuring instrument and multichannel faint light time resolution method |
| CN105758532A (en) * | 2016-02-24 | 2016-07-13 | 成都麟鑫泰来科技有限公司 | Feeble light measuring instrument and multi-channel feeble light time-resolved method |
| CN105911538A (en) * | 2016-04-19 | 2016-08-31 | 武汉大学 | Laser radar triggering signal extension circuit |
| CN106656118B (en) * | 2016-09-28 | 2019-10-11 | 东软医疗系统股份有限公司 | A kind of circuit and detector for obtaining photon and reaching the detector time |
| CN106656118A (en) * | 2016-09-28 | 2017-05-10 | 沈阳东软医疗系统有限公司 | Circuit for obtaining time for photons to reach detector and detector |
| CN110618111A (en) * | 2018-06-19 | 2019-12-27 | 克洛纳测量技术有限公司 | Measuring device and method for the time-resolved measurement of a measurement signal |
| CN110865057A (en) * | 2019-11-06 | 2020-03-06 | 天津大学 | Non-uniform time-to-digital converter applied to fluorescence lifetime imaging |
| CN110865057B (en) * | 2019-11-06 | 2022-04-08 | 天津大学 | Non-uniform time-to-digital converter applied to fluorescence lifetime imaging |
| CN111856485A (en) * | 2020-06-12 | 2020-10-30 | 深圳奥锐达科技有限公司 | Distance measuring system and measuring method |
| CN111856485B (en) * | 2020-06-12 | 2022-04-26 | 深圳奥锐达科技有限公司 | Distance measuring system and measuring method |
| CN112946688A (en) * | 2021-02-02 | 2021-06-11 | 松山湖材料实验室 | Novel photon counting laser radar 3D imaging method and device |
| CN112946688B (en) * | 2021-02-02 | 2024-02-02 | 松山湖材料实验室 | Novel photon counting laser radar 3D imaging method and device |
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