CN102315116B - Method for depositing fluorine-doped silicon oxide thin film on wafer - Google Patents
Method for depositing fluorine-doped silicon oxide thin film on wafer Download PDFInfo
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- CN102315116B CN102315116B CN 201010221786 CN201010221786A CN102315116B CN 102315116 B CN102315116 B CN 102315116B CN 201010221786 CN201010221786 CN 201010221786 CN 201010221786 A CN201010221786 A CN 201010221786A CN 102315116 B CN102315116 B CN 102315116B
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Abstract
The invention provides a method for depositing a fluorine-doped silicon oxide thin film on a wafer. The method comprises the following steps of: depositing a first layer of fluorine-doped silicon oxide with fluorine content of f1 on the upper surface of a metal wiring layer on the upmost layer of the wafer; and depositing a second layer of fluorine-doped silicon oxide with fluorine content of f2 on the upper surface of the first layer of fluorine-doped silicon oxide, wherein f2 is less than f1. By the method, the fluorine-doped silicon oxide thin film with higher fluorine content can be obtained under the condition of avoiding bubbles.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, particularly a kind of on wafer the method for deposit fluorine-doped silica film.
Background technology
In current large-scale semiconductive chip manufacture, need use the metal film layer more than six layers, the structure metal connecting line is realized being electrically connected between these metal film layers.Insulating material is deposited on and forms electric insulation layer between the metal film layer so that sufficient insulation blocking to be provided.And on the electric insulation layer of the superiors deposit silicon nitride as the passivation protection layer.
Electric insulation layer commonly used in the traditional handicraft is the unadulterated silica of high-purity.According to physics general knowledge, the speed that signal transmits in the circuit, be to be subjected to about the product institute of resistance (R) and electric capacity (C), the RC product is big more, speed is just slow more, otherwise the RC product is more little, signaling rate just can be fast more, and is this because the reduction of the signal transmission speed that resistance and electric capacity cause is called the RC delay.
RC postpones relevant with the dielectric constant of electric insulation layer, and dielectric constant is big more, and then RC postpones also big more.It is found that and in silica, mix a certain amount of fluorine, can effectively reduce dielectric constant.Therefore the silica (FSG, Fluorine Silicon Glass) with doped with fluorine replaces the electric insulation layer of unadulterated silica (USG, Un-doped Silicon Glass) as the metallic film interlayer.
Though the dielectric constant of FSG raises along with the content of fluorine and descends, along with the rising of fluorine content, FSG is for the adsorption capacity enhancing of water.And the water (H2O) that is adsorbed among the FSG can react with the silicon fluoride among the FSG, generates hydrogen fluoride (HF) and silicon hydroxide (Si-OH).The dehydration water generation reaction can take place in silicon hydroxide.HF and water can be at the silica of the doped with fluorine of the superiors and on as the interface between the silicon nitride of passivation protection layer the form with gas exist, this is known as air blister defect (bubble defect).
For above-mentioned reasons, the content with fluorine among the FSG in the prior art is limited in below 4.6%, to avoid the generation of air blister defect.
Summary of the invention
The invention provides a kind of on wafer the method for deposit fluorine-doped silica film, can occur under the situation of air blister defect avoiding, obtain the higher fluorine-doped silica film of fluorine content.
The embodiment of the invention proposes a kind of on wafer the method for deposit fluorine-doped silica film, comprise the steps:
Upper surface deposit fluorine content at wafer the superiors metal connecting line layer is the ground floor fluorine-doped silica of f1;
Upper surface deposit fluorine content at described ground floor fluorine-doped silica is the second layer fluorine-doped silica of f2, f2＜f1.
Preferably, the thickness of described ground floor fluorine-doped silica is greater than the height of interlayer metal line, and the thickness span is 4000～10000 dusts.
Preferably, the thickness of described second layer fluorine-doped silica is 1000～3000 dusts.
Preferably, the span of described f1 is: 5.0～6.0%.
Preferably, the span of described f2 is 4.0～4.6%.
Preferably, the method that described deposit fluorine content is the ground floor fluorine-doped silica of f1 is: use PCVD, pressure is controlled at 1～2 holder, high frequency power is 800～1500W, low frequency power 500～1000W, reacting gas: nitrogen flow 3000～4000sccm, SiH
4200～300sccm, SiF
4500～800sccm, N
2O 10000～15000sccm, the reaction time is 50～70 seconds.
Preferably, the method that described deposit fluorine content is the second layer fluorine-doped silica of f2 is: use PCVD, pressure is controlled at 1～2 holder, high frequency power is 800～1500W, low frequency power 500～1000W, reacting gas: nitrogen flow 4000～5000sccm, silane SiH
4500～700sccm, silicon tetrafluoride SiF
41000～2000sccm, nitrous oxide N
2O 10000～15000sccm, the reaction time is 50～70 seconds.
As can be seen from the above technical solutions, at the two-layer fluorine-doped silica of upper surface consecutive deposition of wafer the superiors metal connecting line layer, this double-layer films has different fluorine content, and the fluorine content of topmost thin film is lower.Like this, topmost thin film just plays the effect to the protective layer of lower film, avoids the lower film adsorbed water, has therefore just avoided the generation of air blister defect from root.And the major part in the topmost thin film can be consumed in chemico-mechanical polishing (CMP) process, and the dielectric constant on this two-layer fluorine-doped silica film integral equals the dielectric constant of lower film substantially.So just can both avoid the generation of air blister defect, obtain to have electric insulation layer again than low-k.
Description of drawings
Fig. 1 for the embodiment of the invention propose a kind of on wafer the schematic flow sheet of deposit fluorine-doped silica film.
Embodiment
The present invention program is that the fluorine-doped silica film with the fluorine uniform content of deposit individual layer in the prior art becomes the two-layer fluorine-doped silica film of consecutive deposition, and this double-layer films has different fluorine content, and the fluorine content of topmost thin film is lower.Like this, topmost thin film just plays the effect to the protective layer of lower film, avoids the lower film adsorbed water, has therefore just avoided the generation of air blister defect from root.And the major part in the topmost thin film can be consumed in chemico-mechanical polishing (CMP) process, and the dielectric constant on this two-layer fluorine-doped silica film integral equals the dielectric constant of lower film substantially.So just can both avoid the generation of air blister defect, obtain to have electric insulation layer again than low-k.
The embodiment of the invention proposes a kind of on wafer deposit fluorine-doped silica film flow process as shown in Figure 1, comprise the steps:
Step 101: the upper surface deposit fluorine content at wafer the superiors metal connecting line layer is the ground floor fluorine-doped silica of f1;
Step 102: the upper surface deposit fluorine content at described ground floor fluorine-doped silica is the second layer fluorine-doped silica of f2, f2＜f1.
In the prior art flow process, the thickness of the fluorine-doped silica layer of deposit is 12000 dusts on the wafer the superiors metal connecting line layer of a certain specification, behind copper metallization next, the thickness that carries out fluorine-doped silica layer in the process of Cu-CMP can consume about 1500 dusts, and the fluorine-doped silica layer that so just has thickness and be 10500 dusts remains.With reference to this ratio; the embodiment of the invention is by being provided with the time of above two depositing steps; the thickness that makes the ground floor fluorine-doped silica is 10000 dusts; the thickness of described second layer fluorine-doped silica is 2000 dusts; like this after carrying out Cu-CMP; the residual thickness of second layer fluorine-doped silica is 500 dusts, is enough to play the effect of protective layer.
In other embodiments of the invention, the thickness of described ground floor fluorine-doped silica and second layer fluorine-doped silica changes along with the variation of the thickness of wafer the superiors metal connecting line layer, the thickness of ground floor fluorine-doped silica is greater than the height of interlayer metal line, and the thickness span is 4000～10000 dusts.The thickness of described second layer fluorine-doped silica is 1000～3000 dusts.
Preferably, the span of described f1 is: 5.0～6.0%.The span of described f2 is 4.0～4.6%.
Preferably, the method that described deposit fluorine content is the ground floor fluorine-doped silica of f1 is: use PCVD, pressure is controlled at 1～2 holder, high frequency power is 800～1500W, low frequency power 500～1000W, reacting gas: nitrogen flow 3000～4000sccm, SiH
4200～300sccm, SiF
4500～800sccm, N
2O 10000～15000sccm, the reaction time is 50～70 seconds.
Preferably, the method that described deposit fluorine content is the second layer fluorine-doped silica of f2 is: use PCVD, pressure is controlled at 1～2 holder, high frequency power is 800～1500W, low frequency power 500～1000W, reacting gas: nitrogen flow 4000～5000sccm, silane SiH
4500～700sccm, silicon tetrafluoride SiF
41000～2000sccm, nitrous oxide N
2O 10000～15000sccm, the reaction time is 50～70 seconds.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (5)
1. the method for a deposit fluorine-doped silica film on wafer is characterized in that, comprises the steps:
Upper surface deposit fluorine content at wafer the superiors metal connecting line layer is the ground floor fluorine-doped silica of f1; The thickness of described ground floor fluorine-doped silica is greater than the height of interlayer metal line, and the thickness span is 4000 ~ 10000 dusts;
Upper surface deposit fluorine content at described ground floor fluorine-doped silica is the second layer fluorine-doped silica of f2, f2＜f1; The thickness of described second layer fluorine-doped silica is 1000 ~ 3000 dusts.
2. method according to claim 1 is characterized in that the span of described f1 is: 5.0 ~ 6.0%.
3. method according to claim 1 is characterized in that, the span of described f2 is 4.0 ~ 4.6%.
4. method according to claim 1, it is characterized in that, the method that described deposit fluorine content is the ground floor fluorine-doped silica of f1 is: use PCVD, pressure is controlled at 1 ~ 2 holder, high frequency power is 800 ~ 1500W, low frequency power 500 ~ 1000W, reacting gas: nitrogen flow 3000 ~ 4000sccm, SiH
4200 ~ 300sccm, SiF
4500 ~ 800sccm, N
2O10000 ~ 15000sccm, the reaction time is 50 ~ 70 seconds.
5. method according to claim 1, it is characterized in that, the method that described deposit fluorine content is the second layer fluorine-doped silica of f2 is: use PCVD, pressure is controlled at 1 ~ 2 holder, high frequency power is 800 ~ 1500W, low frequency power 500 ~ 1000W, reacting gas: nitrogen flow 4000 ~ 5000sccm, silane SiH
4500 ~ 700sccm, silicon tetrafluoride SiF
41000 ~ 2000sccm, nitrous oxide N
2O10000 ~ 15000sccm, the reaction time is 50 ~ 70 seconds.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1208247A (en) * | 1997-06-03 | 1999-02-17 | 日本电气株式会社 | Method of forming fluorine-added insulating film |
| CN1242595A (en) * | 1998-07-22 | 2000-01-26 | 西门子公司 | Silicon oxynitride cap for fluorinated silicate glass film in intermetal dielectric semiconductor fabrication |
| CN1400659A (en) * | 2001-07-30 | 2003-03-05 | 株式会社东芝 | Semiconductor device and its manufacture |
| CN1716547A (en) * | 2004-06-30 | 2006-01-04 | 中芯国际集成电路制造(上海)有限公司 | Super low dielectric constant film and its producing method |
| CN101289284A (en) * | 2007-04-20 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Process for effectively controlling air bubble producing in forming process of fluorine-containing silex glass interlayer medium layer |
-
2010
- 2010-06-30 CN CN 201010221786 patent/CN102315116B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1208247A (en) * | 1997-06-03 | 1999-02-17 | 日本电气株式会社 | Method of forming fluorine-added insulating film |
| CN1242595A (en) * | 1998-07-22 | 2000-01-26 | 西门子公司 | Silicon oxynitride cap for fluorinated silicate glass film in intermetal dielectric semiconductor fabrication |
| CN1400659A (en) * | 2001-07-30 | 2003-03-05 | 株式会社东芝 | Semiconductor device and its manufacture |
| CN1716547A (en) * | 2004-06-30 | 2006-01-04 | 中芯国际集成电路制造(上海)有限公司 | Super low dielectric constant film and its producing method |
| CN101289284A (en) * | 2007-04-20 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Process for effectively controlling air bubble producing in forming process of fluorine-containing silex glass interlayer medium layer |
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