CN102315110B - The manufacture method that a kind of trench semiconductor power device grid is derived - Google Patents
The manufacture method that a kind of trench semiconductor power device grid is derived Download PDFInfo
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- CN102315110B CN102315110B CN201110230191.7A CN201110230191A CN102315110B CN 102315110 B CN102315110 B CN 102315110B CN 201110230191 A CN201110230191 A CN 201110230191A CN 102315110 B CN102315110 B CN 102315110B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 230000001413 cellular Effects 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 11
- 239000002019 doping agent Substances 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 6
- 229910000632 Alusil Inorganic materials 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical class [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 208000008425 Protein Deficiency Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000000717 retained Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
Abstract
The present invention relates to the manufacture method that a kind of trench semiconductor power device grid is derived, include cellular region and grid bus leading-out zone, cellular region is normally at the middle section of layout design, it is made up of some repeatability unit, surface is drawn by contact metal, constitute MOSFET source electrode, the back side is drained as MOSFET by metal level and low resistance monocrystalline substrate layer, the plough groove type that wherein interts is netted or strip polysilicon gate, grid bus derives the outside being normally at cellular region, leads to be connected with top-level metallic by cellular region polysilicon gate；Saving polycrystalline is mechanical；Reach the performance suitable with original design.
Description
Technical field
The invention belongs to microelectronic, relate to semiconductor power device, be more particularly to separation type semiconductor power device
The design of part grooved MOSFET and manufacture method.
Background technology
A kind of power MOSFET has three electrodes, is grid, source electrode, drain electrode respectively, according to the height of gate voltage, controls
Source electrode and the unlatching off state of drain electrode.Grooved MOSFET, as emerging power MOSFET in modern age, is that electric current flows vertically to
Device.Make source electrode and the electrode of grid of MOSFET in wafer surface, the back side makes the drain electrode of MOSFET, has
Highly integrated, the advantage of low on-resistance.
Grooved MOSFET include cellular region and grid bus leading-out zone.It is normally at the central authorities of chip design
Region, is constituted strip or net plane structure by some repeatability unit, and surface is drawn by contact hole filler metal to be become
The source electrode of MOSFET, is trench polysilicon grid between adjacent cells.Grid bus leading-out zone is normally at cellular region
Outside, is connected to the polysilicon gate of cellular region top-level metallic and constitutes the gate electrode of MOSFET.
The method of the grid bus leading-out zone of traditional fabrication grooved MOSFET, uses the side of polysilicon mask etching
Method, gets rid of the polysilicon exposing groove of cellular region, retains the portion in grid bus leading-out zone polysilicon and cellular region groove
Point, etch media sealing coat forms contact hole afterwards, refills metal, exports to top layer and constitutes gate electrode.
Summary of the invention
It is an object of the invention in order to avoid above deficiency, it is provided that a kind of trench semiconductor power device grid is led
The manufacture method gone out.
The technical solution adopted in the present invention is: the manufacture method that a kind of trench semiconductor power device grid is derived,
Including cellular region and grid bus leading-out zone, cellular region is positioned at the middle section of layout design, by some repeatability unit structures
Becoming, surface is drawn by contact metal, constitutes MOSFET source electrode, and the back side is made by metal level and low resistance monocrystalline substrate layer
Draining for MOSFET, the plough groove type that wherein interts is netted or strip polysilicon gate, and grid bus is derived and is positioned at outside cellular region
Side, leads to be connected with top-level metallic by cellular region polysilicon gate, low resistance monocrystalline substrate layer, high resistance monocrystal silicon extension
Layer, the well region that the doping type of formation is different on epitaxial layer, trench polysilicon grid, the source dopant region of polysilicon gate both sides,
Buffer layer, metal layer at top, top-level metallic is connected with source dopant region by the metal throuth hole through buffer layer, comprises
The gate medium sealing coat that one layer of polysilicon body and one layer of silicon compound are formed；Include but not limited to following steps:
1) groove is formed by dry etching；
2) growth and the removal of sacrificial oxidation film is carried out at channel bottom and sidewall；
3) growth of gate dielectric layer is carried out again at channel bottom and sidewall；
4) in groove, carry out growth and the etching of grid polycrystalline silicon；
5) region between groove, is doped in the way of ion implanting or diffusion；
6) depositing silicon dioxide above total is the buffer layer of main component；
7) on described buffer layer, form top-level metallic by dry etching to be connected with source dopant region and polysilicon gate
Contact hole；
8) metal filled contact hole, forms source pressure welding point and the pressure welding point of grid in front；
Wherein step 2), sacrificial oxidation film and the growth of buffer layer described in step 6), use tubular at high temperature furnace
Become；
Grid polycrystalline silicon deposition thickness described in step 4) 6,000 10000 angstroms, grid polycrystalline silicon returns not use and covers quarter
Masterplate, after etching, grid polycrystalline silicon only remains in groove；
After doping described in step 5), it is attended by the manufacturing process utilizing high temperature furnace pipe to advance；
Buffer layer described in step 6), doped with boron or phosphorus, thickness 2,000 10000 angstroms；Step 7) is to being given an account of
The etching of matter sealing coat comprises coating photoresist, carries out photoetching, develops and etches；Metal filled described in step 8), uses copper
Alusil alloy or tungsten, formed, its thickness 16 microns in the way of deposit or sputtering.
In the design of mask making groove, replace 1.5 10 with the small wire wide slots of some 0.3 1.5 microns
The big live width groove of micron, is put into the polysilicon that grid bus is derived in groove, and replaces single with some small wire wide slots simultaneously
One big live width trench design.
The invention has the beneficial effects as follows: make full use of what polysilicon in grooved MOSFET technique was retained when etching
Feature makes grid bus deriving structure, and device grids bus leading-out zone is designed to live width 0.3 2 microns and cellular region phase
As groove structure, reach to save the mechanical purpose of polycrystalline；Make the contact hole line of a plurality of gate polysilicon simultaneously, many to reduce
The resistance value of polysilicon gate, reaches the performance suitable with original design.
Detailed description of the invention
The manufacture method that a kind of trench semiconductor power device grid is derived, includes cellular region and grid bus is derived
District, cellular region is positioned at the middle section of layout design, is made up of some repeatability unit, and surface is drawn by contact metal, structure
Becoming MOSFET source electrode, the back side is drained as MOSFET by metal level and low resistance monocrystalline substrate layer, wherein interts ditch
Slot type is netted or strip polysilicon gate, and grid bus derives the outside being positioned at cellular region, is drawn by cellular region polysilicon gate
To being connected with top-level metallic, low resistance monocrystalline substrate layer, high resistance single-crystal Si epitaxial layers, the doping class formed on epitaxial layer
The well region that type is different, trench polysilicon grid, the source dopant region of polysilicon gate both sides, buffer layer, metal layer at top, top layer
Metal is connected with source dopant region by the metal throuth hole through buffer layer, comprises one layer of polysilicon body and one layer of silication is closed
The gate medium sealing coat that thing is formed；Include but not limited to following steps:
1) groove is formed by dry etching；
2) growth and the removal of sacrificial oxidation film is carried out at channel bottom and sidewall；
3) growth of gate dielectric layer is carried out again at channel bottom and sidewall；
4) in groove, carry out growth and the etching of grid polycrystalline silicon；
5) region between groove, is doped in the way of ion implanting or diffusion；
6) depositing silicon dioxide above total is the buffer layer of main component；
7) on described buffer layer, form top-level metallic by dry etching to be connected with source dopant region and polysilicon gate
Contact hole；
8) metal filled contact hole, forms source pressure welding point and the pressure welding point of grid in front；
Wherein step 2), sacrificial oxidation film and the growth of buffer layer described in step 6), use tubular at high temperature furnace
Become；
Grid polycrystalline silicon deposition thickness described in step 4) 6,000 10000 angstroms, grid polycrystalline silicon returns not use and covers quarter
Masterplate, after etching, grid polycrystalline silicon only remains in groove；
After doping described in step 5), it is attended by the manufacturing process utilizing high temperature furnace pipe to advance；
Buffer layer described in step 6), doped with boron or phosphorus, thickness 2,000 10000 angstroms；Step 7) is to institute
The etching stating buffer layer comprises coating photoresist, carries out photoetching, develops and etches；
Metal filled described in step 8), uses copper alusil alloy or tungsten, is formed in the way of deposit or sputtering, its
Thickness 16 microns.
In the design of mask making groove, replace with the small wire wide slots of some 0.3 1.5 microns
The big live width groove of 1.5 10 microns, is put into the polysilicon that grid bus is derived in groove, simultaneously with some little live width ditches
Groove replaces single big live width trench design.
Claims (2)
1. the manufacture method that trench semiconductor power device grid is derived, includes cellular region and grid bus is derived
District, cellular region is positioned at the middle section of layout design, is made up of some repeatability unit, and surface is drawn by contact metal, structure
Becoming MOSFET source electrode, the back side is drained as MOSFET by metal level and low resistance monocrystalline substrate layer, wherein interts ditch
Slot type is netted or strip polysilicon gate, and grid bus derives the outside being positioned at cellular region, is drawn by cellular region polysilicon gate
To being connected with top-level metallic, low resistance monocrystalline substrate layer, high resistance single-crystal Si epitaxial layers, the doping class formed on epitaxial layer
The well region that type is different, trench polysilicon grid, the source dopant region of polysilicon gate both sides, buffer layer, metal layer at top, top layer
Metal is connected with source dopant region by the metal throuth hole through buffer layer, comprises one layer of polysilicon body and one layer of silication is closed
The gate medium sealing coat that thing is formed；Include but not limited to following steps:
Groove is formed by dry etching；
Growth and the removal of sacrificial oxidation film is carried out at channel bottom and sidewall；
The growth of gate dielectric layer is carried out again at channel bottom and sidewall；
Growth and the etching of grid polycrystalline silicon is carried out in groove；
Region between groove, is doped in the way of ion implanting or diffusion；
Depositing silicon dioxide above total is the buffer layer of main component；
Described buffer layer forms top-level metallic and contacting that source dopant region and polysilicon gate are connected by dry etching
Hole；
Metal filled contact hole, forms source pressure welding point and the pressure welding point of grid in front；
Wherein step 2), sacrificial oxidation film and the growth of buffer layer described in step 6), use and formed at high temperature furnace pipe；
Grid polycrystalline silicon deposition thickness described in step 4) 6,000 10000 angstroms, grid polycrystalline silicon returns and does not use mask quarter
Version, after etching, grid polycrystalline silicon only remains in groove；
After doping described in step 5), it is attended by the manufacturing process utilizing high temperature furnace pipe to advance；
Buffer layer described in step 6), doped with boron or phosphorus, thickness 2,000 10000 angstroms；Step 7) is to being given an account of
The etching of matter sealing coat comprises coating photoresist, carries out photoetching, develops and etches；
Metal filled described in step 8), uses copper alusil alloy or tungsten, is formed, its thickness in the way of deposit or sputtering
16 microns.
2. the manufacture method derived according to a kind of trench semiconductor power device grid described in claim 1, its feature
It is: in the design of mask making groove, replace 1.5 with the small wire wide slots of some 0.3 1.5 microns
The big live width groove of 10 microns, is put into the polysilicon that grid bus is derived in groove, and replaces with some small wire wide slots simultaneously
Single big live width trench design.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110230191.7A CN102315110B (en) | 2011-08-12 | The manufacture method that a kind of trench semiconductor power device grid is derived |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110230191.7A CN102315110B (en) | 2011-08-12 | The manufacture method that a kind of trench semiconductor power device grid is derived |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102315110A CN102315110A (en) | 2012-01-11 |
| CN102315110B true CN102315110B (en) | 2016-12-14 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060746A (en) * | 1997-02-11 | 2000-05-09 | International Business Machines Corporation | Power transistor having vertical FETs and method for making same |
| CN101740388A (en) * | 2008-11-10 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing metal-semiconductor field effect transistor |
| CN102122617A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal oxide semiconductor field effect transistor |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060746A (en) * | 1997-02-11 | 2000-05-09 | International Business Machines Corporation | Power transistor having vertical FETs and method for making same |
| CN101740388A (en) * | 2008-11-10 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing metal-semiconductor field effect transistor |
| CN102122617A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal oxide semiconductor field effect transistor |
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