CN102122617A - Manufacturing method of metal oxide semiconductor field effect transistor - Google Patents
Manufacturing method of metal oxide semiconductor field effect transistor Download PDFInfo
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- CN102122617A CN102122617A CN2010100225825A CN201010022582A CN102122617A CN 102122617 A CN102122617 A CN 102122617A CN 2010100225825 A CN2010100225825 A CN 2010100225825A CN 201010022582 A CN201010022582 A CN 201010022582A CN 102122617 A CN102122617 A CN 102122617A
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Abstract
The invention relates to a manufacturing method of a metal oxide semiconductor field effect transistor, which comprises the following steps of: forming a first groove in a substrate; forming a side wall on a jamb of the first groove; epitaxially growing a conductive layer in the first groove encircled by the side wall; constantly carrying out light doping injection and source/drain injection on the substrate; removing the side wall to form a second groove; forming a gate dielectric layer on the surface of the substrate and in the second groove; and forming a grid electrode on a gate oxide layer. The manufacturing method of the metal oxide semiconductor field effect transistor can effectively inhibit short channeling effect and obtain better device performance.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, particularly the manufacture method of metal oxide semiconductor field effect tube.
Background technology
Metal oxide semiconductor field effect tube (MOSFET) is widely used a kind of semiconductor device in the present integrated circuit.With reference to shown in Figure 1, the basic structure of metal oxide semiconductor field effect tube comprises: source region 13, drain region 14 in the gate oxide 11 on substrate 10, the substrate 10, the grid 12 on the gate oxide 11 and the grid 12 both sides substrates 10.
In Chinese patent application 00134849.3 for example, mentioned a kind of conventional manufacture method of metal oxide semiconductor field effect tube, comprise: on substrate, form gate oxide and grid in regular turn, carrying out light dope again in the substrate of grid both sides injects, then form clearance wall, formation source/drain region in the substrate of clearance wall both sides then at gate lateral wall.
In the present actual production, after injecting, light dope also can anneal.In conjunction with Fig. 2 and shown in Figure 3, after light dope injected, the substrate 20 that grid 22 both sides are arranged under the gate oxide 21 can form light doping section 23a.After annealed, lateral displacement can take place in the border of described light doping section 23a, forms the light doping section 23b in bigger zone.With reference to shown in Figure 4, can find behind formation source/drain region 25 that in the substrate of clearance wall 24 both sides the most finally a of the length of effective channel of metal oxide semiconductor field effect tube after the gate patterns metallization processes shortened to b.That is to say that the length of effective channel of formed metal oxide semiconductor field effect tube has shortened with respect to design size.The shortening of described length of effective channel can cause a lot of problems, for example causes threshold voltage to change, limited the electron drift characteristic in the raceway groove etc.And the problems that caused all will influence device performance.
And along with the further microminiaturization of device size nowadays, channel length itself is also in constantly reducing.Thereby how making the channel length of metal oxide semiconductor field effect tube of actual manufacturing to adhere to specification just becomes the current problem that presses for solution.
Summary of the invention
What the present invention solved is that prior art metal oxide semiconductor field effect tube channel length in manufacture process shortens with respect to design size, influences the problem of device performance.
For addressing the above problem, the invention provides a kind of manufacture method of metal oxide semiconductor field effect tube, comprising:
In substrate, form first groove;
Sidewall at first groove forms side wall;
Epitaxial growth conductive layer in first groove that side wall surrounds;
Described substrate is carried out light dope injection and source/leakage injection, formation source/drain region in succession;
Remove described side wall and form second groove;
In described substrate surface and described second groove, form gate dielectric layer;
On described gate oxide, form grid.
Compared with prior art, the manufacture method of above-mentioned metal oxide semiconductor field effect tube has the following advantages: in the described manufacture method, gate electrode forms after source/drain region, thereby the length of effective channel of the metal oxide semiconductor field effect tube of manufacturing is that source/drain region is arranged in spacing under the grid and grid and extends to length sum under source/drain region at substrate, and it is not subjected to the technogenic influence in formation source/drain region.And above-mentioned these all depend on the thickness and the width of the side wall that forms in first groove.Therefore, just can determine the finally length of effective channel of the metal oxide semiconductor field effect tube of formation by thickness and the width that defines described side wall.
Because described length of effective channel not only comprises distance between source/drain region, also comprised the boundary length of gate electrode and substrate, so with respect to the design size of raceway groove and Yan Gengchang, thereby can more effectively avoid channel shortening and influence the situation of device performance.
Description of drawings
Fig. 1 is the basic block diagram of the metal oxide semiconductor field effect tube of prior art;
Fig. 2 to Fig. 4 is the part manufacture process schematic diagram of a kind of metal oxide semiconductor field effect tube of prior art;
Fig. 5 is a kind of execution mode flow chart of the manufacture method of metal oxide semiconductor field effect tube of the present invention;
Fig. 6 to Figure 13 is a kind of embodiment schematic diagram of the manufacture method of metal oxide semiconductor field effect tube of the present invention.
Embodiment
Can find by research the manufacture method of prior art metal oxide semiconductor field effect tube, conducting channel under the grid of metal oxide semiconductor field effect tube just finally is shaped after source/drain region forms, thereby it can be subjected to the influence of source/drain region technology.And, because the annealing after the aforementioned prior art light dope technology can cause the lateral displacement of light doping section, even thereby optimize light dope and subsequent anneal technology, existing lateral channel design still will be affected inevitably and produce the problem that length of effective channel shortens.
Based on this, the manufacture method of metal oxide semiconductor field effect tube of the present invention is by changing the formation shape of raceway groove, and the process sequence by adjustment source/drain region and grid, guarantees that length of effective channel adheres to specification.
With reference to shown in Figure 5, a kind of execution mode of the manufacture method of metal oxide semiconductor field effect tube of the present invention comprises:
Step s1 forms first groove in substrate;
Step s2 is at the sidewall formation side wall of first groove;
Step s3, epitaxial growth conductive layer in first groove that side wall surrounds;
Step s4 carries out light dope injection and source/leakage injection, formation source/drain region in succession to described substrate;
Step s5 removes described side wall and forms second groove;
Step s6 forms gate dielectric layer in described substrate surface and described second groove;
Step s7 forms grid on described gate dielectric layer.
In the above-mentioned execution mode, before forming grid, first formation source/drain region.By described process sequence adjustment with respect to prior art, the technology that can avoid source/drain region exerts an influence to the effective length of raceway groove.And, in the process that forms grid, adopted the structure of groove-shaped grid, thereby the length of effective channel of the final metal oxide semiconductor field effect tube that forms is source/drain region to be arranged in spacing under the grid and grid and to extend to length sum under source/drain region at substrate.Thereby, not only met the designing requirement of length of effective channel, also longer than design size, can more effectively avoid channel shortening and influence the situation of device performance.
And described manufacture method also will be very beneficial for the development trend that device size constantly dwindles.That is to say that along with constantly dwindling of device size, the design size of corresponding channel length is also constantly being dwindled.But still can obtain the length of effective channel longer, thereby for the sizable impetus of having further developed of manufacturing technology than design size by above-mentioned manufacture method.
Further illustrate below in conjunction with the manufacture method of accompanying drawing metal oxide semiconductor field effect tube of the present invention.
With reference to shown in Figure 6, Semiconductor substrate 100 be provided, and on described Semiconductor substrate 100, form mask graph 101.Described Semiconductor substrate 100 is generally the Semiconductor substrate that has the insulation isolation structure.Described insulation isolation structure can by shallow trench isolation for example from the method manufacturing obtain.Described mask graph 101 is formed on the Semiconductor substrate between isolation structure.Described mask graph 101 can be by forming photoresist layer on described Semiconductor substrate 100, and through exposure, develop and form.
With reference to shown in Figure 7, be mask with described mask graph 101, etching semiconductor substrate 100 forms first groove 102.Described etching can be adopted the method for dry etching.For example, can adopt chlorine (cl
2) and oxygen (O
2) mist as etching gas, use the method for plasma etching or reactive ion etching in Semiconductor substrate 100, to form first groove 102.Because the degree of depth of described first groove 102 will determine the thickness of the side wall of follow-up formation, the thickness of side wall also will determine the boundary length of the grid and the substrate of follow-up formation, and finally these parameters all will influence the length of effective raceway groove.Therefore, the degree of depth of described first groove 102 should be considered the length of effective channel that goes for and decide.
After forming first groove 102, at two side-walls formation side walls 103 of first groove 102.The material of described side wall 103 is a dielectric material, for example silica (SiO
2) or silicon nitride (SiN) or silicon oxynitride (SiON).The process that forms described side wall 103 can comprise: earlier the method that strengthens chemical vapour deposition (CVD) by for example high density ion in first groove 102 deposition of dielectric materials to filling up whole first groove 102, the dry etching dielectric material of filling subsequently, the dielectric material that only keeps described first groove, 102 sidewall sections forms side wall 103.Material with described side wall 103 is that silica is an example, can adopt to contain CF
4Etching gas.Because the width of described side wall 103 also will influence length of effective channel, so the thickness of the dielectric material that is kept behind the dry etching also should be considered the length of effective channel that goes for and decides.
With reference to shown in Figure 8, epitaxial growth conductive layer 104 in first groove 102 that described side wall 103 surrounds.Described conductive layer 104 can be the silicon that mixes.The doping type of described epitaxially grown silicon depends on the type of the field effect transistor that will make, if manufacturing N type field effect transistor, the then silicon of epitaxial growth P type doping; If manufacturing P type field effect transistor, the then silicon of epitaxial growth N type doping.
With reference to shown in Figure 9, remove mask graph 101, and conductive layer 104 and side wall 103 are carried out planarization.Described planarization can adopt the method for chemico-mechanical polishing.
With reference to shown in Figure 10, substrate 100 carried out light dope inject formation light dope knot 105, and proceed source/leakage and inject formation source/drain junction 106, with final formation source/drain region.In the process that this two steps ion injects, the effect of described side wall 103 roughly is equivalent in the prior art grid gap wall and promptly serves as the mask in the ion implantation process in the effect that light dope injects and source/leakages injected, to realize self aligned ion injection.
Alternatively, the degree of depth of described source/drain junction 106 will be shallower than the degree of depth of light dope knot 105, with the field inductive effect (field induced effect) that reduces to cause owing to source/drain junction 106.
Alternatively, the process of injecting at light dope can also adopt halo (Halo) to inject, to suppress short-channel effect.
Alternatively, after light dope injection and source/leakage injection, also can anneal.
With reference to shown in Figure 11, after above-mentioned two steps ions injection, source/drain region forms prior to grid, owing to also do not form raceway groove this moment, thereby the effective length of raceway groove can't be received the technogenic influence in source/drain region.For forming grid, at first to remove described side wall 103 and form second groove 107, described second groove 107 is exactly the place of follow-up formation grid, has also roughly determined the channel shape of the field effect transistor of final formation simultaneously.Owing to be that integral body is peeled off, thereby remove the method that described side wall 103 can adopt wet etching.Material with described side wall 103 is that silica is an example, can adopt the etchant of hydrofluoric acid containing (HF), for example dilute hydrofluoric acid or hydrofluoric acid buffered etch liquid.
With reference to shown in Figure 12, after forming second groove 107, in substrate 100 surfaces and second groove 107, form gate dielectric layer.
Specifically, at first in substrate 100 surfaces and second groove 107, form gate dielectric layer 108a.The material of described gate dielectric layer 108a can be silica.Described silica can be by the method growth of boiler tube thermal oxidation.
With reference to shown in Figure 13, on described gate dielectric layer 108a, form grid layer.The material of described grid layer can be polysilicon, and described polysilicon can adopt the method for chemical vapour deposition (CVD) to form.
Subsequently, the etching grid layer forms grid 109, and continues the gate dielectric layer 108a under the etching grid layer subsequently, only keeps the gate dielectric layer 108a part under the grid 109.Described two step etching can adopt the method for dry etching.
Then, heat-treat step, the gate dielectric layer 108a that makes grid be positioned at second groove, 107 corners for 109 times partly thickens, and forms gate dielectric layer 108b.Described thicker gate dielectric layer 108b can avoid the generation of gate induced drain electric leakage (GIDL, Gate-induced drain leakage) phenomenon.
Alternatively, described heat treatment comprises described substrate 100 is carried out dry-oxygen oxidation.Specifically, described substrate 100 placed under 800～1000 ℃ the oxygen atmosphere and carry out oxidation reaction, the gate dielectric layer 108a that makes grid be positioned at second groove, 107 corners for 109 times partly thickens.The time of described oxidation reaction is 5～30 minutes.
Alternatively, described heat treatment comprises described substrate 100 is carried out wet-oxygen oxidation.Specifically, described substrate 100 placed under 800～1000 ℃ the mist atmosphere of hydrogen, oxygen and carry out oxidation reaction, the gate dielectric layer 108a that makes grid be positioned at second groove, 107 corners for 109 times partly thickens.The time of described oxidation reaction is 5～30 minutes.
So far, the general configuration of metal oxide semiconductor field effect tube forms, and follow-up can passing through forms steps such as Metal Contact at grid and source/drain region, with the complete metal oxide semiconductor field effect tube of final formation.
Can see also that from the manufacture process of above-mentioned metal oxide semiconductor field effect tube of giving an example above-mentioned manufacture process can once be made the field effect transistor in two common source/drain regions, thereby more help the integrated of technology.
Continue with reference to shown in Figure 13, described metal oxide semiconductor field effect tube comprises:
Groove-shaped grid 109 in the substrate 100, itself and 100 of substrates have gate oxide 108b;
Source/drain region in the substrate 100 of grid 109 both sides.
In the described metal oxide semiconductor field effect tube, length of effective channel comprises 3 parts: source/drain region is positioned at the spacing d under the grid 109, and grid 109 extends to the length c+e under source/drain region in substrate 100.Therefore, Shi Ji length of effective channel is d+c+e.Because the channel dimensions of general metal oxide semiconductor field effect tube all is to design with the spacing that source/drain region is positioned under the grid, so metal oxide semiconductor field effect tube of process the foregoing description manufacturing, its length of effective channel is also longer than design size, thereby for the development that further reduces of device size sizable impetus is arranged.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. the manufacture method of a metal oxide semiconductor field effect tube is characterized in that, comprising:
In substrate, form first groove;
Sidewall at first groove forms side wall;
Epitaxial growth conductive layer in first groove that side wall surrounds;
Described substrate is carried out light dope injection and source/leakage injection, formation source/drain region in succession;
Remove described side wall and form second groove;
In described substrate surface and described second groove, form gate dielectric layer;
On described gate dielectric layer, form grid.
2. the manufacture method of metal oxide semiconductor field effect tube as claimed in claim 1 is characterized in that, forms side wall at the sidewall of first groove and comprises:
Filled dielectric material in first groove;
The described dielectric material of etching forms side wall.
3. the manufacture method of metal oxide semiconductor field effect tube as claimed in claim 2 is characterized in that, described dielectric material is silica or silicon nitride or silicon oxynitride.
4. the manufacture method of metal oxide semiconductor field effect tube as claimed in claim 1 is characterized in that, the silicon of described conductive layer for mixing.
5. the manufacture method of metal oxide semiconductor field effect tube as claimed in claim 1 is characterized in that, the degree of depth that the source/drain junction that forms is injected in described source/leakage is shallower than the light dope knot that light dope injects formation.
6. the manufacture method of metal oxide semiconductor field effect tube as claimed in claim 1 is characterized in that, removes the method that described side wall adopts wet etching.
7. the manufacture method of metal oxide semiconductor field effect tube as claimed in claim 1, it is characterized in that, also comprise: after forming grid, heat-treat step, make that the gate dielectric layer part that is arranged in the second groove corner under the grid is thicker with respect to the part of second groove.
8. the manufacture method of metal oxide semiconductor field effect tube as claimed in claim 1 is characterized in that, the material of described gate dielectric layer is a silica.
9. the manufacture method of metal oxide semiconductor field effect tube as claimed in claim 1 is characterized in that, the material of described grid is a polysilicon.
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| CN2010100225825A CN102122617B (en) | 2010-01-08 | 2010-01-08 | Manufacturing method of metal oxide semiconductor field effect transistor |
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| CN2010100225825A CN102122617B (en) | 2010-01-08 | 2010-01-08 | Manufacturing method of metal oxide semiconductor field effect transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315110A (en) * | 2011-08-12 | 2012-01-11 | 科达半导体有限公司 | Groove-type semiconductor power-device grid-electrode leading-out designing and manufacturing method |
| CN102315110B (en) * | 2011-08-12 | 2016-12-14 | 科达半导体有限公司 | The manufacture method that a kind of trench semiconductor power device grid is derived |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2006344759A (en) * | 2005-06-08 | 2006-12-21 | Sharp Corp | Trench type mosfet and its fabrication process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315110A (en) * | 2011-08-12 | 2012-01-11 | 科达半导体有限公司 | Groove-type semiconductor power-device grid-electrode leading-out designing and manufacturing method |
| CN102315110B (en) * | 2011-08-12 | 2016-12-14 | 科达半导体有限公司 | The manufacture method that a kind of trench semiconductor power device grid is derived |
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Owner name: SEMICONDUCTOR MANUFACTURING (BEIJING) INTERNATIONA Effective date: 20121102 |
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Effective date of registration: 20121102 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |