CN102315106B - Laser thermal annealing method - Google Patents

Laser thermal annealing method Download PDF

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CN102315106B
CN102315106B CN 201010228206 CN201010228206A CN102315106B CN 102315106 B CN102315106 B CN 102315106B CN 201010228206 CN201010228206 CN 201010228206 CN 201010228206 A CN201010228206 A CN 201010228206A CN 102315106 B CN102315106 B CN 102315106B
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laser
laser heat
semiconductor wafer
annealing
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CN102315106A (en
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陈勇
何永根
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

The invention relates to a laser thermal annealing method, which comprises the following steps of: a, performing a first laser thermal annealing process on a semiconductor chip; b, rotating the semiconductor chip around the center of the semiconductor chip at an angle; and c, performing a second laser thermal annealing process on the semiconductor chip. The angle of the chip is adjusted before secondary route scanning of laser thermal annealing, so the problem of chip warpage caused by the laser thermal annealing can be solved effectively; furthermore, by the method for adjusting the angle ofthe chip before the secondary route scanning, two adjacent rows of laser beam scanning routes are not stacked, and the problem of cascade staggering of the chip can be solved effectively. The method is simple in main operation and convenient to implement; and an effect of reducing the warpage of the chip is obvious. The method can be widely applied to a process for manufacturing the semiconductorchip.

Description

A kind of LASER HEAT method for annealing
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of LASER HEAT method for annealing.
Background technology
(Metal-Oxide-Semiconductor Field-Effect Transistor MOSFET), is a kind of field-effect transistor that can be widely used in analog circuit and the digital circuit to the metal oxide layer semiconductor field-effect transistor.MOSFET can be divided into the MOSFET of n-type and p-type according to the polarity difference of its " conducting channel ", is called NMOSFET and PMOSFET usually again.
In the past few decades, the continuous size that develops MOSFET along with the MOSFET manufacture craft constantly diminishes.In the early stage semiconductor circuit MOSFET technology, channel length is about several microns grade.But to the semiconductor circuit technology of today, this parameter has been dwindled tens times even above 100 times.To the end of the nineties, the MOSFET size is constantly dwindled, and allows the usefulness of semiconductor circuit promote greatly.Along with the area of MOSFET is more little, the cost of making chip just can reduce, and can load more highdensity chip in same encapsulation.The wafer size that a slice integrated circuit technology is used is fixed, so if chip area is more little, onesize wafer just can the more chip of output, so that cost just becomes is lower.
But the reducing of MOSFET size also can bring some negative problems.For example, channel width diminishes and can make raceway groove equivalent electric resistive big.Existing a kind of technology that improves the field-effect transistor carrier mobility is stress memory technique (Stress Memorization Technique, be called for short SMT), form stable stress by the channel region at field-effect transistor, improve the carrier mobility in the raceway groove, namely reduced the raceway groove equivalent resistance.Usually tensile stress can be so that the molecules align in the channel region be more loose, thereby improves the mobility of electronics, is applicable to N-type MOS (following represent with NMOS) transistor; And compression makes that the molecular arrangement in the channel region is tightr, helps to improve the mobility in hole, is applicable to P type MOS (following represent with PMOS) transistor.Prior art usually in the transistorized source of PMOS/position, drain region embeds germanium silicon (SiGe) layer and introduces compression, improving hole mobility and to obtain higher drive current, and this technology can be applied to the technology of 45nm by the concentration that changes germanium.The germanium silicon condensate source-drain electrode with low resistance characteristic that adopts meticulous controlled doping concentration to make, and be control complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor, the CMOS) key factor of size by the short-channel effect that minimizes that the shallow-layer doping way forms.
Therefore, described have embedded germanium silicon (Embeded SiGe, eSiGe) Ceng source/drain structure be widely used in the PMOS transistor.After embedding germanium silicon layer technology, can carry out annealing process usually with lax described germanium silicon layer, reduce the transistorized defect concentration of PMOS and junction leakage current.Annealing process of the prior art have super annealing (Super Anneal), rapid thermal annealing (Rapid Thermal Annealing, RTA), millisecond annealing (Millisecond Anneal, MSA) etc.Fig. 1 shows the millisecond annealing flow process of prior art, at first, laser beam carries out first stroke to semiconductor wafer and scans S1, the laser beam that is produced by laser to scanning of described semiconductor wafer be according to from bottom to top, about back and forth processing track carry out.Specifically: find the telltale mark N (being wafer breach notch) of semiconductor wafer, when first row scanned, laser beam scanned from left to right from the lower end of described semiconductor wafer; Then, adjust on the described laser beam and move certain distance, described distance equals half of length L of described laser beam, and namely degree of overlapping is 50%, and wherein, laser beam length L is the half-peak breadth of the intensity of the laser beam that sends of laser; Then, when second row scanned, laser beam scanned from the right side from the lower end of described semiconductor wafer with turning left; Repeat above steps, back and forth scan from the right side more from left to right with turning left, until laser beam described semiconductor wafer is entirely scanned one time, finish the LASER HEAT annealing process S1 of first stroke.Then, carry out second stroke again and scan S2, described second stroke scans S2 and first stroke, and to scan the S1 mode identical, repeats no more herein.
After executing millisecond annealing, find that the germanium silicon condensate in the source-drain electrode stress relaxation occurred under hot environment, occur under the effect of stress relaxation at germanium silicon condensate, germanium silicon condensate may relative displacement occur and cause stacked dislocation (Overlay, OVL) problem, the OVL problem often is embodied on the wafer distortion, and then causes device performance to descend; What is worse,, cause connecting leak rate and significantly rise to the defective diffusion of going deep into silicon base from germanium silicon polymer layer.
In order to reduce the chip warpage problem, the way of prior art is: reduce the temperature of the used laser beam of LASER HEAT annealing, but after temperature reduces, the liveness of germanium silicon layer ion is reduced, namely increased the resistance value of active area.Therefore, the germanium silicon condensate stress relaxation of being brought by LASER HEAT annealing and the problem of the chip warpage that causes, stacked dislocation becomes problem that urgent need overcomes in the semiconductor integrated circuit manufacturing process.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The chip warpage that causes, the problem of stacked dislocation in order to solve in the prior art germanium silicon condensate stress relaxation brought by LASER HEAT annealing, the invention provides a kind of LASER HEAT method for annealing, comprising: a. carries out the first LASER HEAT annealing process to described semiconductor wafer; B. described semiconductor wafer is rotated an angle around its center; C. described semiconductor wafer is carried out the second LASER HEAT annealing process.
According to a further aspect in the invention, the described first LASER HEAT annealing process and the described second LASER HEAT annealing process are to be undertaken by the surface that laser beam is swept described semiconductor wafer.
According to a further aspect in the invention, after described step a, described laser beam is moved a distance along the direction that is parallel to described semiconductor wafer surface.
According to a further aspect in the invention, described distance equals the length of laser beam or half of described laser beam length.
According to a further aspect in the invention, the length of described laser beam is the half-peak breadth of described laser beam intensity.
According to a further aspect in the invention, the annealing of described first and second LASER HEAT adopts arc to scan mode.
According to a further aspect in the invention, the linear mode of scanning of described first and second LASER HEAT annealing employing.
According to a further aspect in the invention, the angle of described rotation is 44～46 degree, 89～91 degree or 134～136 degree.
According to a further aspect in the invention, the angle of described rotation is 45 degree, 90 degree or 135 degree.
According to a further aspect in the invention, carbon dioxide laser is adopted in the annealing of described first and second LASER HEAT.
The present invention is by adjusting the angle of wafer before the scanning of stroke in the second time of LASER HEAT annealing, the chip warpage problem that LASER HEAT annealing is caused has obtained effective solution.In addition, the present invention also adopts by adjust the method for wafer angle before the scanning of stroke in the second time, make simultaneously adjacent two the row the lasering beam sweep paths between do not have overlapping, the mode of scanning of this LASER HEAT annealing can more effectively solve the chip warpage problem of being brought by LASER HEAT annealing with respect to preceding a kind of mode, and then effectively solves the stacked problem of misalignment of wafer.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is that the mode schematic diagram is scanned in existing LASER HEAT annealing;
Fig. 2 is that the mode schematic diagram is scanned in the LASER HEAT annealing of the embodiment of the invention one;
The angularity contrast schematic diagram of Fig. 3 semiconductor wafer that to be the embodiment of the invention one cause with the existing LASER HEAT annealing mode of scanning;
Fig. 4 is that the mode schematic diagram is scanned in the LASER HEAT annealing of the embodiment of the invention two;
The angularity contrast schematic diagram of Fig. 5 semiconductor wafer that to be the embodiment of the invention two cause with the LASER HEAT annealing mode of scanning of embodiment one;
Fig. 6 is the OVL that shows by lithography apparatus;
The stacked dislocation contrast schematic diagram of the semiconductor wafer that the LASER HEAT annealing mode of scanning of Fig. 7 embodiment of the invention two and embodiment one causes.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention utilizes heavily stressed cover layer and passivation layer stacked structure in order to solve the problem of chip warpage.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
The present invention proposes a kind of new LASER HEAT method for annealing and solve chip warpage that the LASER HEAT annealing process brings and the problem of stacked dislocation.Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Embodiment one
Fig. 2 shows the schematic flow sheet of the LASER HEAT annealing in the embodiments of the invention one.
Step 201 provides to be formed with the transistorized semiconductor wafer of PMOS, and described PMOS transistor has the source/drain structure of embedded germanium silicon layer.
Step 202, described semiconductor wafer is carried out the LASER HEAT annealing process S1 of first stroke: laser beam scans from about the semiconductor wafer lower end to and fro.When scanning first row, laser beam scans from left to right from the lower end of semiconductor wafer, and scanning the path is arc; Then, laser beam is moved certain distance along the direction that is parallel to described semiconductor wafer surface.Particularly, on move laser beam length L half distance, i.e. L/2, right-to-left carries out scanning of next line again; Repeat above-mentioned steps, scan one time semiconductor wafer is whole until laser beam, finish the LASER HEAT annealing process S1 of first stroke.
Step 203 is adjusted the position of described semiconductor wafer, with described semiconductor wafer in a clockwise direction or counterclockwise rotate about 90 degree.Specifically comprise: clockwise or be rotated counterclockwise described semiconductor wafer, the original coordinate before making the new coordinate of postrotational telltale mark N with respect to rotation differs about an angle of 90 degrees.
Step 204, described semiconductor wafer is carried out the LASER HEAT annealing process S2 of second stroke: similar with the LASER HEAT annealing process S1 of first stroke in the step 202, when first row scans, laser beam scans from left to right from the lower end of described semiconductor wafer, and scanning formed path is arc; Then, will move half distance L/2 of laser beam length L on the laser beam, the degree of overlapping of namely scanning the path is 50%, and when second row scanned, laser beam scanned from the right side from the lower end of described semiconductor wafer with turning left; Repeat above steps, back and forth scan from the right side more from left to right, until by laser beam described semiconductor wafer entirely being scanned one time with turning left.The paths intersect of scanning of scanning path and the first stroke laser thermal anneal process S1 of the second stroke laser thermal anneal process S2 is finished the LASER HEAT annealing process S2 of second stroke.
Fig. 3 shows the result who compares according to the LASER HEAT annealing way of introducing among the LASER HEAT annealing way of introducing in the background technology and the embodiment one, from Fig. 3, can draw: when adopting the LASER HEAT annealing way in the background technology, carry out and do not rotate semiconductor wafer when second stroke scans S2, then finish after the LASER HEAT annealing, the x direction of principal axis of semiconductor wafer and the warpage degree on the y direction of principal axis differ greatly.Scan mode if adopt the LASER HEAT annealing among the embodiment one, carrying out second stroke scans and semiconductor wafer must be rotated about 90 degree before the S2, then finish after the LASER HEAT annealing, though x direction of principal axis chip warpage scans the axial warpage of the x that brings more than existing LASER HEAT annealing, but the warpage degree on the semiconductor wafer on x direction of principal axis and the y direction of principal axis is almost identical, the degree of this explanation warpage is that namely warpage issues has obtained reduction uniformly at both direction.
Embodiment two
Fig. 4 shows the LASER HEAT annealing schematic flow sheet of embodiments of the invention two.
Step 401 provides to be formed with the transistorized semiconductor wafer of PMOS, and described PMOS transistor has the source/drain structure of embedded germanium silicon layer;
Step 402 is carried out the LASER HEAT annealing process S1 of first stroke: scan to and fro from about the semiconductor wafer lower end to described semiconductor wafer.When scanning first row, laser beam scans from left to right from the lower end of semiconductor wafer, and scanning the path is arc; Then, will move the distance L of whole laser beams length on the laser beam, right-to-left carries out scanning of next line again; Repeat above-mentioned steps, scan one time semiconductor wafer is whole until laser beam, finish the LASER HEAT annealing process S1 of first stroke.
Step 403 is adjusted the position of described semiconductor wafer, with described semiconductor wafer in a clockwise direction or counterclockwise revolve and turn 90 degrees.Specifically comprise: clockwise or be rotated counterclockwise described semiconductor wafer, the original coordinate before making the new coordinate of postrotational telltale mark N with respect to rotation differs about an angle of 90 degrees.
Step 404, described semiconductor wafer is carried out the LASER HEAT annealing process S2 of second stroke: similar with the LASER HEAT annealing process S1 of first stroke in the step 402, when first row scans, laser beam scans from left to right from the lower end of described semiconductor wafer, and scanning formed path is arc; Then, will move the distance L of whole laser beams length on the laser beam, namely the path overlap degree that scans of twice stroke is 0.When second row scanned, laser beam scanned from the right side from the lower end of described semiconductor wafer with turning left; Repeat above steps, back and forth scan from the right side more from left to right with turning left, until by laser beam described semiconductor wafer entirely being scanned one time, the paths intersect of scanning of scanning path and the first stroke laser thermal anneal process S1 of the second stroke laser thermal anneal process S2 is finished the LASER HEAT annealing process S2 of second stroke.
In above-described embodiment, the laser beam of carrying out LASER HEAT annealing can be produced by laser, and described laser is carbon dioxide laser.Can select the specification of laser beam as required.
Need to prove, in step 203 and step 403, the about an angle of 90 degrees of semiconductor wafer rotation can also be made accommodation according to actual conditions when carrying out the LASER HEAT annealing process S2 of second stroke, for example the anglec of rotation is 45 degree or 135 degree, and direction of rotation is for all can clockwise or counterclockwise.And when the anglec of rotation is 45 degree and 135 when spending, warpage effect and the anglec of rotation are 90 similar when spending.In addition, experimental result shows, when the anglec of rotation be 44～46 degree, when 89～91 degree or 134～136 are spent, its effect is similar with rotation 45 degree, 90 degree or 135 degree.
Be to realize that by the position of adjusting described semiconductor wafer scanning in the LASER HEAT annealing process of adjacent two strokes keeps between the path intersecting in step 203 and the step 403, but not as limit, in other embodiments, sweep directions that also can be by adjusting the LASER HEAT annealing process or adjust the position of described semiconductor wafer simultaneously and the sweep directions of LASER HEAT annealing process realizes, about the technology of the sweep directions of the position of adjusting described semiconductor wafer and LASER HEAT annealing process is well known to those of ordinary skill in the art, so do not repeat them here.
Similarly, step 202,204,402 and 404 also can be done other forms of change.For example, the linear that described LASER HEAT annealing process also can adopt scans mode (being that the formed path of scanning of laser beam is linear) and realizes, back and forth scanned in the rectilinear mode of scanning by the laser beam that produces, until by laser beam described semiconductor wafer entirely being scanned one time; In addition, adjust described laser and move certain distance and also can move down corresponding distance and realize having similar effects by adjusting described semiconductor wafer once scanning the back.
Fig. 5 shows the angularity contrast schematic diagram of the semiconductor wafer that the LASER HEAT annealing way of the LASER HEAT annealing way of embodiment two and embodiment one brings.Wherein, carry out second stroke among the embodiment one and scan before the S2, semiconductor wafer must be rotated about 90 degree, the distance of moving on the laser beam between each row is half of whole laser beams length L, and the degree of overlapping of namely scanning the path is 50%.Carry out second stroke among the embodiment two and scan before the S2, equally semiconductor wafer is rotated about 90 degree, the distance of moving on the laser beam between each row is the whole laser beams length L, and the degree of overlapping of namely scanning the path is 0.As can be seen from Figure 5, it all is uniformly that the LASER HEAT annealing of dual mode makes the angularity of semiconductor wafer on x direction of principal axis and y direction of principal axis, and the annealing of the LASER HEAT among the embodiment two mode of scanning all reduces the angularity of wafer on x direction of principal axis, y direction of principal axis with respect to the annealing of the LASER HEAT among the embodiment one mode of scanning to some extent.
In the manufacture craft of semiconductor wafer, after being formed with the source region, need form contact hole (CT at source electrode, the drain and gate of active area (AA), Contact), here, regard the active area that forms as preceding one deck, the contact hole that will form at active area is as back one deck.Can realize being connected of active area and extraneous circuit by contact hole.Therefore, ideal situation is that the center of contact hole is accurately aimed at the center of active area.But in the practical operation, accurately aim at and be difficult to realize, because execute after the LASER HEAT annealing process, germanium silicon condensate will relative displacement occur and cause (the Overlay of stacked dislocation, OVL) problem, the dotted line cross among Fig. 6 represents the center of active area, and the solid line cross represents the center of contact hole, namely the distance between two centers is more short, illustrates that the Aligning degree of wafer is unreasonable to think.
Fig. 7 shows the stacked dislocation contrast schematic diagram of the semiconductor wafer of embodiment one and embodiment two.As can be seen from the figure, scan under the mode in the LASER HEAT annealing of embodiment two, OVL numerical value scans mode less than the LASER HEAT annealing of embodiment one.And OVL numerical value is more little, shows that this mode of scanning can reduce the stress relaxation that germanium silicon condensate occurs more effectively, has also just reduced wafer distortion better.
Two kinds of execution modes of the present invention are simple to operate.Wherein, first kind of LASER HEAT annealed, and the mode of scanning need only be reversed 45 degree with semiconductor wafer clockwise or counterclockwise before the LASER HEAT annealing of second stroke, 90 degree or 135 are spent, through experiment relatively, this LASER HEAT annealing is scanned mode and is scanned mode than existing LASER HEAT annealing, can reduce the buckling deformation of wafer.And second kind of LASER HEAT annealing mode of scanning not only need be between the LASER HEAT annealing of twice stroke be reversed semiconductor wafer 45 degree, 90 degree or 135 degree clockwise or counterclockwise, and the lasering beam sweep paths of adjacent two row do not have overlapping.The mode of scanning of this LASER HEAT annealing can reduce the buckling deformation of wafer than preceding a kind of mode of scanning, and solves stacked dislocation (OVL) problem of wafer effectively.
In addition, because LASER HEAT annealing way of the present invention can reduce the warpage issues of the wafer that is brought by LASER HEAT annealing under the situation of the temperature that does not reduce laser beam, do not influence the liveness of the ion of germanium silicon layer simultaneously, can not increase the resistance value of active area.Therefore the present invention can improve the product yield than LASER HEAT annealing way of the prior art.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.

Claims (9)

1. the LASER HEAT method for annealing of a semiconductor wafer comprises the following steps:
A. described semiconductor wafer is carried out the first LASER HEAT annealing process, the described first LASER HEAT annealing process is to be undertaken by the surface of the described semiconductor wafer of lasering beam sweep;
After described step a, laser beam is moved certain distance along the direction that is parallel to described semiconductor wafer surface;
B. described semiconductor wafer is rotated an angle around its center;
C. described semiconductor wafer is carried out the second LASER HEAT annealing process.
2. LASER HEAT method for annealing according to claim 1, it is characterized in that: the described second LASER HEAT annealing process is to be undertaken by the surface of the described semiconductor wafer of lasering beam sweep.
3. LASER HEAT method for annealing according to claim 1, it is characterized in that: described distance equals the length of laser beam or half of described laser beam length.
4. LASER HEAT method for annealing according to claim 3, it is characterized in that: the length of described laser beam is the half-peak breadth of described laser beam intensity.
5. LASER HEAT method for annealing according to claim 2 is characterized in that: described first and second LASER HEAT annealing adopts arc to scan mode.
6. LASER HEAT method for annealing according to claim 2 is characterized in that: the linear mode of scanning of described first and second LASER HEAT annealing employing.
7. LASER HEAT method for annealing according to claim 1 is characterized in that: the angle of described rotation is 44～46 degree, 89～91 degree or 134～136 degree.
8. LASER HEAT method for annealing according to claim 7 is characterized in that: the angle of described rotation is 45 degree, 90 degree or 135 degree.
9. LASER HEAT method for annealing according to claim 1 is characterized in that: described first and second LASER HEAT annealing employing carbon dioxide laser.
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JP2001189282A (en) * 1999-12-28 2001-07-10 Japan Steel Works Ltd:The Method and apparatus for laser annealing
CN1992167A (en) * 2005-12-29 2007-07-04 财团法人工业技术研究院 Method for forming polycrystalline silicon film
CN101369526A (en) * 2007-08-15 2009-02-18 应用材料股份有限公司 Pulsed laser anneal system architecture
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