CN102306632B - Planarization method suitable for photoetching technology - Google Patents
Planarization method suitable for photoetching technology Download PDFInfo
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- CN102306632B CN102306632B CN 201110264528 CN201110264528A CN102306632B CN 102306632 B CN102306632 B CN 102306632B CN 201110264528 CN201110264528 CN 201110264528 CN 201110264528 A CN201110264528 A CN 201110264528A CN 102306632 B CN102306632 B CN 102306632B
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- dielectric layer
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- photoresist
- photoetching
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Abstract
The invention discloses a planarization method suitable for a photoetching technology. The method comprises the following steps: coating a dielectric layer on the surface of a substrate by adopting a spin coating method, wherein the dielectric layer covers a stage with the height about 20mu m for the surface of the substrate, and a planar surface is formed on the surface of the substrate; then photoetching the substrate using a photoresist with a low-viscosity coefficient again after the substrate is dried; preparing a UBM (ultrasound microscopy) layer through a wet etching technology; and finally removing the dielectric layer in the process of degumming. Through the method, the UBM layer with a salient point with lineation/ spacing 150mu m/100mu m and height 20mu m is manufactured, and the technological requirement of salient point blind print is satisfied; and the technology has good consistency, the technology process is simple, the production efficiency is high, the method is suitable for mass production, and the products meet the reliable requirement.
Description
Technical field:
The invention belongs to microelectronics manufacture and field of semiconductor manufacture; The present invention relates to a kind of low cost and on wafer, contain the highly UBM layer making of step of 20 μ m with low viscosity coefficient photoresist and media implementation with moderate coefficient of viscosity.
Background technology:
In microelectronics manufacture and semiconductor fabrication process, mostly the covering problem that solves high step in the photoetching process is to select for use the photoresist of high viscosity coefficient to cover step, carries out photoetching more at present; Or carry out photoetching earlier and make step again.Re-use the method that low viscosity coefficient photoresist carries out photoetching and do not appear in the newspapers and the medium that adopts a kind of moderate coefficient of viscosity covers step.
Summary of the invention:
Select for use the photoresist of high viscosity coefficient to cover step at present, the employed material of method (photoresist) cost that carries out photoetching again is higher, and requires also higher to employed lithographic equipment (mask aligner etc.).Make step again with regard to needs design technology flow process again and carry out photoetching earlier, make whole making flow process become complicated.Adopt this method can save material cost and equipment cost, make technological process simple.
The objective of the invention is to overcome the shortcoming of above-mentioned prior art; A kind of flattening method that is applicable to photoetching process is provided; Adopt spin-coating method to apply one deck dielectric layer at substrate surface, the step that the about 20 μ m in dielectric layer covering substrate surface are high also makes substrate surface form a smooth surface, then substrate is re-used low viscosity coefficient photoresist after oven dry and carries out photoetching; Produce the UBM layer through wet corrosion technique, in the process of removing photoresist, remove dielectric layer at last simultaneously.
The material of said dielectric layer is a polyimides.
Said coating rotating speed is 500 rev/mins, and the coating time is 2 minutes; Apply to accomplish after 100 ℃ of oven dry, drying time is 40 minutes.
Produced lines/spacing 150 μ m/100 μ m and had height 20 through this method
The UBM layer of μ m bump pad satisfies the technological requirement that salient point is bitten.Process consistency is good, and technological process is simple, production efficiency is high, be suitable for production in enormous quantities, and product satisfies reliability requirement.
Description of drawings:
Fig. 1 is a planarization photo-etching technological process sketch map of the present invention;
Wherein: 1 is substrate; 2 is the secondary conduction band; 3 is bump pad; 4 is polyimides; 5 are light sensitive photoresist not; 6 is mask; 7 is light sensitive photoresist.
Embodiment:
Below in conjunction with accompanying drawing the present invention is done and to describe in further detail:
Referring to Fig. 1; Before photoetching; Rotating speed when adopting spin-coating method to apply through control and time apply certain thickness dielectric layer (having moderate viscosity coefficient) at substrate surface and come the step of the about 20 μ m of covering surfaces and form a relative more smooth surface; Substrate re-uses low viscosity coefficient photoresist and carries out photoetching after oven dry, produce the UBM layer through wet corrosion technique, in the process of removing photoresist, removes dielectric layer at last simultaneously.
The medium that uses among the present invention is polyimides, is coated in substrate surface through spin-coating method, and applying rotating speed is 500 rev/mins, and the coating time is 2 minutes; Apply to accomplish after 100 ℃ of oven dry, drying time is 40 minutes.Making substrate surface form a relative more smooth surface uses the photoresist of low viscosity coefficient to carry out photoetching then.The developer solution of photoresist can be used as the corrosive liquid of polyimides in the present invention, so substrate can obtain qualified mask again through developing behind post bake.After etching, can remove photoresist earlier, remove polyimides, also can use fuming nitric aicd in the process of removing photoresist, to remove polyimides simultaneously with developer solution.
Adopt 771 chips that produce 314, carry out secondary wiring after, the pad height is 20 μ m,
After the secondary wiring: the wiring on the chip is checked, uses scale microscope to measure.The diameter of pad directly is 150 μ m, spacing 250 μ m.
Use α-step500 step tester to measure the bump pad height, measure the chip of 5 positions on the wafer, measure 7 points on each chip, measurement data is seen table 1.
Table 1 bump pad height meter
Show in the table that the bump pad altitude range is 19 μ m～20 μ m (in the disks).Maximum height tolerance in the chip ± 0.96 μ m.
Conclusion: realized that live width/spacing is 150 microns/100 microns secondary wirings and the making that has bump pad (diameter 150 μ m, spacing 250 μ m, height 19 μ m～20 μ m) on wafer.
Above content is to combine concrete preferred implementation to further explain that the present invention did; Can not assert that embodiment of the present invention only limits to this; Those of ordinary skill for technical field under the present invention; Under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to the present invention and confirm scope of patent protection by claims of being submitted to.
Claims (3)
1. flattening method that is applicable to photoetching process; It is characterized in that: adopt spin-coating method to apply one deck dielectric layer at substrate surface; The step that the about 20 μ m in dielectric layer covering substrate surface are high also makes substrate surface form a smooth surface; Then substrate is re-used low viscosity coefficient photoresist after oven dry and carry out photoetching, remove the dielectric layer of light sensitive photoresist and below thereof, expose UBM layer to be corroded through developing; Produce the UBM layer through wet corrosion technique, in removing residue photoresist process, remove remaining dielectric layer simultaneously at last.
2. be applicable to the flattening method of photoetching process according to claim 1, it is characterized in that: the material of said dielectric layer is a polyimides.
3. be applicable to the flattening method of photoetching process according to claim 1, it is characterized in that: said coating rotating speed is 500 rev/mins, and the coating time is 2 minutes; Apply to accomplish after 100 ℃ of oven dry, drying time is 40 minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110264528 CN102306632B (en) | 2011-09-07 | 2011-09-07 | Planarization method suitable for photoetching technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110264528 CN102306632B (en) | 2011-09-07 | 2011-09-07 | Planarization method suitable for photoetching technology |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102306632A CN102306632A (en) | 2012-01-04 |
| CN102306632B true CN102306632B (en) | 2012-10-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110264528 Expired - Fee Related CN102306632B (en) | 2011-09-07 | 2011-09-07 | Planarization method suitable for photoetching technology |
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| CN (1) | CN102306632B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107920418A (en) * | 2016-10-10 | 2018-04-17 | 上海和辉光电有限公司 | A kind of flexible base board manufacture method |
| CN114976564B (en) * | 2022-05-24 | 2023-12-01 | 中国电子科技集团公司第五十五研究所 | Manufacturing method of air composite medium microstrip line |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI232560B (en) * | 2002-04-23 | 2005-05-11 | Sanyo Electric Co | Semiconductor device and its manufacture |
| JP4458307B2 (en) * | 2008-01-28 | 2010-04-28 | 株式会社村田製作所 | Semiconductor integrated circuit device, mounting structure of semiconductor integrated circuit device, and manufacturing method of semiconductor integrated circuit device |
| CN101733585B (en) * | 2010-02-10 | 2012-09-19 | 北京海斯迪克新材料有限公司 | Bump protective layer for packaging wafer-level chip and its forming process |
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| CN102306632A (en) | 2012-01-04 |
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Granted publication date: 20121031 Termination date: 20180907 |