CN102299703B - Interlock circuit and the interlock system including this interlock circuit - Google Patents

Abstract

The present invention relates to a kind of interlock circuit and include the interlock system of this interlock circuit, this interlock circuit includes input delay unit and output suppression unit.The multiple input signal of input delay cell delay, multiple delay input signal is provided and provides multiple exclusive input signal by multiple delay input signals being carried out logical operations.Output suppresses multiple output signals that unit provides non-concurrent to enable based on multiple exclusive input signals and multiple input signal.

Description

Interlock circuit and the interlock system including this interlock circuit

The cross reference of related application

This application claims on June 24th, 2010 submit to Korean Intellectual Property Office The rights and interests of 10-2010-0060098 korean patent application, the full content of this Korean Patent Application Publication passes through It is incorporated by the application.

Technical field

The present invention relates to a kind of interlock circuit, and relate more specifically to a kind of for carrying out FIFO (FIFO) interlock circuit operated and a kind of interlock system including this interlock circuit.

Background technology

Interlock circuit refers to following circuit: when a circuit in multiple circuit operates, even if to institute State other circuit in multiple circuit and apply input signal, be also prevented from these other circuit and operate.The most just Being to say, interlock circuit refers to for preventing circuit operation until meeting the circuit of specified conditions.

Summary of the invention

The present invention provides a kind of interlock circuit and a kind of interlock system including this interlock circuit, this interlocking electricity Road performs FIFO function, and if the input to multiple circuit and the output from multiple circuit are at base Time identical in basis occurs, then offset described input and output to suppress simultaneous input signal.

The present invention also provides for a kind of interlock circuit and a kind of interlock system including this interlock circuit, this interlocking Circuit does not consider that temporary transient peak-to-peak signal provides output signal, and by inserting after one output signal of disabling Predetermined idle time reduces output signal error.

In some example embodiments, it is provided that a kind of interlocking including input delay unit and output suppression unit Circuit.The multiple input signal of input delay cell delay, it is provided that multiple delay input signals by multiple Delay input signal carries out logical operations to provide multiple exclusive input signal.Output suppression unit is based on multiple Exclusive input signal and multiple input signal provide multiple output signals that non-concurrent enables.

Input delay unit may include that delay cell, including postponing multiple input signal respectively and providing many Multiple input delay circuit of individual delay input signal；And exclusive ALU, including by many Individual delay input signal carries out exclusive logical operations respectively to provide the multiple exclusive of multiple exclusive input signal to patrol Collect computing circuit.

The the first exclusive logical operation circuit included at multiple exclusive logical operation circuits can be by many The first delay input signal that individual delay input signal includes and prolonging in addition to the first delay input signal Late the complementary signal of input signal carries out logical AND operation provides and includes in multiple exclusive input signals First exclusive input signal.

Multiple input delay circuit can include the first input delay circuit, and the first input delay circuit can To include the first transistor and transistor seconds, the first resistor and the second resistor and capacitor.The One transistor may include that grid, receives the first input signal included in multiple input signals；And The first terminal, receives supply voltage.First resistor can be connected to the of primary nodal point and the first transistor Between two-terminal.Transistor seconds may include that grid, receives the first input signal；The first terminal, even Receive ground voltage；And second terminal, it is connected to primary nodal point.Second resistor can be connected to first Between node and secondary nodal point.Capacitor can be connected between ground voltage and secondary nodal point.Such as, multiple Delay input signal can include the first delay input signal, and the first delay input signal can be by second Node provides.When the first input signal changes to logic state " high " from logic state " low ", the first delay is defeated Enter signal and can be delayed by the predetermined input delay time, and when the first input signal from logic state " high " to logic When state " low " changes, the first delay input signal can be delayed by predetermined idle time.Scheduled delay can To include predetermined input delay time and predetermined idle time.

When can determine predetermined input delay time and predetermined zero load based on the first resistor and the second resistor Between.Such as, predetermined idle time can be longer than the predetermined input delay time.

Output suppression unit can include that multiple output suppression circuit, each output suppression circuit include arranging electricity Road, reset circuit and output latch circuit.Arranging circuit can be by based in multiple exclusive input signal Including the first exclusive input signal, the first delay input signal included at multiple delay input signals and Second complementary input signal corresponding with the complementary signal of the second input signal included in multiple input signals Carrying out logical AND operation provides first to arrange signal.Reset circuit can by the second output signal and First complementary input signal corresponding with the complementary signal of the first input signal carries out OR logical operations to be provided First reset signal.Output latch circuit can arrange signal based on first and the first reset signal provides One output signal.

Output latch circuit can arrange signal in response to first and enable the first output signal, and in response to One reset signal and disable the first output signal.

In some example embodiments, it is provided that a kind of interlock circuit, this interlock circuit includes: delay cell, Receive the first input signal and the second input signal, the first input signal and the second input signal are postponed predetermined Time delay also provides the first delay input signal and the second delay input signal；Exclusive ALU, First row is provided by the first delay input signal and the second delay input signal are carried out exclusive logical operations His input signal and the second exclusive input signal；Noise removing unit, based on the first reset signal and the second weight Confidence number and the first delay input signal and the second delay input signal provide the first noise suppression signal and Second noise suppression signal；Unit is set, based on the first noise suppression signal, the first exclusive input signal and Second input signal provides first to arrange signal, and based on the second noise suppression signal, the second exclusive input Signal and the first input signal provide second to arrange signal；Reset cell, based on the first input signal and Two output signals provide the first reset signal, and provide based on the second input signal and the first output signal Second reset signal；And output latch unit, signal is set based on first and the first reset signal provides First output signal, and signal is set based on second and the second reset signal provides the second output signal.

Noise removing unit may include that the first noise remove latch cicuit, postpones input letter in response to first Number and enable the first noise suppression signal, and disable the first noise suppression signal in response to the first reset signal； And the second noise remove latch cicuit, the second noise suppressed letter is enabled in response to the second delay input signal Number, and disable the second noise suppression signal in response to the second reset signal.

Unit is set and can include that first arranges circuit and second and arrange circuit.

First arranges circuit can be by the first noise suppression signal, the first exclusive input signal and with second The second complementary input signal that the complementary signal of input signal is corresponding carries out logical AND operation provides first to set Confidence number, and second arrange circuit can by the second noise suppression signal, the second exclusive input signal and First complementary input signal corresponding with the complementary signal of the first input signal carries out logical AND operation to be provided Second arranges signal.

Reset cell can include the first reset circuit and the second reset circuit.First reset circuit can pass through Second output signal and first complementary input signal corresponding with the complementary signal of the first input signal are carried out OR logical operations provides the first reset signal, and the second reset circuit can by the first output signal and Second complementary input signal corresponding with the complementary signal of the second input signal carries out OR logical operations to be provided Second reset signal.

Output latch unit can include the first output latch circuit and the second output latch circuit, and described Each output latch circuit in first output latch circuit and the second output latch circuit can be reception One arranges signal and second arranges signal and receives the first reset signal and the second reset signal as arranging signal Replacement/latch cicuit is set as reset signal.Thus, the first output latch circuit can be in response to first Signal is set and enables the first output signal, and disable the first output signal in response to the first reset signal, And the second output latch circuit can arrange signal in response to second and enable the second output signal, and in response to Second reset signal and disable the second output signal.

First output latch circuit can maintain when first arranges signal and the first reset signal is the most disabled The original state of one output signal, and the second output latch circuit can arrange signal and second second and reset The original state of the second output signal is maintained when signal is the most disabled.

In some example embodiments, it is provided that a kind of interlock system including interlock circuit and lead-out terminal.Mutually Lock circuit receive the first input signal and the second input signal the first output signal of providing non-concurrent to enable and Second output signal.Lead-out terminal provides system to export in response to the first output signal and the second output signal Signal.Interlock circuit includes input delay unit and output suppression unit.Input delay unit inputs first Signal and the second input signal postpone scheduled delay, it is provided that the first delay input signal and second postpones defeated Enter signal, and carry by the first delay input signal and the second delay input signal are carried out logical operations For the first exclusive input signal and the second exclusive input signal.Output suppression unit is based on the first exclusive input letter Number and the second exclusive input signal, the first input signal and the second input signal and the first delay input signal The first output signal and the second output signal is enabled with the second delay input signal, and based on the first input letter Number and the second input signal and the first output signal and the second output signal disable the first output signal and Two output signals.

Lead-out terminal may include that the first output transistor, including receiving the grid of the first output signal and connecing Receive the first terminal of high supply voltage；And second output transistor, including the grid receiving the second output signal Pole, it is connected to the first terminal of the second terminal of the first output transistor and is connected to the second of ground voltage Terminal.Can be by the first end of the second terminal of the first output transistor, namely the second output transistor Son provides system output signal.

Lead-out terminal can include RS latch and power output unit.RS latch can be in response to first Output signal and enable power input signal, and disable power input signal in response to the second output signal. Power output unit can provide system output signal in response to power input signal.Such as, power output Unit may include that the first output transistor, including receiving the grid of power input signal and being connected to first The first terminal of high supply voltage；And second output transistor, including receive power output signal grid, It is connected to the first terminal of the second terminal of the first output transistor and is connected to the of the second high supply voltage Two-terminal.System output signal can be provided from the second terminal of the first output transistor.

Interlock system can also include: the first input signal signal generating unit, including being connected in series in the first high confession The 3rd resistor between piezoelectric voltage and ground voltage and the 3rd output transistor, and in response to the first pulse Signal and provide the first input signal to the terminal between the 3rd resistor and the 3rd output transistor；And Second input signal signal generating unit, including be connected in series between the first high supply voltage and ground voltage Four resistors and the 4th output transistor, and in response to the second pulse signal at the 4th resistor and Terminal between four output transistors provides the second input signal.

Accompanying drawing explanation

According to combine that accompanying drawing carries out described in detail below can be more clearly understood that illustrative, non-limiting Example embodiment:

Fig. 1 is the block diagram illustrating the interlock circuit according to some example embodiment；

Fig. 2 is the block diagram of the input delay unit of the interlock circuit illustrating Fig. 1；

Fig. 3 is the figure illustrating the input delay unit according to some example embodiment；

Fig. 4 is the circuit diagram illustrating the input delay circuit according to some example embodiment；

Fig. 5 is the block diagram illustrating the output suppression unit according to some example embodiment；

Fig. 6 is the figure illustrating the first output suppression circuit according to some example embodiment；

Fig. 7 to Figure 10 is the sequential chart of the operation of the interlock circuit for explanatory diagram 1 to Fig. 6；

Figure 11 is the figure illustrating the interlock circuit according to some example embodiment；

Figure 12 is the figure illustrating the interlock system including interlock circuit according to some example embodiment；

Figure 13 is the figure illustrating the interlock system including interlock circuit according to some example embodiment.

Detailed description of the invention

Disclosed herein is detailed description property example embodiment.But, concrete structure disclosed herein and function Details is only for describing example embodiment.But, the present invention can embody with many alternative forms and should not When being understood to be limited to example embodiment set forth herein.

Thus, although example embodiment can have various amendment and alternative form, but in the accompanying drawings by showing The mode of example illustrates and is described in detail herein embodiment.It is, however, to be understood that be not intended to make example real Execute example and be limited to particular forms disclosed, but just the opposite, covering is fallen into the present invention's by example embodiment In the range of all modifications, equivalent and replacement scheme.

It will be appreciated that, although terms first, second etc. can here be used for describing various element, but this A little elements should be not limited by these terms.These terms are only used for distinguishing an element and another element.Example As, the first element is properly termed as the second element, similarly, the second element is properly termed as the first element, and not Depart from the scope of example embodiment.

It is understood that when element or layer are referred to as " being formed on another element or layer ", it can be direct or indirect Be formed on another element or layer.It is to say, intermediary element or layer such as can be there is.On the contrary, When element or layer are referred to as " being formed directly on another element ", there is not intermediary element or layer.Should be with class Like mode explain other word for describing relation between element or layer (such as, " and ... between " with " straight Ground connection exists ... between ", " adjacent " and " the most adjacent " etc.).

Term used herein is not intended to only for describing specific embodiment limit example embodiment.Such as this In used, singulative "/a kind of ", " should/described " etc. be intended to also include plural form, unless context Expressly otherwise indicated.It is also understood that, when word " includes " being used herein specify exist stated feature, Entirety, step, operation, element and/or parts, but it is not excluded that existence or add one or more its His feature, entirety, step, operation, element, parts and/or a combination thereof.

Unless otherwise defined, all terms used herein (including technical term and scientific terminology) have with The implication that implication that the ordinary technical staff in the technical field of the invention is commonly understood by is identical.Can also manage Solve, such as should be understood to have to them at relevant neck at term as the term defined in common dictionary Implication that implication under the background in territory is consistent and can not explain with idealization or the most formal idea, Unless the most so limited.

It is described more fully with the present invention referring now to the accompanying drawing of the exemplary embodiment that there is shown the present invention. In the accompanying drawings, identical element is represented by identical label and will not provide its repeat specification.

Fig. 1 is the block diagram illustrating the interlock circuit 10 according to some example embodiment.

With reference to Fig. 1, interlock circuit 10 can include input delay unit 100 and output suppression unit 200.

Input delay unit 100 receives input signal IN including multiple input signal, postpones this input signal IN also provides include the exclusive of multiple exclusive input signal by the input signal postponed carries out logical operations Input signal XIN.The input signal postponed can correspond to multiple delay input signal.Such as, when passing through The first delay input signal and the second delay input signal to including at multiple delay input signals are patrolled When volume computing provides the first exclusive input signal and the second exclusive input signal, can be by postponing first The complementary signal of input signal and the second delay input signal carries out logical AND operation provides first exclusive defeated Enter signal, and can be by the complementary signal of the second delay input signal and the first delay input signal is entered Row logical AND operation provides the second exclusive input signal.

Output suppression unit 200 based on exclusive input signal XIN, input signal IN and includes that multiple delay is defeated The delay input signal DIN entering signal provides output signal OUT including multiple output signal.In interlocking In circuit 10, among multiple output signals of same time point, only one of which output signal can be activated also And can correspond to logic state " high ".It is to say, in order to prevent from enabling multiple output signal simultaneously, interlocking Circuit 10 can be by carrying out exclusive input signal XIN, input signal IN and delay input signal DIN Logical operations suppresses to enable multiple output signal simultaneously.

For example, it is possible to select to be enabled one among multiple output signals by FIFO (FIFO) mode Individual output signal.Thus, if there being the output signal first enabled, enable other output signal even if then providing Condition, other output signal is also maintained at disabled status until the output signal first enabled is disabled.Hereafter The operation of suppression output signal OUT will be described.

Fig. 2 is the input delay unit 100 of the interlock circuit 10 illustrating the Fig. 1 according to some example embodiment Block diagram.

With reference to Fig. 2, input delay unit 100 may include that delay cell 110, including multiple input delays Circuit；And exclusive ALU 120, including multiple exclusive logical operation circuits.

It is many that delay cell 110 reception is properly termed as the first to the n-th input signal IN1, IN2 ... and INn Individual input signal, by multiple input signals IN1, IN2 ... and INn delay scheduled time, and provides permissible It is referred to as multiple delay input signals of the first to the n-th delay input signal DIN1, DIN2 ... and DINn. Such as, the first input delay circuit included at multiple input delay circuit can receive the first input signal IN1, by the first input signal IN1 delay scheduled time, and provides the first delay input signal DIN1.

Such as, obtain multiple delay by multiple input signals IN1 of delay, IN2 ... and INn and input letter The scheduled delay of number DIN1, DIN2 ... and DINn institute foundation can according to multiple input signals IN1, The transition stage of IN2 ... and INn and change.Such as, in the first input signal IN1 from logic state " low " On the rising edge that logic state " high " changes, the first delay input signal DIN1 corresponds to The signal that one input signal IN1 postpones the predetermined input delay time and obtains.On the contrary, at the first input letter Number IN1 from logic state " high " to the trailing edge that logic state " low " changes, the first delay input signal The signal that DIN1 corresponds to that the first input signal IN1 is postponed predetermined idle time and obtains.In advance Determine the input delay time and predetermined idle time can be different.Such as, the predetermined input delay time is permissible Shorter than predetermined idle time.Predetermined input delay time and predetermined idle time can be according to each input delays The configuration of circuit and change.

Exclusive ALU 120 receives multiple delay input signal DIN1, DIN2 ... and DINn, And by carry out respectively exclusive logical operations provide be properly termed as the first to the n-th exclusive input signal XIN1, XIN2 ... and the multiple exclusive input signal of XINn.Can by multiple delay input signal DIN1, DIN2 ... and DINn are applied to corresponding exclusive logical operation circuit to provide multiple corresponding exclusive inputs Signal XIN1, XIN2 ... and XINn.Such as, first included at multiple exclusive logical operation circuits Exclusive logical operation circuit receives the first delay input signal DIN1, and to except the first delay input signal Delay input signal DIN2 ... outside DIN1 and DINn carries out exclusive logical operations.Here, exclusive patrol Collect computing to refer to corresponding delay input signal and the delay in addition to corresponding delay input signal are inputted The logical AND operation that the complementary signal of signal is carried out.By to the first delay input signal DIN1 and other The complementary signal of delay input signal DIN2 ... and DINn carries out logical AND operation to provide first row His input signal XIN1.Thus, when enable the first delay input signal DIN1 and disable other postpone input When signal DIN2 ... and DINn, enable the first exclusive input signal XIN1.

Fig. 3 is the figure illustrating the input delay unit 100a according to some example embodiment.

Delay cell 110a and exclusive ALU can be included with reference to Fig. 3, input delay unit 100a 120a.Delay cell 110a and exclusive ALU 120a are respectively the delay cell shown in Fig. 2 110 and the example of exclusive ALU 120.

Delay cell 110a can include the first input delay circuit 111 and the second input delay circuit 113, Exclusive ALU 120a can include the first exclusive ALU 121 and the second exclusive logic fortune Calculate unit 123.

First input delay circuit 111 receives the first input signal IN1, the first input signal IN1 is postponed pre- Determine time delay, and the first delay input signal DIN1 is provided.Second input delay circuit 113 receives second Input signal IN2, postpones the second input signal IN2 scheduled delay, and provides the second delay input letter Number DIN2.Such as, scheduled delay can include predetermined input delay time and predetermined idle time.Cause And, in the first input signal IN1 and the second input signal IN2 from logic state " low " to logic state " high " On the rising edge changed, the first delay input signal DIN1 and the second delay input signal DIN2 can be logical Cross the letter that the first input signal IN1 and the second input signal IN2 are postponed the predetermined input delay time and obtain Number, and in the first input signal IN1 and the second input signal IN2 from logic state " high " to logic state " low " On the trailing edge changed, the first delay input signal DIN1 and the second delay input signal DIN2 can be logical Cross the signal that the first input signal IN1 and the second input signal IN2 are postponed predetermined idle time and obtain.

First exclusive logical operation circuit 121 can include the first AND-gate 1211 and the first phase inverter 1213. First phase inverter 1213 is by anti-phase for the second delay input signal DIN2, and provides to the first AND-gate 1211 Complementary delay input signal/the DIN2 of second corresponding with the complementary signal of the second delay input signal DIN2.The One AND-gate 1211 is by delay input signal/DIN2 complementary to the first delay input signal DIN1 and second Carry out logical AND operation and the first exclusive input signal XIN1 is provided.

Second exclusive logical operation circuit 123 can include the second AND-gate 1231 and the second phase inverter 1233. Second phase inverter 1233 is by anti-phase for the first delay input signal DIN1, and provides to the second AND-gate 1231 Complementary delay input signal/the DIN1 of first corresponding with the complementary signal of the first delay input signal DIN1.The Two AND-gate 1231 are by delay input signal/DIN1 complementary to the second delay input signal DIN2 and first Carry out logical AND operation and the second exclusive input signal XIN2 is provided.

As described with reference to Figure 2, on the trailing edge of the first input signal IN1 and the second input signal IN2, First delay input signal DIN1 and the second delay input signal DIN2 can be delayed by predetermined idle time, It is then provided with.Pre-according to determine in the first input delay circuit 111 and the second input delay circuit 113 Determining idle time, the first exclusive input signal XIN1 and the second exclusive input signal XIN2 are prolonged in response to first Late input signal DIN1 and the trailing edge of the second delay input signal DIN2 and change.Predetermined idle time can Change with the configuration according to each input delay circuit.

Fig. 4 is the circuit diagram illustrating the input delay circuit 111a according to some example embodiment.

Input delay circuit 111a is the example of the first input delay circuit 111 of Fig. 3.At interlock circuit 10 In, each input delay circuit in multiple input delay circuit can have and substantially phase shown in Fig. 4 Same configuration.

With reference to Fig. 4, input delay circuit 111a can include the first transistor TR1, transistor seconds TR2, First resistor R1, the second resistor R2 and capacitor C1.

The first transistor TR1 may include that grid, receives the first input signal IN1；The first terminal, connects Receive the voltage of supply voltage VDD；And second terminal, it is connected to the first resistor R1.Such as, first Transistor TR1 can be P-type mos (PMOS) transistor, and the first terminal can be Source terminal, and the second terminal can be drain terminal.

Transistor seconds TR2 may include that grid, receives the first input signal IN1；The first terminal, even Receive ground voltage GND；And second terminal, it is connected to primary nodal point ND1.Such as, transistor seconds TR2 can be N-type MOS (NMOS) transistor, and the first terminal can be source terminal, and the second end Son can be drain terminal.

First resistor R1 may be coupled to second terminal of primary nodal point ND1 and the first transistor TR1, And the second resistor R2 can be connected between primary nodal point ND1 and secondary nodal point ND2.

Capacitor C1 may be coupled to secondary nodal point ND2 and the first terminal of transistor seconds TR2.

The first transistor TR1 and transistor seconds TR2 can be made complementally according to the first input signal IN1 On or off.Although it is desirable to provide substantially the same with the first input signal IN1 to secondary nodal point ND2 Signal, but can be based on the first resistor R1 and the second resistor R2 and the first input signal IN1 is postponed Scheduled delay also provides the input signal postponed to secondary nodal point ND2.

Such as, when the first input signal IN1 is corresponding to logic state " high ", transistor seconds TR2 turns on And the first transistor TR1 cut-off, therefore the voltage of secondary nodal point ND2 can correspond to ground voltage GND Voltage.It addition, when the first input signal IN1 is corresponding to logic state " low ", transistor seconds TR2 Ending and the first transistor TR1 conducting, therefore the voltage of secondary nodal point ND2 can correspond to supply voltage The voltage of VDD.But, when by first input signal IN1 postpone scheduled delay time can change with to Signal corresponding to voltage that secondary nodal point ND2 provides.Such as, the 3rd phase inverter 1111 may be electrically connected to Two node ND2.As it has been described above, when the first transistor TR1 is PMOS transistor and transistor seconds TR2 During for nmos pass transistor, owing to the output signal corresponding with the voltage of secondary nodal point ND2 can correspond to The complementary signal of one input signal IN1, so the 3rd phase inverter 1111 can be by the voltage of secondary nodal point ND2 Anti-phase and the first delay input signal DIN1 is provided.

The predetermined input delay time of input delay circuit 111a can be calculated as illustrated in equation 1 and make a reservation for Idle time.

[equation 1]

$\frac{R_1}{R_1+R_2}=\frac{t_{\mathrm{input\; filter\; time}}}{t_{\mathrm{dead\; time}}}$

Wherein t_{dead time}For predetermined idle time, and t_{input filter time}For the predetermined input delay time.

The predetermined input delay time is properly termed as the predetermined input filter time.Can be based on the first resistor R1 Predetermined input delay time and predetermined idle time is determined with the second resistor R2.Such as, due to for multiple The predetermined input delay time that input delay circuit is arranged can be substantially the same with predetermined idle time, so The configuration of input delay circuit can be substantially the same.

Such as, the value of the first resistor R1 can be more than the value of the second resistor R2.It addition, predetermined zero load Time can be differently configured from the predetermined input delay time, and the input delay circuit 111a of Fig. 4 can be asymmetric Input delay circuit.

Fig. 5 is the block diagram illustrating the output suppression unit 200a according to some example embodiment.

The example of the output suppression unit 200 of the interlock circuit 10 that output suppression unit 200a is Fig. 1 of Fig. 5, But example embodiment is not limited to this.That is, although output suppression circuit 200a includes the in Figure 5 One output suppression circuit 210 and the second output suppression circuit 220, but the present embodiment is not limited to this, and defeated Go out to suppress unit 200 can include multiple output suppression circuit.

First output suppression circuit 210 can include that first arranges circuit the 211, first reset circuit 213 and the One output latch circuit 215.

First arranges circuit 211 by the first exclusive input signal XIN1, the first delay input signal DIN1 Carrying out logical AND operation with the second complementary input signal/IN2 provides first to arrange signal SET1.

First reset circuit 213 is by entering the first complementary input signal/IN1 and the second output signal OUT2 Row logic OR operation provides the first reset signal RST1.

First output latch circuit 215 can arrange signal SET1 in response to first and enable the first output signal OUT1 also disables the first output signal OUT1 in response to the first reset signal RST1.Such as, first is defeated Going out latch cicuit 215 can be to reset/arrange (RS) latch cicuit.RS latch cicuit includes two NOR Door, each NOR-gate receives first and arranges signal SET1 and the first reset signal RST1.Furthermore it is possible to The output signal input signal as another NOR-gate of one NOR-gate is provided.

Second output suppression circuit 220 can include that second arranges circuit the 221, second reset circuit 223 and the Two output latch circuits 225.

Second arranges circuit 221 by the second exclusive input signal XIN2, the second delay input signal DIN2 Carrying out logic OR operation with the first complementary input signal/IN1 provides second to arrange signal SET2.

Second reset circuit 223 is by entering the first output signal OUT1 and the second complementary input signal/IN2 Row logic OR operation provides the second reset signal RST2.

Second output latch circuit 225 arranges signal SET2 in response to second and enables the second output signal OUT2 and disable the second output signal OUT2 in response to the second reset signal RST2.

Fig. 6 is the figure illustrating the first output suppression circuit 210a according to embodiments of the present invention.The first of Fig. 6 Output suppression circuit 210a is the example of the first output suppression circuit 210 of Fig. 5, but the present embodiment does not limits In this.

Can include that first arranges circuit 211a, the first replacement with reference to Fig. 6, the first output suppression circuit 210a Circuit 213a and the first output latch circuit 215a.

First arranges circuit 211a can include based on the first exclusive input signal XIN1, the first delay input letter Number DIN1 and the second complementary input signal/IN2 provides the first the 3rd AND-gate arranging signal SET1 2111.If the first exclusive input signal XIN1, the first delay input signal DIN1 and the second Complementary input structure Signal/IN2 both corresponds to logic state " high ", then first arrange signal SET1 and be activated and correspond to logic shape State " high ".If it is to say, enabled in the state of disabling the second delay input signal DIN2 by by the One input signal IN1 postpone the predetermined input delay time and the first delay input signal DIN1 of obtaining and do not open By the second input signal IN2, then first circuit 211a is set enables first signal SET1 is set to enable One output signal OUT1.Further, since in response to during by the first input signal IN1 is postponed predetermined zero load Between and the trailing edge of the second delay input signal DIN2 that obtains carry based on the first exclusive input signal XIN1 For first, signal SET1 is set, so enabling the first output signal OUT1 after predetermined idle time passs, Thus minimize the interference between output signal.

First reset circuit 213a can include based on the first complementary input signal/IN1 and the second output signal OUT2 provides an OR door 2131 of the first reset signal RST1.If the first complementary input signal/IN1 With any one in the second output signal OUT2 corresponding to logic state " high ", then the first reset signal RST1 It is activated and corresponds to logic state " high ".If it is to say, enable the second output signal OUT2, then One reset circuit 213a initialize the first output latch circuit 215a and disable the first output signal OUT1 with Prevent from enabling the first output signal OUT1 and the second output signal OUT2 simultaneously.If disabling the first input letter Number IN1, then the first reset circuit 213a can disable the first output signal OUT1.

First output latch circuit 215a can include the first NOR-gate 2151 and the second NOR-gate 2153. First NOR-gate 2151 is by arranging signal SET1 to first and the first output signal OUT1 carries out logic NOR operation provides first complementary output signal corresponding with the complementary signal of the first output signal OUT1 /OUT1.Second NOR-gate 2153 is by the first reset signal RST1 and the first complementary output signal/OUT1 Carry out logic NOR operation and export the first output signal OUT1.First output latch circuit 215a can wrap Include RS latch cicuit.If first arranges signal SET1 is activated and corresponds to logic state " high ", then open By the first output signal OUT1.If the first reset signal RST1 is activated and corresponds to logic state " high ", Then initialize and disable the first output signal OUT1.In RS latch cicuit, R represent replacement and S represents Arrange.If enabling reset signal, then initialize and disable output signal, and if enable and signal be set, Then arrange and enable output signal.It is said that in general, reset signal and signal is set can have complementary relationship. But, when reset signal and arrange signal the most disabled time, output signal is maintained at original state.It addition, Reset signal can be prevented according to the type of the logic element included at RS latch cicuit and signal is set All it is activated or all output signals are the most disabled.

Fig. 7 to Figure 10 is the sequential of the operation for the interlock circuit 10 referring to figs. 1 to Fig. 6 description is described Figure.Fig. 7 to Figure 10 illustrates the first input signal IN1, the second input signal IN2, the first delay input letter Number DIN1, the second delay input signal DIN2, the first exclusive input signal XIN1, the second exclusive input letter Number XIN2, first arrange signal SET1, second arrange signal SET2, the first output signal OUT1, Two output signals OUT2, the first reset signal RST1 and the voltage level of the second reset signal RST2.Often The voltage level of individual signal can correspond to logic state " high " or logic state " low ".Such as, if enabling spy Determine signal, then this signal specific can correspond to logic state " high ".But, the present embodiment is not limited to this, should Signal specific is also can correspond to logic state " low ".If following description can be based on enabling signal specific, this spy Determine signal to carry out corresponding to logic state " high " this hypothesis.

Fig. 7 is for explanation interlock circuit 10 when enabling multiple input signal within the predetermined input delay time The sequential chart of operation.

With reference to Fig. 7, at time t1, enable the first input signal IN1 and disable the first reset signal RST1.

At time t2, enable the second input signal IN2 and disable the second reset signal RST2.Due to from time Between time t2 before the passage of predetermined input delay time that rises of t1 enable the second input signal IN2, so the Two input signals IN2 are prior to enabling the time of the first delay input signal DIN1.Therefore, it is difficult to determine and enable Between time and the time enabling the second input signal IN2 of the first input signal IN1 which time earlier or More late.Time t6 within the predetermined input delay time from the time t5 disabling the first input signal IN1 Disable the second input signal IN2.First input signal IN1 and the second input signal IN2 are at predetermined input delay It is activated in time and disables, therefore can be the substantially the same signal of phase place.If multiple input signals Having substantially the same phase place as mentioned above, the most the plurality of input signal is referred to as in-phase signal.Due to many Individual output signal cannot be enabled because of the characteristic of interlock circuit 10 simultaneously, thus should ignore all this The in-phase signal of sample.The interlock circuit of Fig. 7 can be cancelled in-phase signal and not use add ons.

At time t3, due to input delay circuit 111, first input signal IN1 is postponed predetermined input and prolong Time late, and enable the first delay input signal DIN1.The predetermined input delay time in Fig. 7 can be right The time (t3-t1) that Ying Yu obtains by time t3 is deducted time t1.

The obtained by the first input signal IN1 is postponed the predetermined input delay time is enabled at time t3 One delay input signal DIN1, and the first exclusive logical operation circuit 121 by postponing input letter to first Number DIN1 and the second delay obtained by the second input signal IN2 is postponed the predetermined input delay time are defeated Enter signal DIN2 to carry out logical AND operation the first exclusive input signal XIN1 is provided.Although it is desirable to From time t3 to the period of time t4 enables the first exclusive input signal XIN1, but the first exclusive input Signal XIN1 is being not up to the voltage the most corresponding with logic state " high " from time t3 during the period of time t4 Level, thus cannot be activated and be maintained at disabled status.Owing to the first exclusive input signal XIN1 is maintained at Disabled status, so disabling first arranges signal SET1 and not enabled the first output signal OUT1.

The first input signal IN1 is disabled and within the predetermined input delay time from time t5 at time t5 Time t6 disable the second input signal IN2.

Time t7 after the predetermined idle time from the time t5 disabling the first input signal IN1 passs Disable the first delay input signal DIN1, and pre-from the time t6 disabling the second input signal IN2 Time t8 after determining passage idle time disables the second delay input signal DIN2.Second exclusive logical operations Circuit 123 is by the second delay input signal DIN2 and the complementary signal of the first delay input signal DIN1 Carry out logical AND operation and the second exclusive input signal XIN2 is provided.It is similar to the first exclusive input signal XIN1, the second exclusive input signal XIN2 is being not up to logic shape from time t7 during the period of time t8 State " high ", is thus maintained at disabled status.Thus, disabling second arranges signal SET2 and to disable second defeated Go out signal OUT2.

In a word, when enabling or disable the first input signal IN1 and second defeated within the predetermined input delay time When entering signal IN2, even if enabling the first input signal IN1 and the second input signal IN2, the first output signal OUT1 and the second output signal OUT2 are not activated yet and are maintained at disabled status.Interlock circuit 10 is permissible Operate in the way of substantially the same with aforesaid way for multiple input signals.Carry out FIFO operation being used for Make to enable input signal in response to first and enable in the interlock circuit of output signal, owing to being difficult to determine Which input signal between the multiple input signals enabled in the predetermined input delay time much earlier or later, institute To ignore the plurality of input signal and to disable output signal.

Fig. 8 is for the interlock circuit 10 not enabling output signal when temporarily enabling input signal for explanation The sequential chart of operation.

With reference to Fig. 8, enable at time t3 and during the period of time t5, temporarily enabling second from time t3 Input signal IN2.For example, it may be possible to it is defeated temporarily to enable second due to signal disturbing such as electromagnetic interference (EMI) Enter signal IN2.

At time t1, enable the first input signal IN1 and disable the first reset signal RST1.From time t1 Time t2 after the passage predetermined input time risen enables the first delay input signal DIN1.Prolong based on first Input signal DIN1 and the second delay input signal DIN2 enable the first exclusive input signal at time t2 late XIN1, and enable first signal SET1 and the first output signal OUT1 are set.In response to the second input signal IN2 and enable the second reset signal RST2.

At time t3, enable the second input signal IN2 and disable first and signal SET1 is set.But, although Disabling first arranges signal SET1, but based on the second output signal applied to the first reset circuit 213 OUT2 and the first input signal IN1 and the first reset signal RST1 is maintained at disabled status.Thus, the One output latch circuit 215 can provide the first output signal OUT1 enabled.

Enable at time t4 and postpone predetermined input delay by the second input signal IN2 that will enable at time t3 Time and the second delay input signal DIN2 of obtaining.In response to the second delay input signal DIN2 enabled And disable the first exclusive input signal XIN1.But, due to based on the first input letter being maintained at the state of enabling Second exclusive input signal XIN2 is maintained at disabled status by number IN1, so disabling second arranges signal SET2 With the second output signal OUT2.Further, since enable the first output signal OUT1, so second resets letter Number RST2 is maintained at disabled status.Thus, the first output signal OUT1 and the second output signal OUT2 Do not affected by the second input signal IN2 enabled.

Although disable the second input signal IN2 at time t5, but owing to just prohibiting after predetermined idle time With the second delay input signal DIN2, so the second delay input signal DIN2 is maintained at the state of enabling.

From time t5, the period to time t6 can correspond to predetermined idle time.For example, it is possible at input letter When logic state " high " changes to logic state " low ", number illustrate that (namely can illustrate on a falling edge) is pre- Determine idle time.Disable the second delay input signal DIN2, therefore can enable the first exclusive input signal XIN1 and first can be enabled signal SET1 is set.Shape is enabled owing to the first output signal OUT1 is in State, is affected so the first output signal OUT1 is not arranged signal SET1 by first enabled.

Time t6 after predetermined idle time passs, enables the first exclusive input signal XIN1, and according to The first exclusive input signal XIN1 enabled enables first and arranges signal SET1.

At time t7, disable the first input signal IN1, and the first delay input signal DIN1 is maintained at and opens By state, because after the predetermined idle time from the time t7 disabling the first input signal IN1 passs Time disable the first delay input signal DIN1.Is enabled in response to the first input signal IN1 enabled One reset signal RST1.Owing to first arranges signal SET1 and be still within enabling state, so disabling first Output signal OUT1.

Time t9 after the predetermined idle time from time t7 passs, disables the first delay input signal DIN1, and disable the first exclusive input signal XIN1 in response to the first delay input signal DIN1 of disabling. Time t8 be from time t7 be currently entered time delay passage after time.Postpone in response to first Input signal DIN1 and disable first and signal SET1 be set.

In a word, if the most enabled first input signal IN1, then could be by the first output signal OUT1 and Two output signals OUT2 are maintained at original state and are not affected by the second input signal IN2 enabled.Thus, Interlock circuit 10 can carry out reliable operation and not affected by the temporary transient change inputted.

Fig. 9 is for by inserting the interlock circuit 10 reducing output error predetermined idle time for explanation The sequential chart of operation, described output error may occur when output signal changes simultaneously.

With reference to Fig. 9, at time t1, enable the first input signal IN1, and in response to the first input letter enabled Number IN1 and disable the first reset signal RST1.

Enable the first input signal IN1 and be currently entered time delay passage after time t2, enable First delay input signal DIN1.At time t2, owing to the second input signal IN2 is in disabled status, institute To enable the first exclusive input signal XIN1, enable first and signal SET1 is set and enables the first output signal OUT1。

At time t3, enable the second input signal IN2 and disable first signal SET1 is set.

Time t4 after the predetermined input delay time from time t3 passs, enables the second delay input Signal DIN2 and disable the first exclusive input signal XIN1.But, owing to enabling the first input signal IN1, So the first delay input signal DIN1 is maintained at the state of enabling, and therefore the second exclusive input signal XIN2 It is maintained at disabled status.Although disabling first arranges signal SET1, but due to the first output signal OUT1 It is in the state of enabling, so the second reset signal RST2 is maintained at the state of enabling and disabling the second output signal OUT2.Owing to the first input signal IN1 is maintained at the state of enabling, so disabling the first reset signal RST1. Result is to reset owing to disabling arranges signal SET1 and first to the first of the first output latch circuit 215 input Signal RST1, so the first output signal OUT1 is maintained at original state.

At time t5, disabling the first input signal IN1, enable the first reset signal RST1, disabling first is defeated Go out signal OUT1 and disable the second reset signal RST2.

Time t6 after the predetermined idle time from the time t5 disabling the first input signal IN1 passs, Disable the first delay input signal DIN1 and enable the second exclusive input signal XIN2.Exclusive in response to second Input signal XIN2 and enable second and signal SET2 be set, and enable the second output signal OUT2.Cause And, exist and disabling the time t5 of the first output signal OUT1 and enabling the second output signal OUT2 The time difference that predetermined idle time between time t6 is corresponding.

In a word, although interlock circuit 10 opens in response to first among the first input signal and the second input signal Enable output signal by input signal, but interlock circuit 10 can be by from one output signal of disabling Time to the period of the time enabling another output signal in insert prevent predetermined idle time may with The fault occurred during Shi Qiyong output signal.

Figure 10 is for explanation interlock circuit 10 when complementally enabling and disable multiple input signal simultaneously The sequential chart of operation.

With reference to Figure 10, at time t1, enable the first input signal IN1, and defeated in response to first enabled Enter signal and disable the first reset signal RST1.

Time t2 after the predetermined input delay time from time t1 passs, enables the first delay input Signal DIN1 and enable the first exclusive input signal XIN1.Based on the exclusive input signal of first enabled XIN1 and the first delay input signal DIN1 enables first and arranges signal SET1.In response to first, letter is set Number SET1 and enable the first output signal OUT1.

At time t3, disable the first input signal IN1 and enable the second input signal IN2.It is to say, Time t3, the first input signal IN1 and the second input signal IN2 are transformed into that have can be in the output signal The complementary reflected.But, if the first output signal OUT1 and the second output signal OUT2 with First input signal IN1 and the identical mode of the second input signal IN2 change, then when by response to often Individual output signal and receive when the system that high voltage operates includes interlock circuit 10 and may generate wherein simultaneously Enable the lap of output signal, thus reduce the performance of system.

At time t3, disable first in response to the second input signal IN2 enabled signal SET1 is set.Separately Outward, disable the first input signal IN1, enable the first reset signal RST1, and disable the first output signal OUT1.The first output signal OUT1 based on disabling and the second input signal IN2 enabled disable second Reset signal RST2.

Time t4 after the predetermined input delay time from time t3 passs, enables the second delay input Signal DIN2, and disable the first exclusive input signal in response to the second delay input signal DIN2 enabled XIN1。

At time t5, in response to the first input signal IN1 disabled at time t3 predetermined idle time it Rear disabling the first delay input signal DIN1, and enable the second exclusive input signal XIN2.In response to opening The second exclusive input signal XIN2 and enable second and signal SET2 be set, and enable the second output letter Number OUT2.Thus, flow in the predetermined idle time from the time t3 disabling the first output signal OUT1 Time t5 after dying enables the second output signal OUT2.Thus, if at substantially the same time t3 Enable and disable the first input signal IN1 and the second input signal IN2 and therefore in the substantially the same time Enable and disable the first output signal OUT1 and the second output signal OUT2, then enable first in the identical time Output signal OUT1 and the second output signal OUT2, it is thus possible to owing to suddenly flowing through the high voltage of circuit and Occur that circuit damages or fault.The interlock circuit of Figure 10 can be by inserting predetermined sky between output signal The load time minimizes the fault of high voltage circuit.

Figure 11 is the figure illustrating interlock circuit 10a according to another embodiment of the present invention.

With reference to Figure 11, interlock circuit 10a can include delay cell 110b, exclusive ALU 120b, Noise removing unit 150, unit 230, reset cell 240 and output latch unit 250 are set.When with ginseng Examining interlock circuit 10 that Fig. 1 to Fig. 6 describes when comparing, the interlock circuit 10a of Figure 11 can also include noise Removal unit 150.

Delay cell 110b includes the first input delay circuit 111a and the second input delay circuit 113a, and And receive the first input signal IN1 and the second input signal IN2, the first input signal IN1 and second are inputted Signal IN2 postpones scheduled delay and provides the first delay input signal DIN1 and second to postpone input letter Number DIN2.

Exclusive ALU 120b includes the first logical operation circuit 121a and the second logical operation circuit 123a, and by the first delay input signal DIN1 and the second delay input signal DIN2 is carried out exclusive Logical operations provides the first exclusive input signal XIN1 and the second exclusive input signal XIN2.First logic Computing circuit 121a is by the first delay input signal DIN1 with as the second delay input signal DIN2 Second complementary delay input signal/DIN2 of complementary signal carry out logical AND operation and provide first exclusive Input signal XIN1.Second logical operation circuit 123a is by the second delay input signal DIN2 and conduct Complementary delay input signal/the DIN1 of the first of the complementary signal of the first delay input signal DIN1 carries out logic AND operation provides the second exclusive input signal XIN2.

Delay cell 110b of Figure 11 and the configuration of exclusive ALU 120b can be with Fig. 1 to Fig. 4 Configuration substantially the same.

Noise removing unit 150 can include the first noise remove latch units 151 and the second noise remove lock Deposit circuit 153.First noise remove latch cicuit 151 and the second noise remove latch cicuit 153 can have The configuration substantially the same with the configuration of RS latch cicuit, and the first delay input signal DIN1 and second Delay input signal DIN2 and the first reset signal RST1 and the second reset signal RST2 can correspond to Reset signal.

First noise remove latch cicuit 151 provides enabled in response to the first delay input signal DIN1 One noise suppression signal NDIN1, and provide disable in response to the first reset signal RST1 first to make an uproar Sound suppression signal NDIN1.

Similarly, the second noise remove latch cicuit 153 provides in response to the second delay input signal DIN2 The the second noise suppression signal NDIN2 enabled, and provide and disable in response to the second reset signal RST2 The second noise suppression signal NDIN2.

Unit 230 is set and can include that first arranges circuit 231 and second and arrange circuit 233.First arranges electricity Road 231 can be by the first noise suppression signal NDIN1, the first exclusive input signal XIN1 and Two complementary input signals/IN2 carries out logical AND operation provides the first AND-gate arranging signal SET1. Second to arrange circuit 233 can be by the second noise suppression signal NDIN2, the second exclusive input signal XIN2 and the first complementary input signal/IN1 carries out logical AND operation provides second to arrange signal SET2 AND-gate.

Except providing the first noise suppression signal NDIN1 and the second noise suppression signal NDIN2 rather than Outside one delay input signal DIN1 and the second delay input signal DIN2, include arranging unit 230 First circuit 231 and second is set the configuration of circuit 233 be set set with first shown in Fig. 5 and Fig. 6 The configuration that circuits 211 arranges circuit 213 with second is substantially the same.

It is said that in general, the first noise suppression signal NDIN1 and the second noise suppression signal NDIN2 can have Have and the first delay input signal DIN1 and the second waveform similar for delay input signal DIN2.But, by In initializing the first noise suppressed in response to the first reset signal RST1 and the second reset signal RST2 Signal NDIN1 and the second noise suppression signal NDIN2, so the first noise suppression signal NDIN1 and Two noise suppression signal NDIN2 can more steadily in response to input signal IN1 and the cataclysm of IN2, thus Noise robustness can be realized.

Due to reset cell 240 and the configuration of output latch unit 250 and operation and the configuration shown in Fig. 6 and Operate substantially the same, describe in detail so it will be omitted.

Figure 12 is the figure illustrating the interlock system 1200 including interlock circuit 10 according to embodiments of the present invention.

With reference to Figure 12, interlock system 1200 can include interlock circuit 10 and lead-out terminal 1210.

The example of interlock circuit 10 can include the interlock circuit described referring to figs. 1 to Figure 11.Interlock circuit 10 receive the first input signal IN1 and the second input signals IN2, and provide non-concurrent enables first defeated Go out signal OUT1 and the second output signal OUT2.First input signal IN1 can correspond to high voltage grid The high voltage input signal HIN that driver provides, and the second input signal IN2 can correspond to low electricity Low-voltage input signal LIN that pressure gate drivers provides.But, high voltage is relative word with low-voltage, And running voltage is not limited to this.

Lead-out terminal 1210 can include MOS transistor or igbt (IGBT).Defeated Go out that terminal 1210 can include being connected in series between high supply voltage HVCC and ground voltage GND One output transistor TRO1 and the second output transistor TRO2.Two of which transistor is connected in series in two Configuration between power rail is referred to as half-bridge configuration.First output transistor TRO1 can correspond to high side gate Driver, and the second output transistor TRO2 can correspond to lowside gate driver.First output crystal Pipe TRO1 can correspond to high voltage gate drivers, and the second output transistor TRO2 can correspond to Low voltage gate driver.

The node being connected to by the first output transistor TRO1 and the second output transistor TRO2 provides the One system output signal SOUT1.The first output signal OUT1 and the second output signal OUT2 is enabled when simultaneously Time, lead-out terminal 1210 can be under the conditions of straight-through (shoot-through) or become direct short-circuit.? Under the conditions of Zhi Tong, can be formed low in the first output transistor TRO1 and the second output transistor TRO2 Resistor path, and electric current can flow through the first transistor TRO1 and transistor seconds TRO2 in a large number.Work as height When supply voltage HVCC increases, amount of current can increase.Straight-through condition may cause damaging each The high power consumption of transistor, mains ripple and/or overheated.Thus, interlock system 1200 can be by providing The first output signal OUT1 that non-concurrent enables and the second output signal OUT2 using provide burning voltage as The first system output signal SOUT1.Such as, the voltage of high supply voltage HVCC can be more than 600V.

Figure 13 is the figure illustrating the interlock system 1300 including interlock circuit 10 according to some example embodiment.

With reference to Figure 13, interlock system 1300 can include interface circuit 1310, pulse generation circuit 1320, Input signal generates terminal 1330, interlock circuit 10, RS latch 1340 and power output unit 1350.

The interlock system 1300 of Figure 13 can be included in high-voltage integrated circuit (HVIC), and can To control IGBT based on second system output signal SOUT2.

The example of interlock circuit 10 can include the interlock circuit described referring to figs. 1 to Figure 10.Interlock circuit 10 receive the first input signal IN1 and the second input signal IN2 and the first output providing non-concurrent to enable Signal OUT1 and the second output signal OUT2.

Interface circuit 1310 is connected between supply voltage VCC and ground voltage GND, receives height power supply defeated Enter signal HIN and interface signal I/F is provided.

Pulse generation circuit 1320 is connected between supply voltage VCC and ground voltage GND, and permissible The first pulse signal P1 or the second pulse signal P2 is generated based on interface signal I/F.Interface signal I/F is permissible According to high supply input signal HIN, there is rising edge or trailing edge, and can in response to rising edge or under Drop along and the first pulse signal P1 or the second pulse signal P2 is provided.

Input signal generates terminal 1330 and is connected to the first high supply voltage HVCC1 and ground voltage GND Between, and the first input signal signal generating unit 1331 and the second input signal signal generating unit 1333 can be included. First input signal signal generating unit 1331 can include being connected to the first high supply voltage HVCC1 and ground connection electricity The 3rd output transistor TRO3 between pressure GND and the 3rd resistor R3, and the second input signal generates Unit 1333 can include the 4th output transistor TRO4 and the 4th resistor R4.3rd resistor R3 can Be connected to the 3rd output transistor TRO3 the high supply voltage HVCC1 of the first terminal and first between.The Three output transistor TRO3 may include that grid, receives the first pulse signal P1；The first terminal, connects To the 3rd resistor R3；And second terminal, it is connected to ground voltage GND.3rd output transistor TRO3 The first input signal IN1 is provided by the first terminal in response to the first pulse signal P1.

4th transistor R4 can be connected to the first terminal and the first high power supply of the 4th output transistor TRO4 Between voltage HVCC1.4th output transistor TRO4 may include that grid, receives the second pulse signal P2；The first terminal, is connected to the 4th resistor R4；And second terminal, it is connected to ground voltage GND. 4th output transistor TRO4 provides the second input letter in response to the second pulse signal P2 by the first terminal Number IN2.

The first input signal IN1 can be provided in response to the first pulse signal P1, or can be in response to Two pulse signal P2 and the second input signal IN2 is provided.3rd output transistor TRO3 can be in response to One pulse signal P1 and turn on, and can change in third transistor when third transistor TRO3 turns on The voltage of the terminal between R3 and the 3rd output transistor TRO3.Thus, it is provided that the first input signal IN1. If on the contrary, the 4th output transistor TRO4 turns in response to the second pulse signal P2, then provide Two input signals IN2.

Interlock circuit 10 in response to the first input signal IN1 and the second input signal IN2 to RS latch 1340 provide the first output signal OUT1 of enabling of non-concurrent and the second output signal OUT2.

RS latch 1340 enables power input signal PIN in response to the first output signal OUT1, and rings Power input signal PIN should be disabled in the second output signal OUT2.If in RS latch 1340 First output signal OUT1 and the second output signal OUT2 are simultaneously corresponding to logic state " high ", then circuit May become highly unstable.If circuit is by the high voltage (voltage of the such as first high supply voltage HVCC1 Voltage with the second high supply voltage HVCC2) drive, then may damage circuit.Thus, interlock circuit 10 can be by preventing from enabling the first output signal OUT1 and the second output signal OUT2 improves electricity simultaneously Road stability.

Power output unit 1350 can be in response to power input signal PIN to second system output signal SOUT2 provides the voltage of the first high supply voltage HVCC1 or carries to second system output signal SOUT2 Voltage for the second high supply voltage HVCC2.Such as, the voltage and of the first high supply voltage HVCC1 The voltage of two high supply voltage HVCC2 can be thousands of volt and the difference can therebetween with about 15V. Power output unit 1350 can include being connected to the first high supply voltage HVCC1 and the second high supply voltage The 6th output transistor TRO6 between HVCC2 and the 5th output transistor TRO5.General by the 5th The grid of output transistor TRO5 and the grid input power input signal of the 6th output transistor TRO6 PIN, and the 5th output transistor TRO5 and the 6th output transistor TRO6 can correspond in response to merit Rate input signal PIN and the PMOS transistor that complementally operates and nmos pass transistor.

But, although in Figure 12 and Figure 13, interlock circuit 10 is configured to based on the first input signal IN1 The first output signal OUT1 and the second output signal OUT2 is provided with the second input signal IN2, but this Embodiment is not limited to this, and interlock circuit 10 can provide non-concurrent to enable based on multiple input signals Multiple output signals.

It is multiple defeated with provide non-concurrent to enable that interlock circuit according to concept of the present invention can cancel in-phase signal Go out signal, and may be inserted into predetermined idle time to prevent from wherein enabling the lap of multiple output signal. It addition, interlock circuit can enable input signal by the mode of FIFO based on first enables output signal. Interlock circuit and interlock system can have the simple logic circuit configuration for performing multiple function, thus subtract The size of the high-tension integrated circuit of little use.

As it has been described above, according to the interlock circuit of concept of the present invention with include that the interlock system of this interlock circuit is permissible Reduce by preventing from enabling output signal based on the multiple signals being simultaneously entered within its time of input filter Output signal error.

It addition, interlock circuit and include that the interlock system of this interlock circuit can be implemented as small size, because it Have for carry out FIFO operation, in-phase signal suppression operation and output suppression operation easy configuration.

Although being particularly shown and described the present invention by reference to the exemplary embodiment of the present invention, but this Field those of ordinary skill it is understood that the present invention can be made the various changes in form and details, and Without departing from the spirit and scope of the present invention the most defined in the appended claims.

Claims (19)

1. an interlock circuit, including:

Input delay unit, it postpones multiple input signals, provides multiple delay input signal and by right The plurality of delay input signal carries out logical operations to provide multiple exclusive input signal；And

Output suppression unit, it provides based on the plurality of exclusive input signal and the plurality of input signal Multiple output signals that non-concurrent enables,

Wherein, described output suppression unit includes multiple output suppression circuit, and wherein, the plurality of output presses down Each output suppression circuit in circuit processed includes:

Arranging circuit, it is by based on first included in the plurality of exclusive input signal exclusive input letter Number, the first delay input signal of including at the plurality of delay input signal and with in the plurality of input The second complementary input signal that the complementary signal of the second input signal that signal includes is corresponding carries out logic AND Computing provides first to arrange signal；

Reset circuit, its by the second output signal and with first included in the plurality of input signal The first complementary input signal that the complementary signal of input signal is corresponding carries out OR logical operations provides the first weight Confidence number；And

Output latch circuit, it arranges signal based on described first and described first reset signal provides first Output signal.

Interlock circuit the most according to claim 1, wherein, described input delay unit includes:

Delay cell, it includes postponing the plurality of input signal respectively and provide the plurality of to postpone input letter Number multiple input delay circuit；And

Exclusive ALU, it includes by the plurality of delay input signal carries out exclusive patrolling respectively Collect computing and the multiple exclusive logical operation circuit of the plurality of exclusive input signal is provided.

Interlock circuit the most according to claim 2, wherein, at the plurality of exclusive logical operation circuit The the first exclusive logical operation circuit included is by described first delay input signal with except described first The complementary signal of the delay input signal outside delay input signal carries out logical AND operation to provide described One exclusive input signal.

Interlock circuit the most according to claim 2, wherein, wraps in the plurality of input delay circuit The the first input delay circuit included includes:

The first transistor, its grid including receiving described first input signal and receive the of supply voltage One terminal；

First resistor, it is connected between primary nodal point and the second terminal of described the first transistor；

Transistor seconds, it includes receiving the grid of described first input signal, being connected to the of ground voltage One terminal and be connected to the second terminal of described primary nodal point；

Second resistor, it is connected between described primary nodal point and secondary nodal point；And

Capacitor, it is connected between described ground voltage and described secondary nodal point.

Interlock circuit the most according to claim 4, wherein said first delay input signal is by described Two nodes provide,

Wherein, when described first input signal changes to logic state " high " from logic state " low ", described One delay input signal is delayed by the predetermined input delay time, and

When described first input signal changes to logic state " low " from logic state " high ", described first postpones Input signal is delayed by predetermined idle time.

Interlock circuit the most according to claim 5, wherein, based on described first resistor and the second electricity Resistance device determines described predetermined input delay time and described predetermined idle time.

Interlock circuit the most according to claim 6, wherein, described predetermined idle time is more predetermined than described The input delay time is long.

Interlock circuit the most according to claim 1, wherein, described output latch circuit is in response to described First arranges signal and enables described first output signal, and disables institute in response to described first reset signal State the first output signal.

9. an interlock circuit, including:

Delay cell, it receives the first input signal and the second input signal, by described first input signal and Described second input signal postpones scheduled delay and provides the first delay input signal and the second delay defeated Enter signal；

Exclusive ALU, it is by described first delay input signal and the second delay input signal Carry out exclusive logical operations and the first exclusive input signal and the second exclusive input signal are provided；

Noise removing unit, it postpones defeated based on the first reset signal and the second reset signal and described first Enter signal and the second delay input signal provides the first noise suppression signal and the second noise suppression signal；

Arranging unit, it is based on described first noise suppression signal, described first exclusive input signal and described Second input signal provides first to arrange signal, and based on described second noise suppression signal, described second Exclusive input signal and described first input signal provide second to arrange signal；

Reset cell, it provides the first reset signal based on described first input signal and the second output signal, And provide the second reset signal based on described second input signal and the first output signal；And

Output latch unit, it arranges signal based on described first and described first reset signal provides described First output signal, and signal is set based on described second and described second reset signal provides described second Output signal.

Interlock circuit the most according to claim 9, wherein, described noise removing unit includes:

First noise remove latch cicuit, it enables described first in response to described first delay input signal Noise suppression signal, and disable described first noise suppression signal in response to described first reset signal；With And

Second noise remove latch cicuit, it enables described second in response to described second delay input signal Noise suppression signal, and disable described second noise suppression signal in response to described second reset signal.

11. interlock circuits according to claim 9, wherein, the described unit that arranges includes:

First arranges circuit, and it is by described first noise suppression signal, described first exclusive input signal With second complementary input signal corresponding with the complementary signal of described second input signal carries out logical AND operation There is provided described first signal is set；And

Second arranges circuit, and it is by described second noise suppression signal, described second exclusive input signal With first complementary input signal corresponding with the complementary signal of described first input signal carries out logical AND operation There is provided described second signal is set.

12. interlock circuits according to claim 9, wherein, described reset circuit includes:

First reset circuit, its by described second output signal and with the complementation of described first input signal The first complementary input signal that signal is corresponding carries out OR logical operations to provide described first reset signal；And

Second reset circuit, its by described first output signal and with the complementation of described second input signal The second complementary input signal that signal is corresponding carries out OR logical operations to provide described second reset signal.

13. interlock circuits according to claim 9, wherein, described output latch unit includes:

First output latch circuit, it arranges signal in response to described first and enables described first output signal, And disable described first output signal in response to described first reset signal；And

Second output latch circuit, it arranges signal in response to described second and enables described second output signal, And disable described second output signal in response to described second reset signal.

14. interlock circuits according to claim 13, wherein, described first output latch circuit is in institute State first to arrange signal and described first reset signal and time the most disabled, maintain the previous of described first output signal State, and

Described second output latch circuit arranges signal and described second reset signal is the most disabled described second Time maintain the original state of described second output signal.

15. 1 kinds of interlock systems, including:

Interlock circuit, it receives the first input signal and the second input signal provide non-concurrent to enable first Output signal and the second output signal；And

Lead-out terminal, it provides system output letter in response to described first output signal and the second output signal Number,

Wherein, described interlock circuit includes:

Input delay unit, described first input signal and the second input signal are postponed predetermined delay by it Time, provide the first delay input signal and the second delay input signal and by described first postpone defeated Enter signal and the second delay input signal carries out logical operations and provides the first exclusive input signal and second exclusive Input signal；And

Output suppression unit, its based on described first exclusive input signal and the second exclusive input signal, Described first input signal and the second input signal and described first delay input signal and second postpone input Signal enables described first output signal and the second output signal, and based on described first input signal and Two input signals and described first output signal and the second output signal disable described first output signal and Second output signal.

16. interlock systems according to claim 15, wherein, described lead-out terminal includes:

First output transistor, it grid including receiving described first output signal and reception height power supply electricity The first terminal of pressure；And

Second output transistor, it includes receiving the grid of described second output signal, being connected to described first The first terminal of the second terminal of output transistor and be connected to the second terminal of ground voltage,

Wherein, described system output signal is provided by the second terminal of described first output transistor.

17. interlock systems according to claim 15, wherein, described lead-out terminal includes:

Resetting/arrange RS latch, it enables power input signal in response to described first output signal, And disable described power input signal in response to described second output signal；And

Power output unit, it provides described system output signal in response to described power input signal.

18. interlock systems according to claim 17, wherein, described power output unit includes:

First output transistor, its grid including receiving described power input signal and to be connected to first high The first terminal of supply voltage；And

Second output transistor, it includes receiving the grid of described power input signal, being connected to described first The first terminal of the second terminal of output transistor and be connected to the second terminal of the second high supply voltage,

Wherein, described system output signal is provided from the second terminal of described first output transistor.

19. interlock systems according to claim 17, also include:

First input signal signal generating unit, it include being connected in series in the first high supply voltage and ground voltage it Between the 3rd resistor and the 3rd output transistor, and in response to the first pulse signal to the described 3rd Terminal between resistor and described 3rd output transistor provides described first input signal；And

Second input signal signal generating unit, it includes that being connected in series in described first high supply voltage connects with described The 4th resistor between ground voltage and the 4th output transistor, and in response to the second pulse signal to Terminal between described 4th resistor and described 4th output transistor provides described second input signal.