CN102299178A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN102299178A CN102299178A CN2010102151671A CN201010215167A CN102299178A CN 102299178 A CN102299178 A CN 102299178A CN 2010102151671 A CN2010102151671 A CN 2010102151671A CN 201010215167 A CN201010215167 A CN 201010215167A CN 102299178 A CN102299178 A CN 102299178A
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Abstract
The invention provides a semiconductor structure which comprises a substrate, a source region and a drain region formed on the substrate, a gate contact region formed on the substrate and a stack structure which is formed on the substrate and is positioned between the source region and the drain region, wherein the stack structure comprises at least a unit, the unit comprises a first gate, a second gate and a channel formed between the first gate and the second gate. By adopting the stack FET (field effect transistor) device structure, the size of the device can be effectively reduced, the control ability of the channel can be enhanced and the technology of 22nm and below new generation VLSI (very large scale integrated circuit) with low energy consumption and high speed can be realized.
Description
Technical field
The present invention relates to semiconductor design and manufacturing field thereof, structure of particularly a kind of stacked field-effect transistor (stacking FET) and preparation method thereof.
Background technology
Along with development of semiconductor, especially in VLSI (very lagre scale integrated circuit (VLSIC)) technical field, on the basis that does not reduce device performance, further dwindling chip size and reducing its energy density becomes current research trend.Because the high mobility of III-V compounds of group, compare with the Si MOSFET (mos field effect transistor) of standard, possesses the high advantage that drives of low energy consumption, so in recent years to its research heat up again (with reference to M.Radosavlgevic etc., " Advanced High-K Gate Dielectric for High-Performance Short-Channel In
0.7Ga
0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications ", IEDM2009,319-322 page or leaf).And the III-V compound material is used for the research and development of VLSI chip of future generation, in the raising speed that cuts down the consumption of energy, also be a challenge to the requirement of chip size.
Summary of the invention
Purpose of the present invention is intended to one of solve the problems of the technologies described above at least, particularly proposes a kind of stacked FET structure, effective reduction of device size, and can realize this structure by the VLSI technology below the 22nm.
For achieving the above object, one aspect of the present invention proposes a kind of semiconductor structure, comprising: substrate; Be formed on source region and drain region on the described substrate; Be formed on the gate contact region on the described substrate; And be formed on the stacked structure between described source region and drain region on the described substrate, and described stacked structure comprises at least one unit, described unit comprises first grid, second grid and is formed on raceway groove between described first grid and the second grid.
On the other hand, the present invention proposes a kind of preparation method who forms above-mentioned semiconductor structure, may further comprise the steps: substrate is provided; On described substrate, form stacked structure, described stacked structure comprises at least one unit, described unit comprises first grid, second grid and is formed on raceway groove between described first grid and the second grid, and each described first grid and second grid along first insulating barrier that forms on the sidewall of first direction; Form source region and drain region on described substrate, described source region contacts with described stacked structure on described first direction with the drain region; On the sidewall of each described raceway groove, form second insulating barrier along second direction; Form gate contact region along described second direction in the both sides of described stacked structure.
The present invention is by proposing a kind of stacked FET semiconductor structure, effective reduction of device size: on the one hand, dwindle by the control of double gate (dual gate) and the size of thin channel layer structure realization orientation; On the other hand, dwindle by the size of multiple raceway groove stacked structure (multiple stack) realization channel width dimension.More than the combination of two aspect characteristics, become the key of high-speed 22nm of low energy consumption and following VLSI technological break-through of new generation.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, and accompanying drawing of the present invention is schematically, does not therefore draw in proportion.Wherein:
The semiconductor structure schematic diagram that Fig. 1-3 proposes for the embodiment of the invention;
Fig. 4-26 is preparation method's the intermediate steps schematic diagram of the semiconductor structure of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition, first feature described below second feature it " on " structure can comprise that first and second features form the embodiment of direct contact, can comprise that also additional features is formed on the embodiment between first and second features, such first and second features may not be direct contacts.
As Figure 1-3, be the semiconductor structure schematic diagram that the embodiment of the invention proposes, wherein Fig. 1 is a vertical view, and Fig. 2 and Fig. 3 are respectively along the profile of AA ' in the vertical view and BB '.This structure comprises: stacked structure 200, source region 300 and drain region 400 and grid that substrate 100, substrate 100 can preferably include a resilient coating 101, be formed on the resilient coating 101 contact porose area 500.Wherein, resilient coating 101 is made of the material that comprises a kind of III-V compounds of group at least.Source region 300 and drain region 400 are positioned at the both sides of stacked structure 200 along AA ' direction, and gate contact region 500 is positioned at the both sides of stacked structure 200 along BB ' direction.Isolate by insulating material 109 between each grid contact porose area 500.Stacked structure 200 comprises a unit 001 at least, preferably, comprises the repeatedly stacking of a plurality of unit, and source region, drain region and stacked structure are equal substantially, dwindles to realize the size of device on channel width dimension.As shown in Figure 2, unit 001 comprise first grid 102-1, second grid 102-2 and be formed on first grid 102-1 and second grid 102-2 between raceway groove 103, between raceway groove 103 and the first grid 102-1, be formed with gate dielectric layer 104 respectively between raceway groove 103 and the second grid 102-2.First grid 102-1 and second grid 102-2 constitute double gate (dual gate), dwindle by the size of structure realization device on orientation of double gate.Below describe for convenient, comprise follow-up preparation method's part, the orientation of device is defined as first direction (AA ' direction among each figure), channel width dimension is defined as second direction (BB ' direction among each figure).First grid 102-1 and second grid 102-2 comprise first insulating barrier 1 on first direction, to isolate source region and drain region.Raceway groove 103 comprises second insulating barrier 106 on second direction, with isolation channel with contact porose area 500 with grid.Be noted that the orlop of stacked structure 200 and the superiors are gate dielectric layer 104, and two adjacent unit, 001 a shared grid, for example, promptly the first grid of certain unit is the second grid of an adjacent cells on it simultaneously.In a preferred embodiment, the thickness of gate dielectric layer 104 is 1-3nm, and the thickness of grid layer 102 is 2-10nm, and the thickness of channel layer 103 is 2-10nm.
On the one hand, the thin channel layer structure between double gate and the double gate can effectively reduce short-channel effect, thereby can realize that device dwindles along the size of orientation; On the other hand, the effective width of device is to be determined by two factors of number that the developed width of channel region and raceway groove pile up, the present invention is promptly carried high drive current by the number that the increase raceway groove piles up, the developed width that need not to increase channel region can obtain bigger effective width, thereby can realize that device dwindles along the size of channel width dimension.
Further, the present invention proposes to form the preparation method of above-mentioned semiconductor structure, shown in Fig. 4-26, is the intermediate steps schematic diagram of this method.Below, come each step of the embodiment of the invention is described in detail with reference to these accompanying drawings.
Steps A: Semiconductor substrate 100 is provided.In embodiments of the present invention, substrate 100 is an example with body silicon, but in the practical application, substrate can comprise any suitable semiconductor substrate materials, specifically can be but is not limited to silicon, germanium, SiGe, SOI (silicon-on-insulator), carborundum, GaAs or any III/V compound semiconductor etc.According to the known designing requirement of prior art (for example p type substrate or n type substrate), substrate 100 can comprise various doping configurations.In addition, substrate 100 can comprise epitaxial loayer alternatively, can be by stress changes to strengthen the property.
Preferably, substrate 100 surfaces comprise resilient coating 101.A kind of III-V compounds of group on resilient coating 101 comprises is as GaAS.Resilient coating can adopt conventional depositing technics to form for example sputter, PLD, MOCVD, ALD, PEALD or other suitable methods.
Step B: on substrate, form stacked structure 200.Particularly, at first on the resilient coating 101 on down deposit gate dielectric layer 104, grid layer 102, gate dielectric layer 104, channel layer 103, gate dielectric layer 104, grid layer 102, gate dielectric layer 104 successively, so alternately repeat some unit, with gate dielectric layer 104 for stopping layer.Shown in Fig. 4-5, wherein Fig. 4 is a vertical view, and Fig. 5 is the profile along AA ' among Fig. 4.Wherein, gate dielectric layer 104, grid layer 102, channel layer 103 include the III-V compounds of group, and still, gate dielectric layer 104 is a wide bandgap material, and as InAlAs, grid layer 102 and channel layer 103 are low bandgap material, as are respectively InAs, InGaAs.In the preferred embodiment of the invention, the thickness of gate dielectric layer 104 is 1-3nm, and the thickness of grid layer 102 is 2-10nm, and the thickness of channel layer 103 is 2-10nm.The deposit of layers of material can adopt conventional depositing technics to form for example sputter, PLD, MOCVD, ALD, PEALD or other suitable methods.
Graphical then stacked structure 200 promptly etches away the stack layer outside the channel region.For example realize by photoetching and anisotropic rie (RIE), with undermost gate dielectric layer 104 for stopping layer.Shown in Fig. 6-8, wherein Fig. 6 is a vertical view, and Fig. 7 and Fig. 8 are respectively along the profile of AA ' among Fig. 6 and BB '.
Then selectivity over etching grid layer 102 makes it to form opening with the gate dielectric layer 104 of its levels, and shown in Fig. 9-11, wherein Fig. 9 is a vertical view, and Figure 10 and Figure 11 are respectively along the profile of AA ' among Fig. 9 and BB '.
Last deposition insulating material one, and carry out anisotropy RIE for stopping layer, makes the above-mentioned opening of insulating material one filling to form first insulating barrier 105 with the sidewall of gate dielectric layer 104.Shown in Figure 12-14, wherein Figure 12 is a vertical view, and Figure 13 and Figure 14 are respectively along the profile of AA ' among Figure 12 and BB '.Described insulating material comprises silicon dioxide, silicon nitride, for example silicon dioxide.Deposition insulating material can adopt ald (ALD) or molecular layer deposition (MLD) or other method that is fit to.
Step C: on substrate, form source region 300 and drain region 400.Particularly, can be by epitaxial growth metal or semiconductor layer 107, for example InGaAs of Can Zaing.Be noted that this metal or semiconductor layer 107 form low ohm the contact with raceway groove 103 sidewalls.Carry out planarization then, for example chemico-mechanical polishing (CMP) is the stop surface with gate dielectric layer 104 surfaces of the superiors.Shown in Figure 15-17, wherein Figure 15 is a vertical view, and Figure 16 and Figure 17 are respectively along the profile of AA ' among Figure 15 and BB '.
Anisotropy RIE metal or semiconductor layer 107 are to form patterned source region 300 and drain region 400 then, simultaneously at BB ' direction over etching raceway groove 103, make raceway groove 103 darker than the over etching of grid layer 102 at the over etching of BB ' direction, as 5-20nm, thereby make the raceway groove 103 and the gate dielectric layer 104 of its levels form opening, shown in Figure 18-20, shown in Figure 18-20, wherein Figure 18 is a vertical view, and Figure 19 and Figure 20 are respectively along the profile of AA ' among Figure 18 and BB '.
Step D: on the sidewall of each raceway groove 103, form second insulating barrier 106 along BB ' direction.Comprise particularly: deposition insulating material two, then this insulating material is carried out anisotropy RIE, make the opening that forms among its filling step C to form insulating barrier 2 106.Shown in Figure 21-23, wherein Figure 21 is a vertical view, and Figure 22 and Figure 23 are respectively along the profile of AA ' among Figure 21 and BB '.Insulating material two comprises silicon dioxide, silicon nitride, for example silicon nitride.Deposition insulating material two can adopt ALD or MLD or other method that is fit to.
Then, with respect to second insulating barrier, 106 selective etchs, first insulating barrier 105, follow epitaxial growth metal or semi-conducting material, the InAs of Can Zaing for example, link to each other with grid layer 102 in the stacked structure 200 and to form grid extension area 108, then carry out planarization, for example chemico-mechanical polishing (CMP) is the stop surface with gate dielectric layer 104 surfaces of the superiors.Shown in Figure 24-26, wherein Figure 24 is a vertical view, and Figure 25 and Figure 26 are respectively along the profile of AA ' among Figure 24 and BB '.
Step e: form gate contact region 500 in the both sides of stacked structure 200 along BB ' direction, particularly, can anisotropy RIE grid extension area 108 to form gate contact region 500, then deposition insulating material 109, and carry out planarization (as CMP) with the superiors' gate dielectric layer 104 surfaces for stopping layer.Insulating material 109 comprises silicon dioxide, silicon nitride, for example silicon dioxide.As Figure 1-3, wherein Fig. 1 is a vertical view, and Fig. 2 and Fig. 3 are respectively along the profile of AA ' among Fig. 1 and BB '.
The present invention proposes semiconductor structure of a kind of stacked FET and preparation method thereof, on the one hand, by the control and the thin channel layer structure reduction short-channel effect of double gate, thereby the size that realizes orientation is dwindled; On the other hand, by the effective width of multiple raceway groove stacked structure increase FET device, thereby the size that realizes channel width dimension is dwindled.And, improve the raceway groove control ability of III-V family device by the dual-gate structure, be that device dwindles ability, increase effective width and reduce random fluctuation that these characteristics become the key of high-speed 22nm of low energy consumption and following VLSI technological break-through of new generation by stacked structure.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification that scope of the present invention is by claims and be equal to and limit to these embodiment.
Claims (19)
1. a semiconductor structure is characterized in that, comprising:
Substrate;
Be formed on source region and drain region on the described substrate;
Be formed on the gate contact region on the described substrate; With
Be formed on the stacked structure between described source region and drain region on the described substrate, described stacked structure comprises at least one unit, and described unit comprises first grid, second grid and is formed on raceway groove between described first grid and the second grid.
2. semiconductor structure as claimed in claim 1 is characterized in that described substrate surface comprises resilient coating, and described resilient coating comprises at least a III-V compounds of group.
3. semiconductor structure as claimed in claim 1 is characterized in that, described stacked structure comprises that a plurality of described unit repeatedly stacking forms, and described source region, drain region are equal substantially with described stacked structure.
4. semiconductor structure as claimed in claim 1 is characterized in that described source region and drain region are positioned at the both sides of described stacked structure on first direction, and described contact zone is positioned at the both sides of described stacked structure on second direction.
5. semiconductor structure as claimed in claim 1 is characterized in that, comprises gate dielectric layer respectively between described raceway groove and described first grid and the second grid.
6. semiconductor structure as claimed in claim 5 is characterized in that, described raceway groove, first grid, second grid and described gate dielectric layer comprise the III-V compounds of group.
7. semiconductor structure as claimed in claim 5 is characterized in that, the thickness of described raceway groove is 2-10nm, and the thickness of described first grid and second grid is 2-10nm, and the thickness of described gate dielectric layer is 1-3nm.
8. semiconductor structure as claimed in claim 1, it is characterized in that, described stacked structure also comprises first insulating barrier, and described first insulating barrier is arranged in the described first grid of each described unit and the both sides of second grid on first direction, to isolate described source region and drain region.
9. semiconductor structure as claimed in claim 1 is characterized in that described stacked structure also comprises second insulating barrier, and described second insulating barrier is arranged in the both sides of the described raceway groove of each described unit on second direction, to isolate described raceway groove and gate contact region.
10. as claim 1 or 4 or 8 or 9 described semiconductor structures, it is characterized in that described first direction is the length direction of described raceway groove, described second direction is the Width of described raceway groove.
11. the formation method of a semiconductor structure is characterized in that, may further comprise the steps:
A., substrate is provided;
B. on described substrate, form stacked structure, described stacked structure comprises at least one unit, described unit comprises first grid, second grid and is formed on raceway groove between described first grid and the second grid, and each described first grid and second grid along first insulating barrier that forms on the sidewall of first direction;
C. form source region and drain region on described substrate, described source region contacts with described stacked structure on described first direction with the drain region;
D, on the sidewall of each described raceway groove, form second insulating barrier along second direction;
E, form gate contact region in the both sides of described stacked structure along described second direction.
12. method as claimed in claim 11 is characterized in that, described steps A also is included in described substrate surface and forms resilient coating, and described resilient coating comprises at least a III-V compounds of group.
13. method as claimed in claim 11 is characterized in that, described stacked structure comprises that a plurality of described unit repeatedly stacking forms, and described source region, drain region are equal substantially with described stacked structure.
14. method as claimed in claim 11 is characterized in that, the step that forms stacked structure among the described step B also comprises: form gate dielectric layer respectively between described raceway groove and described first grid and second grid.
15. method as claimed in claim 14 is characterized in that, described raceway groove, first grid and second grid and described gate dielectric layer comprise the III-V compounds of group.
16. semiconductor structure as claimed in claim 14 is characterized in that, the thickness of described raceway groove is 2-10nm, and the thickness of described first grid and second grid is 2-10nm, and the thickness of described gate dielectric layer is 1-3nm.
17. method as claimed in claim 11 is characterized in that, the step that forms first insulating barrier among the described step B comprises:
The sidewall of described first grid of over etching and second grid is to form opening;
Fill described opening to form described first insulating barrier.
18. method as claimed in claim 11 is characterized in that, the step that forms second insulating barrier among the described step D comprises:
Along the sidewall of the described raceway groove of described second direction over etching to form opening;
Fill described opening to form described second insulating barrier.
19., it is characterized in that described first direction is described orientation as claim 11 or 18 described methods, described second direction is described channel width dimension.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103715195A (en) * | 2013-12-27 | 2014-04-09 | 中国科学院上海微系统与信息技术研究所 | Full annular grating CMOS structure based on silicon-based three-dimensional nano array and preparation method thereof |
| CN107275331A (en) * | 2012-09-28 | 2017-10-20 | 英特尔公司 | The epitaxial growth device layer that groove is limited |
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| US5780327A (en) * | 1996-03-05 | 1998-07-14 | International Business Machines Corporation | Vertical double-gate field effect transistor |
| JP2005079283A (en) * | 2003-08-29 | 2005-03-24 | Seiko Epson Corp | Thin film semiconductor device and its manufacturing method, electro-optical device, and electronic apparatus |
| WO2009060052A1 (en) * | 2007-11-09 | 2009-05-14 | Commissariat A L'energie Atomique | Sram memory cell equipped with transistors having a vertical multi-channel structure |
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Patent Citations (5)
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| US5567959A (en) * | 1993-12-27 | 1996-10-22 | Nec Corporation | Laminated complementary thin film transistor device with improved threshold adaptability |
| JPH08213584A (en) * | 1995-02-08 | 1996-08-20 | Casio Comput Co Ltd | Photoelectric converter |
| US5780327A (en) * | 1996-03-05 | 1998-07-14 | International Business Machines Corporation | Vertical double-gate field effect transistor |
| JP2005079283A (en) * | 2003-08-29 | 2005-03-24 | Seiko Epson Corp | Thin film semiconductor device and its manufacturing method, electro-optical device, and electronic apparatus |
| WO2009060052A1 (en) * | 2007-11-09 | 2009-05-14 | Commissariat A L'energie Atomique | Sram memory cell equipped with transistors having a vertical multi-channel structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275331A (en) * | 2012-09-28 | 2017-10-20 | 英特尔公司 | The epitaxial growth device layer that groove is limited |
| CN103715195A (en) * | 2013-12-27 | 2014-04-09 | 中国科学院上海微系统与信息技术研究所 | Full annular grating CMOS structure based on silicon-based three-dimensional nano array and preparation method thereof |
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