CN102289244B - Current-subtracting type composite compensation reference current source - Google Patents
Current-subtracting type composite compensation reference current source Download PDFInfo
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- CN102289244B CN102289244B CN 201110168239 CN201110168239A CN102289244B CN 102289244 B CN102289244 B CN 102289244B CN 201110168239 CN201110168239 CN 201110168239 CN 201110168239 A CN201110168239 A CN 201110168239A CN 102289244 B CN102289244 B CN 102289244B
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Abstract
The invention discloses a current-subtracting type composite compensation reference current source, which comprises five parts, namely a current generation circuit, a current mirror image circuit, a first-level current subtracting circuit, a second-level current subtracting circuit and a third-level current subtracting circuit, wherein an output end of the current generation circuit is connected with the current mirror image circuit; input ends of the first-level current subtracting circuit and the third-level current subtracting circuit are connected with the output end of the current mirrorimage circuit; the output end of the first-level current subtracting circuit is connected with the second-level current subtracting circuit; and the output end of the second-level current subtractingcircuit is connected with the third-level current subtracting circuit. The invention has the advantages that: the topological structure of the reference current source can be simplified, and the circuit utilization rate of the reference current source is improved, so the working efficiency of the reference current source is improved; by composite adoption of segmentation curvature compensation and high-order non-linear temperature compensation, a reference current can be effectively compensated in a wider temperature range; and the current-subtracting type composite compensation reference current source is applicable to most of analog and digital circuits in which the reference current source is required.
Description
Technical field
The invention belongs to electronic technology field; the electric current that further relates in the Analogous Integrated Electronic Circuits is asked the compound standard of compensation current source of poor type; as the pith of mimic channel and Digital Analog Hybrid Circuits, for other circuit module such as oscillator, wave filter, digital-to-analog conversion and precise time Postponement module provide stable reference current.
Background technology
All need reference current source in simulation, modulus mixing even totally digital circuit, reference current source is very important functional module in the integrated circuit.For electric current, not loss when long metal wire transmits, voltage then has loss, so, in the mimic channel of long interconnect metallization lines is arranged, more be inclined to use current reference source; In addition, ifs circuit adopts current-mode, can be than adopting voltage mode to work under higher frequency, to improve the speed of circuit, but the accuracy when current-mode circuit is worked in large-temperature range and stability directly are decided by the temperature stability of current source.In order to satisfy the requirement of circuit operate as normal under abominable external temperature environment, reference current source must have very little temperature coefficient.
(patent No. ZL 200510021871.2 for the patented technology that University of Electronic Science and Technology has " CMOS reference current source with higher-order temperature compensation ", Granted publication CN 100385363C) a kind of CMOS reference current source with higher-order temperature compensation is disclosed, mainly comprise: the single order temperature-compensated current produces circuit, for generation of the electric current through the single order temperature compensation; The high temperature section compensating current generating circuit of single order temperature-compensated current is for generation of the high temperature section offset current of single order temperature-compensated current; The low-temperature zone compensating current generating circuit of single order temperature-compensated current is for generation of the low-temperature zone offset current of single order temperature-compensated current; The electric current supercircuit is used for the single order temperature-compensated current is produced three electric currents that the low-temperature zone compensating current generating circuit of the high temperature section compensating current generating circuit of circuit, single order temperature-compensated current and single order temperature-compensated current produces temperature independent electric current of back output that superposes.Though this method has adopted the mode of utilizing the electric current of the electric current of PTAT (being directly proportional with temperature) and CTAT (being inversely proportional to temperature) to superpose in proportion in the different temperatures section to realize high-order temperature compensated, the output reference electric current, but still the less than one that exists is that reference current source circuit has adopted amplifier architecture, makes circuit structure complicated; The 2nd, in high-temperature section and low temperature section, there is a compensating current generating circuit idle respectively, make percentage of circuit utilization low, cause reference current source module work efficiency to reduce.
(patent No. ZL 200610020154.2 for the patented technology that University of Electronic Science and Technology has " negative temperature compensating current generating circuit and temperature compensating current reference source ", Granted publication CN 100373283C) a kind of negative temperature compensating current generating circuit and temperature compensating current reference source are disclosed, mainly comprise: the positive temperature-compensated current of single order produces circuit, for generation of the positive temperature-compensated current of single order; The positive temperature-compensated current of second order produces circuit, for generation of the positive temperature-compensated current of second order; Three rank negative temperature compensating current generating circuits are for generation of three rank negative temperature compensating currents; Ratio summing circuit and output circuit are used for that the positive temperature-compensated current of single order is produced circuit, the positive temperature-compensated current of second order and produce three electric currents that circuit and three rank negative temperature compensating current generating circuits produce temperature independent electric current of back output that superposes.This method has realized the temperature coefficient that reference current is lower, but still the deficiency that exists is that temperature range is narrow, only covers-10 ℃, and when being lower than-10 ℃, temperature coefficient worsens rapidly.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, provide a kind of electric current to ask the compound standard of compensation current source of poor type, adopt the common-source common-gate current mirror structure, improve Power Supply Rejection Ratio, simplify circuit structure, in two temperature sections, utilize same branch road to produce the offset current of two kinds of temperatures coefficient, improve percentage of circuit utilization, improve the module work efficiency, compound use segmentation curvature compensation and high-order nonlinear temperature compensation are compensated reference current in wideer temperature range, further reduce temperature coefficient, satisfy the requirement of reference current source performance index.
For achieving the above object, the present invention includes current generating circuit, current mirror circuit, first order electric current subtractor circuit, second level electric current subtractor circuit, third level electric current subtractor circuit five parts; Described current generating circuit output terminal connects current mirror circuit, current mirror circuit input termination input current, output terminal connects first order electric current subtractor circuit and third level electric current subtractor circuit, first order electric current subtractor circuit output terminal is connected to second level electric current subtractor circuit, and second level electric current subtractor circuit output terminal is connected to third level electric current subtractor circuit.
Compared with prior art the present invention has the following advantages:
(1) the present invention utilizes the common-source common-gate current mirror structure, and suitable Power Supply Rejection Ratio is provided, the baroque shortcoming of having avoided the available technology adopting amplifier circuit to cause, and circuit structure is simpler.
(2) the present invention utilizes same circuit to produce different offset currents at two temperature sections, not existing in the prior art has a compensating current generating circuit idle respectively in high temperature section and low-temperature zone, cause the ineffective shortcoming of reference current source module, improve the current source work efficiency.
(3) the present invention utilizes the method for segmentation curvature compensation and high-order nonlinear temperature compensation Application of composite, overcome the narrow limited shortcoming of compensation effect that causes of single compensation method temperature range in the prior art, reference current is effectively compensated in wideer temperature range.
Description of drawings
Fig. 1 is the block scheme of circuit of the present invention;
Fig. 2 is the electrical schematic diagram of circuit of the present invention.
Embodiment
It is following that the present invention will be further described with reference to accompanying drawing.
With reference to Fig. 1, the present invention includes current generating circuit, current mirror circuit, first order electric current subtractor circuit, second level electric current subtractor circuit, third level electric current subtractor circuit five parts; Described current generating circuit output terminal connects current mirror circuit, current mirror circuit input termination input current, output terminal connects first order electric current subtractor circuit and third level electric current subtractor circuit, first order electric current subtractor circuit output terminal is connected to second level electric current subtractor circuit, and second level electric current subtractor circuit output terminal is connected to third level electric current subtractor circuit.
With reference to Fig. 2,4 series connection of triode 3 in the current generating circuit and resistance, input reference voltage connects the base stage of triode 3, drops on the resistance 4 after deducting the BE junction voltage of triode 3, produce negative temperature parameter current, flow out to the drain electrode of the PMOS pipe 2 the current mirror circuit from the collector of triode 3.
Current mirror circuit comprises eight PMOS pipes, two NMOS pipes.PMOS pipe 1 in eight PMOS pipes and PMOS manage 5 source electrodes and meet power vd D, the grid of PMOS pipe 1 is connected with the grid of its drain electrode with PMOS pipe 5 respectively, the connected mode of PMOS pipe 1 and PMOS pipe 5 constitutes the input of common-source common-gate current mirror to pipe, the drain electrode of PMOS pipe 1 connects input current, and input current is the negative temperature parameter current from the outside reference voltage module; PMOS pipe 1 in eight PMOS pipes and PMOS manage 16 source electrodes and meet power vd D, the grid of PMOS pipe 1 is connected with the grid of its drain electrode with PMOS pipe 16 respectively, the connected mode of PMOS pipe 1 and PMOS pipe 16 constitutes the input of common-source common-gate current mirror to pipe, and the drain electrode output negative temperature parameter current of PMOS pipe 16 is to third level electric current subtractor circuit; The grid of the PMOS pipe 9 in eight PMOS pipes is connected with the grid of its drain electrode with PMOS pipe 6 respectively, the drain electrode of PMOS pipe 6 connects the drain electrode of NMOS pipe 7, the drain electrode of PMOS pipe 9 connects the drain electrode of NMOS pipe 10, the source electrode of PMOS pipe 9 connects the drain electrode of PMOS pipe 8, PMOS pipe 8 is the diode type of attachment, source electrode meets power vd D, and the connected mode of PMOS pipe 6～10 constitutes cascade device bias-voltage generating circuit, produces bias voltage; The grid of the PMOS pipe 2 in eight PMOS pipes is connected with the grid of its drain electrode with PMOS pipe 11 respectively, its source electrode meets power vd D, the connected mode of PMOS pipe 2 and PMOS pipe 11 constitutes the input of common-source common-gate current mirror to pipe, and the drain electrode output current of PMOS pipe 11 is to first order electric current subtractor circuit; The grid of NMOS pipe 7 is connected with the grid of its drain electrode with NMOS pipe 10 respectively, the source ground of two pipes, and the connected mode of NMOS pipe 7 and NMOS pipe 10 constitutes current mirror.
First order electric current subtractor circuit comprises a PMOS pipe and a NMOS pipe.PMOS manages 12 grids and connects cascade device bias voltage, and source electrode connects the drain electrode of PMOS pipe 11, and drain electrode connects 13 drain electrodes of NMOS pipe; The grid of the NMOS pipe 7 in the grid of NMOS pipe 13 and the current mirror circuit is connected, source ground, and the mirror image negative temperature parameter current of NMOS pipe 13 asks poor with the electric current of PMOS pipe 12, generates first order offset current, and NMOS manages 13 and drains and export first order offset currents.Low thermophase, the electric current of PMOS pipe 12 is greater than the electric current of PMOS pipe 13, and the first order offset current of generation is the difference of two-way electric current, outputs in the electric current subtractor circuit of the second level; Hot stage, the electric current of PMOS pipe 12 is less than the electric current of PMOS pipe 13, because can not be reverse by the electric current of triode 14, flow through PMOS and manages 13 electric current and be forced to drag down, keep two metal-oxide-semiconductor electric currents and equate, do not have offset current to flow into second level electric current subtractor circuit.
Third level electric current subtractor circuit comprises a PMOS pipe and four NPN triodes.PMOS manages 17 grids and connects cascade device bias voltage, and source electrode connects the drain electrode of PMOS pipe 16 in the current mirror circuit, and drain electrode connects the collector of triode 18; Triode 18 base stages in four NPN triodes are connected with the base stage of its collector with triode 20 respectively, and emitter-base bandgap grading connects the collector of triode 19; The base stage of triode 19 is connected emitter grounding with the base stage of its collector with triode 21 respectively; Triode 21 emitter groundings, collector is connected with the emitter-base bandgap grading of triode 20; Four triodes are formed the mirror image circuit of similar metal-oxide-semiconductor common-source common-gate current mirror structure; The electric current of PMOS pipe 17 asks poor with the second level offset current that second level electric current subtractor circuit is imported, and the current mirror of generation is to triode 21, the collector output reference electric current of triode 20.
Claims (6)
1. an electric current is asked the compound standard of compensation current source of poor type, comprises current generating circuit, current mirror circuit, first order electric current subtractor circuit, second level electric current subtractor circuit, third level electric current subtractor circuit five parts; Described current generating circuit output terminal connects current mirror circuit, current mirror circuit input termination input current, output terminal connects first order electric current subtractor circuit and third level electric current subtractor circuit, first order electric current subtractor circuit output terminal is connected to second level electric current subtractor circuit, and second level electric current subtractor circuit output terminal is connected to third level electric current subtractor circuit.
2. electric current according to claim 1 is asked the compound standard of compensation current source of poor type, it is characterized in that: first triode (3) in the described current generating circuit and first resistance (4) series connection.
3. electric current according to claim 1 is asked the compound standard of compensation current source of poor type, it is characterized in that: described current mirror circuit comprises eight PMOS pipes, two NMOS pipes; Wherein:
PMOS pipe (1) in described eight PMOS pipes and the 3rd PMOS pipe (5) source electrode meet power vd D, the grid of the one PMOS pipe (1) is connected with the grid that the 3rd PMOS manages (5) with its drain electrode respectively, the connected mode of the one PMOS pipe (1) and the 3rd PMOS pipe (5) constitutes the input of common-source common-gate current mirror to pipe, the drain electrode of the one PMOS pipe (1) connects input current, and input current is the negative temperature parameter current from the outside reference voltage module;
PMOS pipe (1) in described eight PMOS pipes and the 6th PMOS pipe (16) source electrode meet power vd D, the grid of the one PMOS pipe (1) is connected with the grid that the 6th PMOS manages (16) with its drain electrode respectively, the connected mode of the one PMOS pipe (1) and the 6th PMOS pipe (16) constitutes the input of common-source common-gate current mirror to pipe, and the drain electrode of the 6th PMOS pipe (16) output negative temperature parameter current is to third level electric current subtractor circuit;
The grid of the 8th PMOS pipe (9) in described eight PMOS pipes is connected with the grid that the 7th PMOS manages (6) with its drain electrode respectively, the drain electrode of the 7th PMOS pipe (6) connects the drain electrode of NMOS pipe (7), the drain electrode of the 8th PMOS pipe (9) connects the drain electrode of the 2nd NMOS pipe (10), the source electrode of the 8th PMOS pipe (9) connects the drain electrode of the 4th PMOS pipe (8), the 4th PMOS pipe (8) is the diode type of attachment, and source electrode meets power vd D; The connected mode of above-mentioned the 4th PMOS pipe (8), the 7th PMOS pipe (6), the 8th PMOS pipe (9), NMOS pipe (7) and the 2nd NMOS pipe (10) constitutes cascade device bias-voltage generating circuit, produces bias voltage;
The grid of the 2nd PMOS pipe (2) in described eight PMOS pipes is connected with the grid that the 5th PMOS manages (11) with its drain electrode respectively, its source electrode meets power vd D, the connected mode of the 2nd PMOS pipe (2) and the 5th PMOS pipe (11) constitutes the input of common-source common-gate current mirror to pipe, and the drain electrode output current of the 5th PMOS pipe (11) is to first order electric current subtractor circuit;
The grid of described NMOS pipe (7) is connected with the grid that the 2nd NMOS manages (10) with its drain electrode respectively, the source ground of two pipes, and the connected mode of NMOS pipe (7) and the 2nd NMOS pipe (10) constitutes current mirror.
4. electric current according to claim 1 is asked the compound standard of compensation current source of poor type, it is characterized in that: described first order electric current subtractor circuit comprises a PMOS pipe and a NMOS pipe; Wherein:
Described the 9th PMOS pipe (12) grid connects cascade device bias voltage, and source electrode connects the drain electrode of the 5th PMOS pipe (11), and drain electrode connects the 3rd NMOS pipe (13) drain electrode; The grid of the 3rd NMOS pipe (13) is connected with the grid that a NMOS in the current mirror circuit manages (7), source ground, the electric current of the mirror image negative temperature parameter current of the 3rd NMOS pipe (13) and the 9th PMOS pipe (12) asks poor, generate first order offset current, the 3rd NMOS pipe (13) drain electrode output first order offset current.
5. electric current according to claim 1 is asked the compound standard of compensation current source of poor type, it is characterized in that: second triode (14) in the electric current subtractor circuit of the described second level and second resistance (15) series connection, the base stage of second triode (14) is connected with its collector, emitter-base bandgap grading connects the base stage of the 4th triode (19) in the third level electric current subtractor circuit, the electric current of the electric current of second resistance (15) and second triode (14) asks poor, generate second level offset current, the emitter-base bandgap grading output second level offset current of second triode (14).
6. electric current according to claim 1 is asked the compound standard of compensation current source of poor type, it is characterized in that: described third level electric current subtractor circuit comprises a PMOS pipe and four NPN triodes; Wherein:
Described the tenth PMOS pipe (17) grid connects cascade device bias voltage, and source electrode connects the drain electrode of the 6th PMOS pipe (16) in the current mirror circuit, and drain electrode connects the collector of the 3rd triode (18);
The 3rd triode (18) base stage in described four NPN triodes is connected with the base stage of its collector with the 5th triode (20) respectively, and emitter-base bandgap grading connects the collector of the 4th triode (19); The base stage of the 4th triode (19) is connected emitter grounding with the base stage of its collector and the 6th triode (21) respectively; The 6th triode (21) emitter grounding, collector is connected with the emitter-base bandgap grading of the 5th triode (20); Four triodes are formed the mirror image circuit of similar metal-oxide-semiconductor common-source common-gate current mirror structure; The second level offset current of the electric current of the tenth PMOS pipe (17) and the input of second level electric current subtractor circuit asks poor, the current mirror to the of generation six triodes (21), the collector output reference electric current of the 5th triode (20).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110168239 CN102289244B (en) | 2011-06-21 | 2011-06-21 | Current-subtracting type composite compensation reference current source |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110168239 CN102289244B (en) | 2011-06-21 | 2011-06-21 | Current-subtracting type composite compensation reference current source |
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| CN102289244A CN102289244A (en) | 2011-12-21 |
| CN102289244B true CN102289244B (en) | 2013-09-25 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346744B (en) * | 2013-06-27 | 2016-08-10 | 四川和芯微电子股份有限公司 | Current arithmetic device |
| CN106873698A (en) * | 2017-04-01 | 2017-06-20 | 唯捷创芯(天津)电子技术股份有限公司 | A kind of current subtractor circuit, chip and communication terminal |
| CN114326917B (en) * | 2021-12-27 | 2023-11-03 | 厦门科塔电子有限公司 | Current reference temperature compensation circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4866399A (en) * | 1988-10-24 | 1989-09-12 | Delco Electronics Corporation | Noise immune current mirror |
| CN1529216A (en) * | 2003-10-17 | 2004-09-15 | 清华大学 | Reference current source of low-temp. coefficient and low power-supply-voltage coefficient |
| CN1779591A (en) * | 2005-10-18 | 2006-05-31 | 电子科技大学 | CMOS reference current source with higher-order temperature compensation |
| CN1811656A (en) * | 2006-01-16 | 2006-08-02 | 电子科技大学 | Negative temperature compensating current generating circuit and temperature compensating current reference source |
-
2011
- 2011-06-21 CN CN 201110168239 patent/CN102289244B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4866399A (en) * | 1988-10-24 | 1989-09-12 | Delco Electronics Corporation | Noise immune current mirror |
| CN1529216A (en) * | 2003-10-17 | 2004-09-15 | 清华大学 | Reference current source of low-temp. coefficient and low power-supply-voltage coefficient |
| CN1779591A (en) * | 2005-10-18 | 2006-05-31 | 电子科技大学 | CMOS reference current source with higher-order temperature compensation |
| CN1811656A (en) * | 2006-01-16 | 2006-08-02 | 电子科技大学 | Negative temperature compensating current generating circuit and temperature compensating current reference source |
Non-Patent Citations (4)
| Title |
|---|
| 一种新颖的快速启动零温度系数电流基准;曲玲玲等;《微电子学》;20090220;第39卷(第1期);16-20 * |
| 一种采用带隙结构的高精度电流基准电路设计;郭文雄等;《科学技术与工程》;20070301;第7卷(第5期);845-847,866 * |
| 曲玲玲等.一种新颖的快速启动零温度系数电流基准.《微电子学》.2009,第39卷(第1期),16-20. |
| 郭文雄等.一种采用带隙结构的高精度电流基准电路设计.《科学技术与工程》.2007,第7卷(第5期),845-847,866. |
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