CN1022868C

CN1022868C - Real-time feedback and processing system of education informations

Info

Publication number: CN1022868C
Application number: CN 88104582
Authority: CN
Inventors: 顾力兵; 徐章英
Original assignee: Individual
Current assignee: Individual
Priority date: 1988-07-21
Filing date: 1988-07-21
Publication date: 1993-11-24
Anticipated expiration: 2003-07-21
Also published as: CN1031438A

Abstract

The present invention relates to a real-time feedback and processing system of education information, which is composed of a host system of middle-and-low grade microcomputers 1, a special interface 2, a classroom address bus AB, a classroom data bus DB and a student's terminal cluster ST including a plurality of student's terminals (reactors) 3. with main processing procedures performed with machine codes, the system can use asynchronous test of multiple selected topics and input of multi-bit numbers, also greatly reduce the total number of class conducting wires, simplify interfaces, easily extend character sets and instruction sets and increase subsequent functions. Thus, the system is suitable for different requirements under various conditions.

Description

Real-time feedback and processing system of education informations

The present invention relates to teaching aid, belong to the computer-aided instruction utensil, relate in particular to a kind of education informations feedback and disposal system in real time with the electricity operation of response mode work.

At present with mini-computer system and special purpose interface and reactor faciation education informations real time processing system in conjunction with collocation form.For singly selecting reactive mode, can only synchronism detection, data processing speed is slower, and adopts the multi-way switch scheme, with in the classroom at 64 seats, the host interface extension line has 64 * 9=576 root lead, lay and overhaul all compare difficult.

The objective of the invention is to overcome the deficiency of said system,, be based on low and middle-grade microcomputers, propose a kind of newly-designed education informations feedback and disposal system in real time from vast middle and primary schools actual conditions.

The present invention contains interface bus IOBUS by micro-mainframe computer system 1, special purpose interface 2(), classroom address bus AB, classroom data bus DB and comprise that the student terminal group ST of several student terminals (reactor) 3 constitutes.Under the control of host computer system 1 special software, sequentially send the address of each student terminal 3 to classroom address bus AB by special purpose interface 2, accessed student terminal 3 is just sent into data classroom data bus DB, adopt 1 internal memory by special purpose interface 2, and do various processing into the main frame system.

Main system 1 is a mini-computer, comprises system software and specialized application software.The present invention does not have specific (special) requirements to it, can letter can be numerous, dispose 8 16kRAM internal memories, the simple system of CRT monitor and tape cassette player also can meet the demands.

Special purpose interface 2, classroom address bus AB, classroom data bus DB and student terminal 3 all are custom-designed for realizing purpose of the present invention.

Special purpose interface 2 is the impact dampers between classroom bus AB, DB and the host interface bus IOBUS, is made up of logic gate 4, data triple gate 5 and address latch 6.Be used for providing the address to classroom address bus AB, and data are adopted into main frame 1 data bus DATA, it also provides reset signal RES.The wherein input end of logic gate 4 and notch device selection line DS and read-write line R/ Link, insert the corresponding slotted eye of main frame by plug-in card, an output terminal output chip selection signal CS of logic gate 4 is to data triple gate 5, STROB is to address latch 6 for another output terminal output gating signal, the input termination host interface bus IOBUS data bus DATA of address latch 6, and output meets classroom data bus AB, the input termination classroom address bus DB of data triple gate 5, and the data bus DATA of output termination host interface bus IOBUS.When host computer system 1 provides the address of student terminal 3 by interface bus IOBUS to address latch 6, and send gating signal STROB by logic gate 4, just with address latch in the classroom of address latch 6 address bus AB.When host computer system 1 when special purpose interface 2 reads in data, send chip selection signal CS by logic gate 4 to data triple gate 5, the data of classroom data bus DB are adopted into main frame 1 internal memory by data triple gate 5.Special purpose interface 2 also provides power supply for student terminal 3.

Classroom bus AB, DB connect each student terminal 3 by connector.For standard 64 seats, comprise that power lead may be as few as 13 or 14 lines.Wherein data bus DB in classroom selects mode to use 3 leads by the synchronism detection list, uses 5 leads by the asynchronous test multiselect mode of freely selecting a topic, and control and

power bus use

4 or 3 leads, uses 6 leads when the classroom address bus is pressed the bus addressing scheme.

Student terminal 3 is the transponders that are placed on each student's desk.It is by scrambler 7, and monopulse produces circuit 8, ternary latch 9, logic control circuit 10 and address decoder 11 and forms.Wherein the design of logic control circuit 10 is one of key characters of the present invention, and it is made up of pulse shaping circuit 12, status register 13, two AND

circuit

14,15 and pulse distributor 16.Several button ON are sent in the input end connection of pulse shaping circuit 12, status register 13 is delivered in its output, two input ends of AND circuit 15 link with the chip selection signal CS end of the address decoder 11 of status register 13 output terminals and student terminal 3 respectively, and provide clearing signal CE to the ternary latch 9 of student terminal 3, the input end of pulse distributor 16 connects revises button Cr, its output connects status register 13 and scrambler 7 respectively, AND circuit 14 input ends link with the chip selection signal CS end of the address decoder 11 of student terminal 3 and the reset line RES of classroom bus respectively, the reset terminal of its output terminal and status register 13 links, thereby finishes following function:

Accept and store the load instruction (press and send several button ON) that button is sent here;

Accept address decoder 11 output signals, send number when, just send clearing signal CE to ternary latch 9;

RES is effective when reset signal, and load instruction is just eliminated when selected in the address;

Accept modify instruction (press and revise button Cr), finish retouching operation.

The input end of scrambler 7 is connected with digital keys, character keys and topic button, and one group of output terminal is connected to the data input pin of ternary latch 9, another output terminal output gating signal GS produces the gating end G that circuit 8 is delivered to ternary latch 9 through monopulse, the input end of address decoder 11 is connected to classroom address bus AB, the chip selection signal CS of its output terminal output delivers to logic control circuit 10, an input end of logic control circuit 10 is picked several button ON and is revised button Cr, another input termination reset signal RES, an output terminal of logic control circuit 10, the output terminal output clearing signal CE that is AND circuit 15 is to ternary latch 9, and another output terminal is revised button Cr and controlled by pulse distributor 16 output terminal output modifications signal C to scrambler 7.Operand word button, character keys, topic button and modification button Cr, scrambler 7 can produce respective code, realizes the Binary Conversion of key code.

The course of work of the present invention is as follows substantially: when pressing arbitrary input button, the gating useful signal GS that scrambler 7 provides produces circuit 8 through monopulse and is converted to the monopulse gating signal, and combination padlock is stored in ternary latch 9 wouldn't be sent.When press send several button ON after, promptly send load instruction here, load instruction is accepted and latched to logic control circuit 10, chosen by main frame 1 up to address decoder 11, when sending effective chip selection signal CS, AND circuit 15 through logic control circuit 10 is sent clearing signal CE to ternary latch 9, and its latch data is delivered to classroom data bus DB, and is connect by special use

Adopt into calculator memory, RES is effective in reset signal, and promptly under the selected situation in address, logic control circuit 10 resets, and eliminates load instruction, counts, realizes sending several requirements by turn to classroom data bus DB to accept once more to put.Under the management of corresponding software, will deliver to the data of main frame 1 internal memory make the decoding processing of the number of setting a question, numeral and control command, thereby realize that freely select a topic number, single choosing are reacted, multiselect reacts, long number is filled a vacancy and multiple operation such as modification.Pressing digital keys to pressing in the time of sending several buttons, terminal shows the number of being put so that check, and allows to revise.Revise button Cr when pressing, promptly send modify instruction, logic control circuit 10 is accepted and retouching operation is finished in control.In a single day data are sent, and show just to eliminate.In the time will inserting topic, press topic button N and high button simultaneously, numeral just is latched in the ternary latch 9, press then and send several button ON, under the address signal effect, export the clearing signal CE of ternary latch 9 by pulse shaping circuit 12, status register 13 and the AND circuit 15 of logic control circuit 10, the topic high position data just by main frame 1 adopt into, with the same manner, can insert low level topic number value.

The present invention has the following drawings:

Fig. 1 is The general frame of the present invention (student terminal group ST only draw a student terminal 3);

Fig. 2 is special purpose interface 2 block diagrams;

Fig. 3 is student terminal 3 block diagrams;

Fig. 4 is logic control circuit 10 block diagrams.

The present invention does not have specific (special) requirements to host computer system, and software and interface can adapt to the requirement of different types of machines, when user's conversion type, only need use corresponding interface and software instead. Its main processing procedure realizes with machine code, operation fast, it is few to account for internal memory, characteristics with Real-time Collection and fast processing, and function strengthens to some extent, can use the input of the asynchronous test of multiple choice (the freely number of selected topic) and long number, can also greatly reduce the classroom conductor bus, the components and parts bus, and the simplification interface, thereby cost is descended, easy for installation, in addition, the present invention also is easy to expansion, every increase by one data lines in data/address bus, and the keyboard number can be double, energy extended character set and command set, address wire of every increase in address bus, student terminal (reactor) can be double, in order to increase follow-up function.

The present invention has multiple embodiments, for example address bus fully decoded, or address wire two-stage decode, or address wire gate scheme etc., can adapt to needs different under the multiple condition. When in the low computer system, implementing, can be by special-purpose data transmission interface, with adopt into data to the more full microsystem transmission of configuration, process with the system that realizes data.

Embodiment:

Host computer system 1 adopts APPLE II main frame, 48kRAM, system configuration display, line printer, disc driver.Use DOS3.3CP/M and dBASE II system software, application software has some kinds of primary control programs and scale-of-two subroutine dish file.

Special purpose interface 2 is made up of four integrated circuit, and eight D triple gate 74LS373 make address latch 6; Six triple gate 74LS367 make data triple gate 5; Three end Sheffer stroke gate 74LS10 and not gate 74LS04 make logic gate 4.Its input end and notch device selection line DS and read-write line R/ W link, to accept main frame 1 control.Insert main frame 1 corresponding slotted eye by plug-in card, classroom bus AB, DB are drawn by plug-in card.

System adopts the fully decoded addressing scheme.Classroom address bus AB is 6 lines, and classroom data bus DB is 5 lines, and reset line RES is 1 line, and other has 2 power leads, is combined as one 14 line bus cable, and student terminal 3 can plug arbitrarily on bus cable.

Student terminal group ST is made up of 64 student terminals 3.Each student terminal 3 is made up of six integrated circuit, several diodes, triode and Resistor-Capacitor Unit, and 8-3 scrambler 74LS148 makes scrambler 7; Triode 3DG6 makes monopulse and produces circuit 8; Eight D triple gate 74LS373 make ternary latch 9; Two two end Sheffer stroke gate 74LS00 make logic control circuit 10; Two not gates and three end Sheffer stroke gate 74LS04,74LS30 make address decoder 11.64 student terminal 3 shared 2A/5V stabilized voltage supply power supplies, circuit board and button attach together in a computer shell, form single student terminal (reactor) 3.

The glance frequency of main frame 1 pan student terminal group ST is 2 times/second.Can freely the number of selected topic be asynchronous replys in 50 topics during test.Every topic " is selected to prop up " (give advice and learn alternative each branch) and mostly is 5 most.Can multiplely select.

All specialized equipment is contained in the case and becomes portable system.

Claims

1, a kind of by micro-mainframe computer system 1, special purpose interface 2, classroom address bus AB, classroom data bus DB with comprise education informations that the student terminal group ST of several student terminals (reactor) constitutes feedback and disposal system in real time, it is characterized in that:

1,1 special purpose interface 2 is by logic gate 4, data triple gate 5 and address latch 6 are formed, selection wire DS is set for the input end of logic gate 4 and notch and read-write line R/W links, insert the corresponding slotted eye of main frame by plug-in card, an output terminal output chip selection signal CS of logic gate 4 is to data triple gate 5, STROB is to address latch 6 for another output terminal output gating signal, the input termination host interface bus IOBUS data bus DATA of address latch 6, and output meets classroom data bus AB, the input termination classroom address bus DB of data triple gate 5, and the data bus DATA of output termination host interface bus IOBUS;

1,2 for standard 64 seats, classroom address bus AB and classroom data bus DB comprise that power lead may be as few as 13 or 14 lines, wherein data bus DB in classroom selects mode to use 3 leads by the synchronism detection list, singly select mode to use 5 leads by the asynchronous test of freely selecting a topic, control and power bus use 4 or 3 leads, use 6 leads when the classroom address bus is pressed the bus addressing scheme;

1,3 student terminals 3 are by scrambler 7, monopulse produces circuit 8, ternary latch 9, logic control circuit 10 and address decoder 11 are formed, the input end of scrambler 7 is connected with digital keys, character keys and topic button, and one group of output terminal is connected to the data input pin of ternary latch 9, another output terminal output gating signal GS produces the gating end G that circuit 8 is delivered to ternary latch 9 through monopulse, the input end of address decoder 11 is connected to classroom address bus AB, the chip selection signal CS of its output terminal output delivers to logic control circuit 10, an input end of logic control circuit 10 is picked several button ON and is revised button Cr, another input termination reset signal RES, an output terminal output clearing signal CE of logic control circuit 10 is to ternary latch 9, and another output terminal is revised button Cr control output modifications signal C to scrambler 7.

2, education informations as claimed in claim 1 is feedback and disposal system in real time, it is characterized in that logic control circuit 10 is by pulse shaping circuit 12, status register 13, two AND circuit 14,15 and pulse distributor 16 form, several button ON are sent in the input end connection of pulse shaping circuit 12, status register 13 is delivered in its output, two input ends of AND circuit 15 link with the chip selection signal CS end of the address decoder 11 of status register 13 output terminals and student terminal 3 respectively, and provide clearing signal CE to the ternary latch 9 of student terminal 3, the input end of pulse distributor 16 connects revises button Cr, its output connects status register 13 and scrambler 7 respectively, AND circuit 14 ends are gone into end and are linked with the chip selection signal CS end of the address decoder 11 of student terminal 3 and the reset line RES of classroom bus respectively, and the reset terminal of its output terminal and status register 13 links.