CN2256557Y - Machine for learning computer - Google Patents

Abstract

The utility model relates to a learning machine which is composed of a keyboard, a keyboard interface circuit, a central controller, a high-frequency circuit, a joy stick and a learning card, etc. The keyboard interface circuit is composed of a special SB02 counting decoder and a multiplex selector, etc.; compared with the existing learning machine, the utility model has the advantages of low cost, simple circuit, small circuit board area, stable performance and easy maintenance.

Description

A kind of learning machine

The utility model relates to a kind of learning machine, is a kind of home-use Chinese and English learning machine that is suitable for specifically.

At present, home-use learning machine is existing a variety of, and its hardware group becomes: keyboard, keyboard interface circuit, central controller, high-frequency circuit, operating rod and study card.Wherein keyboard is one of chief component of learning machine, and it is arranged in the switch of matrix by one group and the button knowledge sign indicating number interface circuit of CPU (central controller) interface is formed.Learning machine requires its keyboard identical with computer keyboard in order to reach its purpose, also uses 101 keyboards.Its principle of work is: CPU to the counting decoder chip select, selects 1 data selector chip select by chip selection signal P and read signal RD to 42, as shown in Figure 5 by chip selection signal P and write signal WR.After the starting, counting decoder begin the counting and to keyboard scan, data selector is to the last output of data bus D1～D4 number, CPU reading from D1～D4 line, if data are 1 entirely, show that then keyboard does not have key to be pressed, if data are not 1 entirely, then showing has key to be pressed, and this moment, CPU read key.When reading key, pulse signal CP is 1, and one group of parallel tetrad data that CPU reads are low four of key set code, and then pulse signal CP is 1, and one group of parallel tetrad data that CPU reads are the high four of key set code.CPU deciphers the addressing processing according to above-mentioned eight-digit binary number sign indicating number subsequently, thereby finishes the one-touch operation.Keyboard knowledge coding mode all adopts dynamic coding to know coding mode in the learning machine, and general interface circuit all is to select 1 data selector by one 42 at present, and a block count code translator and two 2 input nand gate circuit are formed.

The purpose of this utility model is the learning machine that a kind of interface circuit of design is simple more, the wiring board area is little.

The utility model can adopt following technical scheme: learning machine is made up of keyboard, keyboard interface circuit, central controller, high-frequency circuit, operating rod and study card, interface circuit comprises a MUX, a counting decoder and reads in control circuit, it is characterized in that: the above-mentioned control circuit that reads in is made up of one two Sheffer stroke gate.

The utility model is in above-mentioned technical scheme, and counting decoder and two NAND gate circuit have been formed a special-purpose SB02 counting decoder integrated package.

Below in conjunction with accompanying drawing the utility model is done the embodiment explanation:

Fig. 1 is the learning machine hardware structure diagram;

Fig. 2 is the utility model central controller, study card and interface circuit connection layout;

Fig. 3 is special-purpose SB02 counting decoder circuit diagram;

Fig. 4 is control signal and keyboard scanning signal sequential chart;

Fig. 5 is general existing learning machine interface circuit figure;

In the present embodiment, hardware group of the present utility model becomes: keyboard, keyboard interface circuit, central controller, high-frequency circuit, operating rod and study card.

In the utility model, keyboard interface circuit selects 1 data selector 74LS158 to form by special-purpose SB02 counting decoder and one 42, as shown in Figure 2.The internal circuit of SB02 counting decoder as shown in Figure 3, it comprises independently 2 input nand gates of a counting decoder that is output as Q0～Q12 and 1, the CP and the R input end of special-purpose SB02 counting decoder promptly are the input ends of its inner counting decoder, and Q0～Q12 output terminal promptly is the output terminal of its internal counter; And the input end A of special-purpose SB02 counting decoder and B promptly are two input ends of 2 input nand gates, and its output terminal Y promptly is the output terminal Y of 2 input nand gates.The time clock CP of special-purpose SB02 counter is sent by central controller CPU, its input end A and B are connected respectively to the LK signal controlling end in signal controlling end P and the study card of reading in of central controller CPU, its output terminal Y is connected to 42 A that select 1 data selector 74LS158 as the chip select signal, and output signal Q0～Q12 is then as keyboard scanning signal.

LK signal in the P signal of central controller CPU and the study card is input to the A and the B end of special-purpose SB02 counting decoder, play the chip select effect jointly, the CP end and 42 that the clock pulse signal CP of while CPU is input to special-purpose SB02 counting decoder selects the A/B of 1 data selector 74LS158 to hold.When work, the L K signal in the P signal of CPU and the study card is input to special-purpose SB02 counting decoder and carries out chip select, and CPU sends reset signal R simultaneously, begins to receive keyboard signal then; The CP end and 42 that clock pulse signal CP acts on special-purpose SB02 counting decoder simultaneously selects the A/B of 1 data selector 74LS158 to hold, Q0～the Q12 of special-purpose SB02 counting decoder brings out existing sweep signal, as shown in Figure 5, simultaneously 42 select 1 data selector 74LS158 on 1Y～4Y line, to send data, CPU reading of data from 1Y～4Y line.If data are 0 entirely, show that then keyboard does not have key to be pressed; If data are not 0 entirely, then showing has key to be pressed, at this moment, when pulse signal when A/B brings out existing low level, read one group parallel tetrad data of CPU are as low four of key set code; When A/B brought out existing high level, one group of parallel tetrad data that CPU reads were as connecing the high four of key.CPU deciphers the addressing processing according to above-mentioned eight-digit binary number sign indicating number subsequently, thereby finishes the scanning process of a keyboard.

The utility model is compared with existing learning machine, because interface circuit has only been used one two Sheffer stroke gate, and has adopted special-purpose SB02 counting decoder integrated package, thereby has simplified circuit, has reduced the wiring board area, has reduced cost.Owing to adopted SB02, the chip select signal has been reduced simultaneously, make circuit performance also more stable, also safeguard easily.

Claims (2)

1. learning machine, it is made up of keyboard, keyboard interface circuit, central controller, high-frequency circuit, operating rod and study card, interface circuit comprises a MUX, a counting decoder and reads in control circuit, it is characterized in that: the above-mentioned control circuit that reads in is made up of one two Sheffer stroke gate.

2. a kind of learning machine according to claim 1 is characterized in that said counting code translator and two NAND gate circuit have formed a special-purpose SBO2 counting decoder integrated package.

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