CN102281125A - Laminated and partitioned irregular low density parity check (LDPC) code decoder and decoding method - Google Patents
Laminated and partitioned irregular low density parity check (LDPC) code decoder and decoding method Download PDFInfo
- Publication number
- CN102281125A CN102281125A CN2011102153915A CN201110215391A CN102281125A CN 102281125 A CN102281125 A CN 102281125A CN 2011102153915 A CN2011102153915 A CN 2011102153915A CN 201110215391 A CN201110215391 A CN 201110215391A CN 102281125 A CN102281125 A CN 102281125A
- Authority
- CN
- China
- Prior art keywords
- node
- information
- bit
- processing unit
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Error Detection And Correction (AREA)
Abstract
The invention discloses a laminated and partitioned irregular low density parity check (LDPC) code decoder and a decoding method in the technical field of communication. An external information storage unit outputs a soft value transmitted to an information node by a last iterated check node to a decoding processing module. A cyclic shift register transmits a posterior probability likelihood ratio update value of the information node to the decoding processing module. The decoding processing module transmits the check update value in the iteration to the external information storage unit, and simultaneously transmits the posterior probability likelihood ratio update value of the information node to the cyclic shift register through a decoding processing module interweaving network. The decoder is suitable for decoding all quality control (QC) LDPC codes, and all the partitioned LDPC code words support decoding; the decoder has no stream competition conflict, and has better throughput performance and relatively simple working time sequence; and the consumption of the interweaving network of huge resources is not needed, many hardware resources are saved, and the resource consumption of the whole decoder is relatively low. The decoding supporting parallelism degree can be flexibly changed.
Description
Technical field
The present invention relates to a kind of decoder and interpretation method of communication technical field, specifically is a kind of hierarchical block irregular low-density check code device and interpretation method.
Background technology
Loe-density parity-check code (Low Density Parity Check Codes, LDPC Codes) is a kind of coding techniques that Gallager in 1963 at first proposes, has performance near shannon limit, become a research focus of coding field, be widely applied in the various wireless communication field standards, comprise the digital TV ground transmission standard of China, European second generation satellite digital video broadcast standard, IEEE 802.11n, IEEE 802.16e etc.In the present radio communication, the communication of high data rate more and more is subject to people's attention, and therefore simple in structure, the ldpc decoder that throughput is high is the research emphasis of LDPC sign indicating number always.In addition, in actual applications,, need to use the sign indicating number of different code length and code check to transmit according to the different and different channel conditions of the information of transmission.Therefore the ldpc decoder structure that can support the certain scale code length to obtain enough error correcting capabilities also is to need one of emphasis of considering in the decoder architecture design.In order to support big code length, resource consumption is very big usually, since present technical limitations, the FPGA resource-constrained, and the ldpc code decoder that resource cost is little also is the important research content.The structure of ldpc code decoder has three kinds of forms: serial structure, full parallel organization and part parallel structure.Part parallel structure ldpc decoder is because its moderate complexity and hardware resource consumption and extensive use.In addition, for ldpc decoder, different algorithms, for example belief propagation algorithm, minimum-sum algorithm, band correction minimum-sum algorithm, layering belief propagation algorithm, layering band correction minimum-sum algorithm etc., will influence the structure of ldpc decoder, influence the various aspects of decoder simultaneously, comprise throughput, performance, resource use etc.
Find through literature search prior art, number of patent application is 200710044708 Chinese patent, patent name is " low-density check code encoder of layering and a decoding process method ", carry and provided a kind of low-density check code encoder based on the correction minimum-sum algorithm, this decoder mainly is made up of processing module, external information memory cell, second memory cell and first interleaving network, second interleaving network.This decoder needs two interleaving networks, because the design feature of interleaving network makes that this decoder can the more hardware resource of consumption rate.And number of patent application is 200810200033 Chinese patent, and patent name is " the irregular low-density check code device and the decoding process method of layering ", and previous patent is further improved, and removes an interleaving network, has increased iteration and has stopped module.These two encoder/decoder systems all have interleaving network, expend huge resource, and unavoidably there is a flowing water conflict, need to insert idle flowing water latent period, influenced the decoding throughput greatly, the LE resource consumption of these two decoders is directly proportional with the spreading factor of QC-LDPC in addition, can hold any more at general FPGA for the QC-LDPC of code length greatly than big spreading factor.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, a hierarchical block irregular low-density check code device and interpretation method have been proposed, improved decoder architecture does not need interleaving network, has saved hardware resource consumption, and very little resource consumption is arranged, there is not the flowing water collision problem yet, better throughput performance is arranged, can support the QC-LDPC sign indicating number of very big spreading factor, support all QC-LDPC sign indicating number decoding, support multiple spreading factor and the decoding of depositing, the deficiency of having replenished preceding two decoders.
The present invention is achieved by the following technical solutions:
The present invention relates to a kind of hierarchical block irregular low-density check code device, comprising: external information memory cell, circulating register, decoding processing module, wherein:
The external information memory cell is that the checksum update value is exported to the decoding processing module with the soft value that the check-node of last iteration passes to information node, and the check updating value in this iteration of transmitting of storage decoding processing module;
Always total N of circulating register, N is a code letter matrix column number, and the posterior probability likelihood ratio of information node is passed to the decoding processing module, and the posterior probability likelihood ratio updating value of the information node that transmits of storage decoding processing module;
The decoding processing module passes to the external information memory cell with the checksum update value that passes to information node by check-node in this iteration, finish jointly by bit node processing unit and code check node processing unit, and the posterior probability likelihood ratio updating value of information node is passed to circulating register, finish jointly by bit node processing unit and information bit processing unit.
Described external information memory cell uses memory to realize, the memory number is the check-node number, data bit width is that the data bit width twice of external information adds up anharmonic ratio spy, storage maximum, minimum value and minimum value position, and storage depth is the mother matrix spreading factor.
Described circulating register number has the bit node number, and each circulating register input and output tap number is the column weight of bit node corresponding to mother matrix.
Described decoding processing module comprises: the one 2 selects 1 selector, bit node processing unit, code check node processing unit, information bit processing unit, wherein:
The one 2 selects 1 selector, and the data of input are selected, and select between the channel information and the information node posterior probability likelihood ratio of reading from circulating register, and the result that will select exports to the bit node processing unit;
The bit node processing unit has the heavy number of corresponding row to the every provisional capital of mother matrix, and the bit updating value of computing information node passes to code check node processing unit and information bit processing unit;
The code check node processing unit, number is M, and M is a code letter matrix line number, the bit updating value of the information node of sending here according to the bit node processing unit that receives, calculate the checksum update value of this iteration, and pass to information bit processing unit and external information memory cell;
The checksum update value of this iteration that bit updating value that the information bit processing unit transmits according to the bit node processing unit and code check node processing unit transmit is come computing information node posterior probability likelihood ratio updating value, exports to circulating register.
Described bit node processing unit comprises: subtracter, the first complement code transducer and the first cut position arithmetic unit, wherein:
Subtracter subtracts each other the checksum update value of the last iteration that first information node posterior probability likelihood ratio and external information memory cell are read, and obtains the information updating value of information node, passes to the first complement code transducer;
The first complement code transducer is converted to the numeral of sign bit-absolute value form with the information updating value of information node, and is transferred to the first cut position arithmetic unit;
The first cut position arithmetic unit carries out the cut position operation to the dateout of the first complement code transducer, bit wide is become the bit wide of original information node information of being scheduled to, become big situation to avoid in the process that adds up, occurring data bit width, promptly obtain the bit updating value of information node.
Described code check node processing unit comprises: minimum is inferior searches module, multiplier, the second cut position arithmetic unit and the second complement code transducer for a short time, wherein:
For a short time search the information that module transmits from the bit node processing unit for minimum time and find out minimum value and sub-minimum, so that the further property taken advantage of correcting process is saved in the external information memory cell,
Multiplier multiply by a constant with minimum inferior output of searching module for a short time, the output of multiplier is again by the second cut position arithmetic unit, the bit wide of verification updating value is retrained within the specific limits,, obtain the checksum update value of final this iteration afterwards again through the second complement code transducer.
Described minimum time searches for a short time that module is made up of many four inputs, two output junior units and junior units are exported in two inputs two, wherein:
Two nodal informations of two inputs, two output junior units inputs are output as and arrange good former state data by size, and effect is that two numbers are sorted, and is made of selector;
Four inputs of four inputs, two output junior units are four outputs of two two inputs, two outputs or other two four input two outputs, and effect is minimum and the sub-minimum selected inside two groups of input data that sequence size in four;
Described information bit processing unit comprises: buffer, the 3rd complement code transducer, adder, wherein:
Buffer is used to deposit the bit updating value of the information node that the bit node processing unit transmits, and its length equals the number (promptly equaling the row weight of the corresponding current check-node of check matrix) of the information node that links to each other with current check-node;
The buffer that the 3rd complement code transducer receives in the code check node processing unit transmits data, and the data of symbol-absolute value form are converted to complement form;
The checksum update value addition of this iteration that adder transmits the output and the code check node processing unit of the 3rd complement code transducer obtains information node posterior probability likelihood ratio updating value, passes to the decoding circulating register.
The present invention relates to a kind of hierarchical block irregular low-density check code method, may further comprise the steps:
Step 1, the input data (channel value) of acquisition decoder;
Step 2, selector is selected the input data of information node posterior probability likelihood ratio, if this information node participates in decoding for the first time in decode procedure, the shift register of then selecting firm input channel information is as information node posterior probability likelihood ratio, otherwise the data of reading from the another one circulating register pass to the decoding processing module as the information node posterior probability likelihood ratio of current iteration;
Step 3, reading the soft value that check-node the last iteration passes to information node from the external information memory cell is the checksum update value, passes to the decoding processing module;
Step 4, bit node processing unit read out the checksum update value of the last iteration that information node posterior probability likelihood ratio and external information memory cell read, and obtain the bit updating value of information node, pass to the code check node processing unit;
Step 5, code check node processing unit are calculated the checksum update value of this iteration according to the bit updating value that passes to all information nodes of current check-node, and this checksum update value deposits the external information memory cell in;
Step 6 utilizes the 4th bit updating value and the 5th that goes on foot the information node that calculates to go on foot the checksum update value of this iteration that calculates, and the posterior probability likelihood ratio updating value of computing information node deposits shift register then in.
The present invention has following beneficial effect:
(1) decoder of the present invention is applicable to all QC class LDPC sign indicating numbers, so long as the LDPC code word of piecemeal is all supported decoding;
(2) decoder of the present invention does not have flowing water competition conflict, and it utilizes circulating register to substitute memory, has eliminated the flowing water conflict, does not need to insert the flowing water conflict idle waiting cycle, and better throughput performance is arranged, and work schedule is also simple relatively;
(3) decoder of the present invention does not need to expend the interleaving network of huge resource, has saved a lot of hardware resources, and whole decoder resource consumption is less relatively;
(4) the present invention supports to decipher degree of parallelism and can change flexibly, can select a compromise at hardware resource and throughput easily, for not needing flexibility but the application demand of minimum resource of needs or high throughput has fine applicability.
Description of drawings
Fig. 1 is the structural representation of H matrix of the QC-LDPC sign indicating number of accurate cyclic extensions method construct among the present invention;
Fig. 2 is the structural representation and the layered approach schematic diagram of the check matrix among the present invention;
Fig. 3 is circulating register schematic diagram of the present invention (is example with 4 taps);
Fig. 4 is that maximin of the present invention is searched modular structure block diagram (being input as example with 7);
Fig. 5 is the system architecture diagram of decoder of the present invention;
Fig. 6 is system's each several part network connection diagram of decoder of the present invention.
Fig. 7 is the decoding core processing module block diagram of decoder of the present invention.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
As shown in Figure 1, be existing mother matrix and the extended method thereof of degree of parallelism that use as the quasi-cyclic LDPC code that decoder adopted of k.Needing the size of the code word of structure is m*n, and then the size of corresponding mother matrix is (m/k) * (n/k), and each element in the mother matrix expands to the matrix of a k*k.In the mother matrix 0 is extended to the null matrix of a k*k; In the mother matrix 1 is extended to the cyclic shift form of the cell matrix of a k*k, and among the figure, the left side is the mother matrix schematic diagram, and the right side is certain nonzero element expansion schematic diagram in the mother matrix.
Also need mother matrix is carried out conversion after having constructed mother matrix, deciphering with decoder for decoding of the present invention can more performance.Transform method is as follows, from mother matrix second row, if same Lie Fei-1 yuan of capable non--1 element of n and 1 ~ (n-1) row have repetition, all non--1 elements of full line all add 1, till same Lie Fei-1 element of all non--1 elements and 1 ~ (n-1) row did not all have to repeat, non--1 element of each row of mother matrix after the last conversion was all different.
As shown in Figure 2, diagram is the layered approach of the alternative manner of decoder use of the present invention, the layered approach that two patents mentioning in the specification background technology are used is shown in the figure left side, capable the k of each row expansion of mother matrix as one deck, the number of plies is the mother matrix line number altogether, yet decoder layered approach of the present invention is then shown in figure the right, only get the delegation of k in capable after the every row expansion of mother matrix, the mother matrix line number is as one deck altogether, the number of plies is spreading factor k, the first behavior ground floor after for example all are expanded, the second behavior second layer ...
As shown in Figure 3, be the related circulating register structure of decoder of the present invention, circulating register is spliced by multistage and connects into annular, and a section number is the mother matrix column weight, each section output passes to the bit node processing unit, imports from the transmission of information bit processing unit.
As shown in Figure 4, be that the related minimum sub-minimum of decoder of the present invention is searched modular structure, be exemplified as the module of 7 inputs, a pair of in twos packet sequencing connects 4 then and selects 2 modules to select minimum and sub-minimum from two groups of sorted 4 numbers earlier.
As shown in Figure 5, be decoder one example structure figure of the present invention, this hierarchical block irregular low-density check code device, comprise: decoding processing module, external information memory cell, three big modules of a n circulating register, wherein decipher processing module and can be divided into bit node processing unit, code check node processing unit and three parts of information bit processing unit.
As shown in Figure 6, connect network diagram between the several modules of this present invention decoder one embodiment, wherein circulating register is table tennis, number has n (n mother matrix columns), check-node has m (m is the mother matrix line number), and each bit node processing unit and information bit processing unit all have heavy node that adds deduct of row.
In the described decoding processing module, the external information memory cell is that the checksum update value is exported to the decoding processing module with the soft value that the check-node of last iteration passes to information node.Circulating register passes to the decoding processing module with the updating value of the posterior probability likelihood ratio of information node.The decoding processing module passes to the external information memory cell with the checksum update value that passes to information node by check-node in this iteration, and the posterior probability likelihood ratio updating value of information node is passed to circulating register.
As shown in Figure 7, the decoding core processing module block diagram of described decoding processing module, comprise: the one 2 selects 1 selector 501, bit node processing unit 502, code check node processing unit 509, information bit processing unit 512, wherein: the one 2 selects 1 to select the data of 501 pairs of inputs of module to select, and the result that will select exports to the bit node processing unit.The bit updating value of bit node processing unit computing information node passes to code check node processing unit and information bit processing unit.The bit updating value of the information node that the bit node processing unit that code check node processing unit basis receives is sent here is calculated the checksum update value of this iteration, and is passed to information bit processing unit and external information memory cell 509.The checksum update value of this iteration that bit updating value that the information bit processing unit transmits according to the bit node processing unit and code check node processing unit transmit is come computing information node posterior probability likelihood ratio updating value, exports to circulating register 515.
Described decoding processing module, it is as follows that it carries out flow process:
(1) selects the input data
The one 2 selects the data of 501 pairs of inputs of 1 selector to select.If this information node participates in decoding for the first time in decode procedure, then select the circulating register 514 or 515 of firm stores information of channels, otherwise the information node posterior probability likelihood ratio of reading in selection another one circulating register 514 or 515.The one 2 selects the output llrSum of 1 selector 501 to pass to the bit node processing unit.
(2) the bit updating value of computing information node
As shown in Figure 5, the bit node processing unit comprises subtracter 502, the first complement code converter 503 and the first cut position arithmetic unit 504, the checksum update value llr2MsgOld of the last iteration of reading from the external information memory cell passes to subtracter 502, subtracter 502 selects the output llrSum of 1 selector 501 and checksum update value llr2MsgOld to subtract each other with the 1, obtain the information updating value llrNewTmp of information node, the checksum update value reads according to tick lables and selects minimum or sub-minimum.LlrNewTmp passes to the first complement code transducer 503, the digital translation of complement form is become the digital llrNewUnsigned of sign bit-absolute value form.Become big situation owing to may occur data bit width in the process that adds up, therefore the output of the first complement code transducer 503 need be sent to the first cut position arithmetic unit 504, bit wide is renamed as original predetermined size.The bit updating value llr2Check that the first cut position arithmetic unit 504 comes out sends into the code check node processing unit.
(3) the calculation check node passes to the checksum update value of information node
As shown in Figure 5, the check-node information updating module comprises: minimum sub-minimum is searched module and correcting module.Minimum sub-minimum is searched module and is made up of some comparators, structure such as Fig. 4, and correcting module is 3 adders formations of the property taken advantage of correction use.The operation of code check node processing unit is divided into following a few step again:
1. calculate the minimum value and the sub-minimum of the bit updating value of all information nodes that link to each other with current check-node.(present embodiment adopts the LMMSA algorithm, so minimum value and sub-minimum in the bit updating value that needs calculate with current check-node links to each other.）
Directly use one to be connected to each other by many comparators that the minimum time little module that forms 505 is disposable to be found out minimum and sub-minimum and write down this selections minimum or inferior little with row anharmonic ratio spy.
2. the property taken advantage of correction
Minimum time little module 505 outputs are directly inputted to the property taken advantage of correction in the multiplier 506, are about to it and multiply by a coefficient alpha, send into the second cut position arithmetic unit 507 through the output after the multiplier.The Alpha value obtains by LDPC sign indicating number common simulation platform scanner coefficient alpha emulation, and coefficient alpha is that near 0.8 performance is best, can get a value during realization near 0.8, and not emulation again.
3. cut position computing
The bit wide of the information of coming out from multiplier 506 is bigger than the bit wide of checksum update value, so before entering the second complement code transducer 508, need adjust the bit wide that this value is carried out, is adjusted into the bit wide of checksum update value by the second cut position arithmetic unit 507.
4. number format conversion
The second complement code transducer 508 is sent in the output of the second cut position arithmetic unit 507, is the digital llr2Msg of complement form with the digital translation of sign bit-absolute value form.
5. the calculation check node passes to the updating value of information node
Select the minimum still time little updating value that passes to information node as check-node according to the position bit sign.
At last, the checksum update value of this iteration deposits external information memory cell 401 in.
(3) computing information node posterior probability likelihood ratio updating value
As shown in Figure 5, information node posterior probability likelihood ratio update module comprises buffer 510, the 3rd complement code transducer 511 and adder 512.Buffer 510 is in bit updating value llr2Check several cycles of buffer delay, and the data Q that comes out from buffer 510 enters the 3rd complement code transducer 511, is converted into complement form llrNew by symbol-absolute value shape, sends into adder 512.Another input of adder 512 is checksum update value llr2Msg, and two values are subtracted each other, and obtains information node posterior probability likelihood ratio updating value llrSumNew.The sign bit of llrSumNew just is declares the result firmly, deposits the circulating register 514 or 515 of table tennis simultaneously in.
When adopt the present embodiment system to a code length be 8064, code check is 1/2 non-rule low density checkout code, to decipher this sign indicating number now, spreading factor 96, the number of plies is 96, promptly the number of submatrix is 96.The characteristics of this non-rule low density checkout code are that all row heavily are 7.Concrete decode procedure may further comprise the steps:
Step 1, receiving channel information, channel information will be by 8064/96=84 the submodule that be divided into of order, corresponding 84 circulating registers, the circulating register of table tennis will have one to be used to the stores information of channels that is shifted, another is used for the iterative decoding use, and exchange interaction is rattled and used then.
Step 2, the one 2 selects 1 to select module 501 can select to be used for the circulating register of iterative decoding, and selection result llrSum is sent into the decoding processing module;
Step 3, the checksum update value llr2MsgOld and the information node posterior probability likelihood ratio llrSum of the last iteration of reading from external information memory cell 509 subtract each other the information as llr, carry out complement code conversion and cut position, obtain absolute value and symbol;
Step 4, in processing procedure, the decoding processing module at first obtains the bit updating value llr2Check of information node.Obtaining this iteration check-node according to the bit updating value llr2Check of information node passes to the checksum update value llr2Msg of information node and deposits external information memory cell 509 in.Then, the decoding processing module obtains information node posterior probability likelihood ratio updating value llrSumNew according to the bit updating value llr2Check of information node with the checksum update value llr2Msg that this iteration check-node passes to information node, deposits circulating register in.Enter next iteration after so having finished an iteration.And the like, finish up to iteration.
The checksum update value llr2MsgOld and the information node posterior probability likelihood ratio llrSum that enter the last iteration of decoding processing module subtract each other as two inputs of subtracter 502, obtain the information updating value llrNewTmp of information node.LlrNewTmp is passed to the first complement code transducer 503, the digital translation of complement form is become the digital llrNewUnsigned of sign bit-absolute value form.The output of the first complement code transducer 503 is sent to the first cut position arithmetic unit 504.The data llr2Check that the first cut position arithmetic unit 504 comes out deposits in the buffer 510 in order.Simultaneously, bit updating value llr2Check passes to minimum sub-minimum module.Step 5, in the code check node processing unit, minimum little module 505 selected minimum and sub-minimum from correspondence with 7 llr2Check of delegation, be input to the property taken advantage of correction in the multiplier 506, promptly multiply by 0.8125, the bit wide of the information of coming out from multiplier 506 is bigger than the bit wide of the updating value of check-node, so before entering the second complement code transducer 508, need adjust the bit wide that this value is carried out, be adjusted into the bit wide of check-node by the second cut position arithmetic unit 507.The second complement code transducer 508 is sent in the output of the second cut position arithmetic unit 507, with the digital translation of sign bit-absolute value form is the digital llr2Msg of complement form, the ascend the throne updating value of check-node of the information llr2Msg that comes out from the second complement code converter 508 deposits external information memory cell 509 in.
Step 6, the Q that comes out from buffer 510 enters the 3rd complement code transducer 511, is converted into complement form llrNew by symbol-absolute value shape, sends into adder 512.Another input of adder 512 is checksum update value llr2Msg, and two values are subtracted each other, and obtains information node posterior probability likelihood ratio updating value llrSumNew.The sign bit of llrSumNew just is declares the result firmly, deposits circulating register afterwards in.
Step 7, circulation or iteration finish next time.
In the present embodiment, do not have flowing water competition conflict, it utilizes circulating register to substitute memory, has eliminated the flowing water conflict, does not need to insert the flowing water conflict idle waiting cycle, and better throughput performance is arranged, and work schedule is also simple relatively; Do not need to expend the interleaving network of huge resource, saved a lot of hardware resources, whole decoder resource consumption is less relatively.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be conspicuous.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. hierarchical block irregular low-density check code device, comprise: decoding processing module, external information memory cell, circulating register, it is characterized in that, the posterior probability likelihood ratio of using circulating register to come the stored information node, use minimum sub-minimum to search disposable output minimum of module and sub-minimum, decoding iterative process layered approach, respectively get delegation as one deck in the k that layered approach adopts mother matrix to expand is capable, each layer decoding quantity is a mother matrix, the number of plies cyclic extensions factor that is as the criterion; Wherein:
The external information memory cell is that the checksum update value is exported to the decoding processing module with the soft value that the check-node of last iteration passes to information node, and the check updating value in this iteration of transmitting of storage decoding processing module;
Circulating register passes to the decoding processing module with the posterior probability likelihood ratio of information node, and the posterior probability likelihood ratio updating value of the information node that transmits of storage decoding processing module;
The decoding processing module passes to the external information memory cell with the checksum update value that passes to information node by check-node in this iteration, and the posterior probability likelihood ratio updating value of information node is passed to circulating register through decoding processing module interleaving network.
2. hierarchical block irregular low-density check code device according to claim 1, it is characterized in that, described decoding processing module comprises: the one 2 selects 1 selector, bit node processing unit, code check node processing unit, information bit processing unit, wherein:
The one 2 selects 1 selector to select between the channel information and the information node posterior probability likelihood ratio of reading from circulating register, and the result that will select exports to the bit node processing unit;
The bit updating value of bit node processing unit computing information node passes to code check node processing unit and information bit processing unit;
The bit updating value of the information node that the bit node processing unit that code check node processing unit basis receives is sent here is calculated the checksum update value of this iteration, and is passed to information bit processing unit and external information memory cell;
The checksum update value of this iteration that bit updating value that the information bit processing unit transmits according to the bit node processing unit and code check node processing unit transmit is come computing information node posterior probability likelihood ratio updating value, and exports to circulating register through decoding processing module interleaving network.
3. hierarchical block irregular low-density check code device according to claim 2 is characterized in that, described bit node processing unit comprises: subtracter, the first complement code transducer and the first cut position arithmetic unit, wherein:
Subtracter subtracts each other the checksum update value of the last iteration that first information node posterior probability likelihood ratio and external information memory cell are read, and obtains the information updating value of information node, passes to the first complement code transducer;
The first complement code transducer is converted to the numeral of sign bit-absolute value form with the information updating value of information node, and is transferred to the first cut position arithmetic unit;
The first cut position arithmetic unit carries out the cut position operation to the dateout of the first complement code transducer, bit wide is become the bit wide of original information node information of being scheduled to, become big situation to avoid in the process that adds up, occurring data bit width, promptly obtain the bit updating value of information node.
4. hierarchical block irregular low-density check code device according to claim 2 is characterized in that, described code check node processing unit comprises: minimum is inferior searches module, multiplier, the second cut position arithmetic unit and the second complement code transducer for a short time, wherein:
For a short time search the information that module transmits from the bit node processing unit for minimum time and find out minimum value and sub-minimum, so that the further property taken advantage of correcting process is saved in the external information memory cell;
Multiplier multiply by a constant with minimum inferior output of searching module for a short time, this constant obtains by software emulation, the output of multiplier is again by the second cut position arithmetic unit, the bit wide of verification updating value is retrained within the specific limits, again through the second complement code transducer, obtain the checksum update value of final this iteration afterwards.
5. hierarchical block irregular low-density check code device according to claim 4 is characterized in that, described minimum time searches for a short time that module is made up of many four inputs, two output junior units and junior units are exported in two inputs two;
Two nodal informations of described two inputs, two output junior units inputs are output as and arrange good former state data by size, and effect is that two numbers are sorted, and is made of selector;
Four inputs of described four inputs, two output junior units are four outputs of two two inputs, two outputs or other two each and every one four inputs, two outputs, and effect is minimum and the sub-minimum selected inside two groups of input data that sequence size in four.
6. hierarchical block irregular low-density check code device according to claim 2 is characterized in that, described information bit processing unit comprises: buffer, the 3rd complement code transducer, adder, wherein:
Buffer is used to deposit the bit updating value of the information node that the bit node processing unit transmits, and its length equals the number of the information node that links to each other with current check-node, and the row that promptly equals the corresponding current check-node of check matrix is heavy;
The buffer that the 3rd complement code transducer receives in the code check node processing unit transmits data, and the data of symbol-absolute value form are converted to complement form;
The checksum update value addition of this iteration that adder transmits the output and the code check node processing unit of the 3rd complement code transducer obtains information node posterior probability likelihood ratio updating value, passes to the decoding circulating register.
7. hierarchical block irregular low-density check code device according to claim 1, it is characterized in that, described external information memory cell uses memory to realize, the memory number is the check-node number, data bit width is that the data bit width twice of external information adds up anharmonic ratio spy, storage maximum, minimum value and minimum value position, storage depth is the mother matrix spreading factor;
Described circulating register number has the bit node number, and each circulating register input and output tap number is the column weight of bit node corresponding to mother matrix.
8. a kind of hierarchical block irregular low-density check code method according to claim 1 is characterized in that, may further comprise the steps:
Step 1, the input data that obtain decoder are channel value;
Step 2, selector is selected the input data of information node posterior probability likelihood ratio, if this information node participates in decoding for the first time in decode procedure, the shift register of then selecting firm input channel information is as information node posterior probability likelihood ratio, otherwise the data of reading from the another one circulating register pass to the decoding processing module as the information node posterior probability likelihood ratio of current iteration;
Step 3, reading the soft value that check-node the last iteration passes to information node from the external information memory cell is the checksum update value, passes to the decoding processing module;
Step 4, bit node processing unit read out the checksum update value of the last iteration that information node posterior probability likelihood ratio and external information memory cell read, and obtain the bit updating value of information node, pass to the code check node processing unit;
Step 5, code check node processing unit are calculated the checksum update value of this iteration according to the bit updating value that passes to all information nodes of current check-node, and this checksum update value deposits the external information memory cell in;
Step 6 utilizes the 4th bit updating value and the 5th that goes on foot the information node that calculates to go on foot the checksum update value of this iteration that calculates, and the posterior probability likelihood ratio updating value of computing information node deposits shift register then in.
9. a kind of hierarchical block irregular low-density check code method according to claim 8, it is characterized in that, described decoding iterative process layered approach, respectively get delegation as one deck in the k that layered approach adopts mother matrix to expand is capable, each layer decoding quantity is a mother matrix, the number of plies cyclic extensions factor that is as the criterion does not need interleaving network, does not have the flowing water conflict.
10. hierarchical block irregular low-density check code processing method according to claim 8, it is characterized in that, the posterior probability likelihood ratio of described circulating register stored information node, each time in each layer decoding iteration, circulating register content displacement once, data but also import down one piece of data the last period had not only been exported in several sections junctions of a shift register loop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110215391 CN102281125B (en) | 2011-07-29 | 2011-07-29 | Laminated and partitioned irregular low density parity check (LDPC) code decoder and decoding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110215391 CN102281125B (en) | 2011-07-29 | 2011-07-29 | Laminated and partitioned irregular low density parity check (LDPC) code decoder and decoding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102281125A true CN102281125A (en) | 2011-12-14 |
| CN102281125B CN102281125B (en) | 2013-07-17 |
Family
ID=45106326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110215391 Active CN102281125B (en) | 2011-07-29 | 2011-07-29 | Laminated and partitioned irregular low density parity check (LDPC) code decoder and decoding method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102281125B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103384153A (en) * | 2013-07-03 | 2013-11-06 | 清华大学 | Method and system for decoding quasi-cyclic LDPC (low-density parity check) codes |
| CN104052495A (en) * | 2013-03-15 | 2014-09-17 | 翁咏禄 | Low density parity check code hierarchical decoding architecture for reducing hardware buffer |
| CN103929188B (en) * | 2014-04-22 | 2017-03-08 | 北京经纬恒润科技有限公司 | A kind of interpretation method, apparatus and system |
| CN106911337A (en) * | 2017-01-23 | 2017-06-30 | 北京联想核芯科技有限公司 | Data processing method, device and decoder |
| CN107294541A (en) * | 2016-04-11 | 2017-10-24 | 清华大学 | Low area overhead from fault-tolerant ldpc decoder |
| CN109309502A (en) * | 2018-08-03 | 2019-02-05 | 西安电子科技大学 | The layering LDPC basic matrix of 5G NR standard handles interpretation method |
| CN109495115A (en) * | 2018-11-01 | 2019-03-19 | 哈尔滨工业大学 | A kind of ldpc decoder and interpretation method based on FPGA |
| CN111224673A (en) * | 2018-11-26 | 2020-06-02 | 中兴通讯股份有限公司 | Decoding method, device and decoder |
| CN111384970A (en) * | 2018-12-29 | 2020-07-07 | 电信科学技术研究院有限公司 | Decoding method, device and communication equipment |
| CN111404555A (en) * | 2020-02-16 | 2020-07-10 | 西安电子科技大学 | Cyclic shift network control method, system, storage medium and decoder |
| CN112242851A (en) * | 2020-11-23 | 2021-01-19 | 湖南国科锐承电子科技有限公司 | Iterative data processing method in layered decoding of LDPC code and decoder system |
| CN112636767A (en) * | 2020-12-03 | 2021-04-09 | 重庆邮电大学 | Layered semi-parallel LDPC decoder system with single replacement network |
| CN113590377A (en) * | 2021-07-16 | 2021-11-02 | 深圳宏芯宇电子股份有限公司 | Decoding device, decoding method, storage medium and computer equipment |
| CN114124110A (en) * | 2021-11-29 | 2022-03-01 | 北京思朗科技有限责任公司 | LDPC layered decoding method and LDPC decoder |
| CN114553242A (en) * | 2022-03-04 | 2022-05-27 | 电子科技大学 | Partial parallel LDPC decoder based on semi-probability calculation |
| CN116827358A (en) * | 2023-07-13 | 2023-09-29 | 白盒子(上海)微电子科技有限公司 | 5G LDPC coding realization method and device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040187129A1 (en) * | 2003-02-26 | 2004-09-23 | Tom Richardson | Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation |
| US7181676B2 (en) * | 2004-07-19 | 2007-02-20 | Texas Instruments Incorporated | Layered decoding approach for low density parity check (LDPC) codes |
| CN101106381A (en) * | 2007-08-09 | 2008-01-16 | 上海交通大学 | Hierarchical low density check code decoder and decoding processing method |
| CN101262231A (en) * | 2008-04-25 | 2008-09-10 | 浙江大学 | A decoding method for block low-density check code and reconstruction of multi-mode decoder |
| CN101355406A (en) * | 2008-09-18 | 2009-01-28 | 上海交通大学 | Decoder for layered non-rule low density checkout code and method for processing decode |
| US20100037121A1 (en) * | 2008-08-05 | 2010-02-11 | The Hong Kong University Of Science And Technology | Low power layered decoding for low density parity check decoders |
| CN101895375A (en) * | 2010-07-28 | 2010-11-24 | 上海交通大学 | Decoding system of low-density parity-check code |
-
2011
- 2011-07-29 CN CN 201110215391 patent/CN102281125B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040187129A1 (en) * | 2003-02-26 | 2004-09-23 | Tom Richardson | Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation |
| US7181676B2 (en) * | 2004-07-19 | 2007-02-20 | Texas Instruments Incorporated | Layered decoding approach for low density parity check (LDPC) codes |
| CN101106381A (en) * | 2007-08-09 | 2008-01-16 | 上海交通大学 | Hierarchical low density check code decoder and decoding processing method |
| CN101262231A (en) * | 2008-04-25 | 2008-09-10 | 浙江大学 | A decoding method for block low-density check code and reconstruction of multi-mode decoder |
| US20100037121A1 (en) * | 2008-08-05 | 2010-02-11 | The Hong Kong University Of Science And Technology | Low power layered decoding for low density parity check decoders |
| CN101355406A (en) * | 2008-09-18 | 2009-01-28 | 上海交通大学 | Decoder for layered non-rule low density checkout code and method for processing decode |
| CN101895375A (en) * | 2010-07-28 | 2010-11-24 | 上海交通大学 | Decoding system of low-density parity-check code |
Non-Patent Citations (1)
| Title |
|---|
| 陈徐薇,甘小莺,俞晖,华颖,徐友云: "非规则低密度奇偶校验码译码器", 《上海交通大学学报》 * |
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104052495A (en) * | 2013-03-15 | 2014-09-17 | 翁咏禄 | Low density parity check code hierarchical decoding architecture for reducing hardware buffer |
| CN104052495B (en) * | 2013-03-15 | 2018-09-21 | 翁咏禄 | Low density parity check code hierarchical decoding architecture for reducing hardware buffer |
| CN103384153B (en) * | 2013-07-03 | 2016-05-18 | 清华大学 | Quasi-cyclic LDPC code coding method and system |
| CN103384153A (en) * | 2013-07-03 | 2013-11-06 | 清华大学 | Method and system for decoding quasi-cyclic LDPC (low-density parity check) codes |
| CN103929188B (en) * | 2014-04-22 | 2017-03-08 | 北京经纬恒润科技有限公司 | A kind of interpretation method, apparatus and system |
| CN107294541B (en) * | 2016-04-11 | 2020-07-10 | 清华大学 | Low area overhead self-fault-tolerant L DPC decoder |
| CN107294541A (en) * | 2016-04-11 | 2017-10-24 | 清华大学 | Low area overhead from fault-tolerant ldpc decoder |
| CN106911337A (en) * | 2017-01-23 | 2017-06-30 | 北京联想核芯科技有限公司 | Data processing method, device and decoder |
| CN109309502A (en) * | 2018-08-03 | 2019-02-05 | 西安电子科技大学 | The layering LDPC basic matrix of 5G NR standard handles interpretation method |
| CN109495115B (en) * | 2018-11-01 | 2022-08-09 | 哈尔滨工业大学 | LDPC decoder based on FPGA and decoding method |
| CN109495115A (en) * | 2018-11-01 | 2019-03-19 | 哈尔滨工业大学 | A kind of ldpc decoder and interpretation method based on FPGA |
| CN111224673A (en) * | 2018-11-26 | 2020-06-02 | 中兴通讯股份有限公司 | Decoding method, device and decoder |
| CN111224673B (en) * | 2018-11-26 | 2024-10-11 | 中兴通讯股份有限公司 | Decoding method, device and decoder |
| CN111384970A (en) * | 2018-12-29 | 2020-07-07 | 电信科学技术研究院有限公司 | Decoding method, device and communication equipment |
| CN111404555B (en) * | 2020-02-16 | 2023-12-19 | 西安电子科技大学 | Cyclic shift network control method, system, storage medium and decoder |
| CN111404555A (en) * | 2020-02-16 | 2020-07-10 | 西安电子科技大学 | Cyclic shift network control method, system, storage medium and decoder |
| CN112242851A (en) * | 2020-11-23 | 2021-01-19 | 湖南国科锐承电子科技有限公司 | Iterative data processing method in layered decoding of LDPC code and decoder system |
| CN112242851B (en) * | 2020-11-23 | 2024-03-19 | 湖南国科锐承电子科技有限公司 | Iterative data processing method and decoder system in layered decoding of LDPC code |
| CN112636767A (en) * | 2020-12-03 | 2021-04-09 | 重庆邮电大学 | Layered semi-parallel LDPC decoder system with single replacement network |
| CN112636767B (en) * | 2020-12-03 | 2023-04-07 | 重庆邮电大学 | Layered semi-parallel LDPC decoder system with single replacement network |
| CN113590377A (en) * | 2021-07-16 | 2021-11-02 | 深圳宏芯宇电子股份有限公司 | Decoding device, decoding method, storage medium and computer equipment |
| CN114124110A (en) * | 2021-11-29 | 2022-03-01 | 北京思朗科技有限责任公司 | LDPC layered decoding method and LDPC decoder |
| CN114553242A (en) * | 2022-03-04 | 2022-05-27 | 电子科技大学 | Partial parallel LDPC decoder based on semi-probability calculation |
| CN114553242B (en) * | 2022-03-04 | 2023-04-25 | 电子科技大学 | Partial parallel LDPC decoder based on semi-probability calculation |
| CN116827358A (en) * | 2023-07-13 | 2023-09-29 | 白盒子(上海)微电子科技有限公司 | 5G LDPC coding realization method and device |
| CN116827358B (en) * | 2023-07-13 | 2024-04-02 | 白盒子(上海)微电子科技有限公司 | 5G LDPC coding realization method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102281125B (en) | 2013-07-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102281125B (en) | Laminated and partitioned irregular low density parity check (LDPC) code decoder and decoding method | |
| CN101355406B (en) | Decoder for layered non-rule low density checkout code and method for processing decode | |
| CN101106381B (en) | Hierarchical low density check code decoder and decoding processing method | |
| CN111162797B (en) | Encoding device and encoding method of rate compatible 5G LDPC code | |
| CN102394661B (en) | LDPC (low density parity check) decoder and decoding method based on layer decoding processing | |
| CN102075198B (en) | Quasi-cyclic low-density parity check convolution code coding-decoding system and coding-decoding method thereof | |
| CN101800559B (en) | High-speed configurable QC-LDPC code decoder based on TDMP | |
| CN112636767B (en) | Layered semi-parallel LDPC decoder system with single replacement network | |
| CN103220002B (en) | A kind of quasi-cyclic LDPC code constructing method eliminating decoder access conflict | |
| CN109802687A (en) | A kind of high speed code-rate-compatible LDPC encoder of the QC-LDPC code based on FPGA | |
| CN111162795B (en) | LDPC coding hardware implementation method based on check sub-matrix segmentation | |
| CN100578945C (en) | Decoder device for LDPC code, and decoding method | |
| Pourjabar et al. | A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio | |
| CN105515588B (en) | A kind of LDPC CC high speed decoders | |
| CN107707261A (en) | A kind of building method of the LDPC check matrix based on protograph | |
| CN100557983C (en) | A kind of quasi-cyclic low-density parity check codes encoder and check digit generation method | |
| CN101895375B (en) | Decoding system of low-density parity-check code | |
| US20140122979A1 (en) | Hardware Architecture and Implementation of Low Power Layered Multi-Level LDPC Decoder | |
| CN116192157A (en) | Implementation method for reducing QC-LDPC code generation matrix density | |
| CN100593911C (en) | Method and system for decoding the layer data received by communication system | |
| CN102611462A (en) | LDPC-CC (Low-Density Parity-Check Convolution Codes) decoding algorithm and decoder | |
| CN115580309A (en) | LDPC decoder for improving decoding efficiency and throughput of decoder | |
| CN110958025B (en) | Short frame length coding and decoding method based on superposition | |
| Ajaz et al. | Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11 ad applications | |
| Gong et al. | A Reusable and Efficient Architecture for QC-LDPC Encoder With Less Expansion Factors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20160206 Address after: 200120 Shanghai, Pudong New Area, east of the three lane road, No. 1018, 1-2 floor, 3 Patentee after: Shanghai NERC-DTV National Engineering Research Center Co., Ltd. Address before: 200240 Minhang District, Shanghai, Dongchuan Road, No. 800, No. Patentee before: Shanghai Jiao Tong University |