CN102281125A - Laminated and partitioned irregular low density parity check (LDPC) code decoder and decoding method - Google Patents

Abstract

The invention discloses a layered block irregular low-density check code decoder and a decoding method in the field of communication technology , wherein: the external information storage unit transfers the check node of the last iteration to the soft value output of the information node to the decoding processing module. The cyclic shift register transmits the update value of the posterior probability likelihood ratio of the information node to the decoding processing module. The decoding processing module transmits the check update value in this iteration to the external information storage unit, and at the same time transmits the update value of the posterior probability likelihood ratio of the information node to the circular shift register through the interleaving network of the decoding processing module. The present invention is applicable to decoding of all QC LDPC codes, as long as the block LDPC codewords support decoding; there is no pipeline competition conflict, good throughput performance, and relatively simple working sequence; no need to consume huge resources The interleaved network saves a lot of hardware resources, and the resource consumption of the entire decoder is relatively small. The degree of parallelism in support of decoding can be changed flexibly.

Description

Hierarchical Block Irregular Low Density Check Code Decoder and Decoding Method

technical field

The invention relates to a decoder and a decoding method in the field of communication technology, in particular to a layered block irregular low-density check code decoder and a decoding method.

Background technique

Low Density Parity Check Codes (Low Density Parity Check Codes, LDPC Codes) is a coding technology first proposed by Gallager in 1963. It has performance close to the Shannon limit. It has become a research hotspot in the field of coding and is widely used in various Standards in the field of wireless communication include my country's digital TV terrestrial transmission standard, the European second-generation satellite digital video broadcasting standard, IEEE 802.11n, IEEE 802.16e, etc. In the current wireless communication, people pay more and more attention to the communication of high data rate, so the LDPC decoder with simple structure and high throughput has always been the research focus of LDPC codes. In addition, in practical applications, codes with different code lengths and code rates need to be used for transmission according to different information to be transmitted and different channel conditions. Therefore, an LDPC decoder structure that can support a certain scale of code length to obtain sufficient error correction capability is also one of the key points to be considered in the design of the decoder structure. In order to support large code lengths, resource consumption is usually very large. Due to current technical limitations, FPGA resources are limited, and LDPC code decoders with low resource consumption are also important research content. The structure of LDPC code decoder has three forms: serial structure, full parallel structure and partial parallel structure. Partially parallel LDPC decoders are widely used because of their moderate complexity and hardware resource consumption. In addition, for LDPC decoders, different algorithms, such as belief propagation algorithm, minimum sum algorithm, minimum sum algorithm with modification, layered belief propagation algorithm, layered minimum sum algorithm with modification, etc., will affect LDPC decoding The structure of the decoder affects all aspects of the decoder at the same time, including throughput, performance, resource usage, etc.

After searching the literature of the prior art, it is found that the Chinese patent application number is 200710044708, and the patent name is "layered low-density check code decoder and decoding processing method", which proposes a method based on the modified minimum A low-density check code decoder of sum algorithm, the decoder is mainly composed of a processing module, an external information storage unit, a second storage unit, a first interleaving network, and a second interleaving network. The decoder requires two interleaving networks, and due to the structural characteristics of the interleaving networks, the decoder consumes more hardware resources. And the Chinese patent with the patent application number 200810200033, the patent name is "layered irregular low-density check code decoder and decoding processing method", which further improves the previous patent, removes an interleaving network, and adds iteration termination module. These two decoder systems have an interleaving network, which consumes huge resources, and there are inevitably pipeline conflicts, which need to insert idle pipeline waiting periods, which greatly affects the decoding throughput. In addition, the LE resource consumption of the two decoders is different from that of The expansion factor of QC-LDPC is directly proportional, and QC-LDPC with a larger code length for a larger expansion factor cannot be accommodated in a general FPGA.

Contents of the invention

Aiming at the deficiencies of the prior art, the present invention proposes a layered block irregular low-density check code decoder and a decoding method. The improved decoder structure does not require an interleaving network, which saves hardware resource consumption and has a lot of advantages. Small resource consumption, no pipeline conflict problem, good throughput performance, can support QC-LDPC codes with large expansion factors, support decoding of all QC-LDPC codes, and support decoding of multiple expansion factors. Supplements the deficiencies of the first two decoders.

The present invention is achieved through the following technical solutions:

The invention relates to a layered block irregular low-density check code decoder, comprising: an external information storage unit, a cyclic shift register, and a decoding processing module, wherein:

The external information storage unit outputs the soft value of the check node of the last iteration to the information node, that is, the check update value, to the decoding processing module, and stores the check update value in this iteration transmitted by the decoding processing module;

There are a total of N cyclic shift registers, N is the number of columns of the code letter matrix, and the posterior probability likelihood ratio of the information node is passed to the decoding processing module, and the posterior probability of the information node transmitted by the decoding processing module is stored Likelihood ratio update value;

The decoding processing module transfers the check update value passed from the check node to the information node in this iteration to the external information storage unit, which is jointly completed by the bit node processing unit and the check node processing unit, and the a posteriori of the information node The update value of the probability likelihood ratio is transmitted to the circular shift register, which is jointly completed by the bit node processing unit and the information bit processing unit.

The external information storage unit is implemented using memory, the number of memory is the number of check nodes, the data bit width is twice the data bit width of the external information plus the row weight bit, and the maximum, minimum and minimum value positions are stored, and the storage depth is is the mother matrix expansion factor.

The cyclic shift registers have a total number of bit nodes, and the number of input and output taps of each cyclic shift register is the bit node corresponding to the column weight of the parent matrix.

The decoding processing module includes: a first 2-to-1 selector, a bit node processing unit, a check node processing unit, and an information bit processing unit, wherein:

The first 2-to-1 selector selects the input data, selects between the channel information and the posterior probability likelihood ratio of the information node read from the cyclic shift register, and outputs the selected result to the bit node processing unit;

The bit node processing unit has a corresponding number of row weights for each row of the mother matrix, calculates the bit update value of the information node, and passes it to the check node processing unit and the information bit processing unit;

The number of check node processing units is M, and M is the number of rows of the code letter matrix. According to the bit update value of the information node sent by the received bit node processing unit, the check update value of this iteration is calculated and passed to Information bit processing unit and external information storage unit;

The information bit processing unit calculates the update value of the information node posterior probability likelihood ratio according to the bit update value sent by the bit node processing unit and the check update value of this iteration sent by the check node processing unit, and outputs it to the cyclic shift register.

The bit node processing unit includes: a subtractor, a first complement converter and a first truncation operator, wherein:

The subtractor subtracts the posterior probability likelihood ratio of the first information node from the check update value of the last iteration read by the external information storage unit to obtain the information update value of the information node, which is passed to the first complement converter;

The first complement code converter converts the information update value of the information node into a number in the form of sign bit-absolute value, and transmits it to the first truncation operator;

The first truncation operator performs a truncation operation on the output data of the first complement code converter, and changes the bit width to the bit width of the originally predetermined information node information, so as to avoid possible changes in the data bit width during the accumulation process In a large case, the bit update value of the information node is obtained.

The check node processing unit includes: a minimum second smallest search module, a multiplier, a second truncation operator and a second complement converter, wherein:

The minimum sub-minimum search module finds the minimum value and the sub-minimum value from the information transmitted by the bit node processing unit for further multiplicative correction processing and saves them in the external information storage unit.

The multiplier multiplies the output of the smallest second-smallest search module by a constant, and the output of the multiplier passes through the second truncation operator to constrain the bit width of the check update value within a certain range, and then undergoes second complement conversion device to get the final verification update value of this iteration.

The smallest second-smallest search module is composed of many four-input two-output small units and two-input two-output small units, wherein:

The two-input-two-output small unit inputs two node information, and the output is the original data arranged according to the size. The function is to sort the two numbers, which is composed of selectors;

The four inputs of the four-input two-output small unit are two two-input two-output or two other four-input two-output four outputs. second minimum value;

The information bit processing unit includes: a buffer, a third complement converter, and an adder, wherein:

The buffer is used to store the bit update value of the information node transmitted by the bit node processing unit, and its length is equal to the number of information nodes connected to the current check node (that is, equal to the row weight of the check matrix corresponding to the current check node);

The third complement code converter receives the data transmitted from the buffer in the check node processing unit, and converts the data in the sign-absolute value form into a complement form;

The adder adds the output of the third complement converter and the check update value of this iteration transmitted by the check node processing unit to obtain the updated value of the posterior probability likelihood ratio of the information node, which is passed to the decoding cyclic shift register.

The present invention relates to a layered block irregular low-density check code decoding method, comprising the following steps:

Step 1, obtaining the input data (channel value) of the decoder;

Step 2. The selector selects the input data of the posterior probability likelihood ratio of the information node. If the information node participates in the decoding for the first time in the decoding process, the shift register that has just input the channel information is selected as the post-information node. Posterior probability likelihood ratio, otherwise the data read from another cyclic shift register is passed to the decoding processing module as the posterior probability likelihood ratio of the information node of the current iteration;

Step 3, read the soft value passed from the check node to the information node in the last iteration from the external information storage unit, that is, the check update value, and pass it to the decoding processing module;

Step 4, the bit node processing unit reads the posterior probability likelihood ratio of the information node and the check update value of the last iteration read by the external information storage unit, obtains the bit update value of the information node, and passes it to the check node processing unit ;

Step 5, the check node processing unit calculates the check update value of this iteration according to the bit update values of all information nodes passed to the current check node, and the check update value is stored in the external information storage unit;

Step 6: Use the bit update value of the information node calculated in the fourth step and the check update value of this iteration calculated in the fifth step to calculate the update value of the posterior probability likelihood ratio of the information node, and then store it in the shift register.

The present invention has following beneficial effect:

(1) The decoder of the present invention is applicable to all QC LDPC codes, as long as it is a block LDPC codeword, it supports decoding;

(2) The decoder of the present invention has no pipeline contention conflicts, it uses circular shift registers instead of memory, eliminates pipeline conflicts, does not need to insert pipeline conflict idle waiting periods, has better throughput performance, and the working sequence is relatively simple;

(3) The decoder of the present invention does not require an interleaving network that consumes huge resources, which saves a lot of hardware resources, and the resource consumption of the entire decoder is relatively small;

(4) The present invention supports that the degree of decoding parallelism can be flexibly changed, and it is convenient to choose a compromise between hardware resources and throughput rate, which is very suitable for application requirements that do not require flexibility but require extremely small resources or extremely high throughput rates sex.

Description of drawings

Fig. 1 is the structural representation of the H matrix of the QC-LDPC code that quasi-cyclic extension method constructs in the present invention;

Fig. 2 is a schematic structural diagram and a schematic diagram of a hierarchical method of a parity check matrix in the present invention;

Fig. 3 is a schematic diagram of the circular shift register of the present invention (taking 4 taps as an example);

Fig. 4 is a structural block diagram of the maximum and minimum value search module of the present invention (taking 7 inputs as an example);

Fig. 5 is the system structural block diagram of decoder of the present invention;

Fig. 6 is a schematic diagram of the network connection of various parts of the system of the decoder of the present invention.

Fig. 7 is a block diagram of the decoding core processing module of the decoder of the present invention.

Detailed ways

The embodiments of the present invention are described in detail below in conjunction with the accompanying drawings: this embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operating procedures are provided, but the protection scope of the present invention is not limited to the following the described embodiment.

As shown in FIG. 1 , it is the mother matrix of the quasi-cyclic LDPC code adopted by a decoder with a degree of parallelism k and its extension method. The size of the codeword to be constructed is m*n, and the size of the corresponding mother matrix is (m/k)*(n/k), and each element in the mother matrix is expanded into a k*k matrix. The 0 in the mother matrix is expanded into a k*k zero matrix; the 1 in the mother matrix is expanded into a cyclic shift form of a k*k unit matrix. In the figure, the left side is the mother matrix diagram, and the right side is the mother matrix Schematic diagram of the expansion of a non-zero element in .

After the mother matrix is constructed, it is necessary to transform the mother matrix, and decoding with the decoder of the present invention can achieve better performance. The transformation method is as follows, starting from the second row of the mother matrix, if the non-1 element in the nth row is repeated with the non-1 element in the same column of the 1~(n-1) row, all non-1 elements in the entire row will be added with 1, Until all the non-1 elements are not repeated with the non-1 elements in the same column of rows 1~(n-1), the non-1 elements in each column of the transformed mother matrix are different.

As shown in Figure 2, the illustration is the layered method of the iterative method used by the decoder of the present invention. The layered method used by the two patents mentioned in the background technology of the specification is shown on the left side of the figure, and each row of the mother matrix is expanded The k rows of k rows are used as one layer, and the total number of layers is the number of rows of the mother matrix. However, the layered method of the decoder of the present invention is shown on the right side of the figure. After each row of the mother matrix is expanded, only one row in the k rows is taken, and the total number of rows of the mother matrix is The number is taken as one layer, and the number of layers is the expansion factor k, for example, the first row after all expansion is the first layer, and the second row is the second layer... .

As shown in Figure 3, it is the circular shift register structure involved in the decoder of the present invention. The circular shift register is spliced and connected into a ring by multiple segments. The number of segments is the column weight of the mother matrix, and the output of each segment is passed to the bit node for processing. unit that passes input from the information bit processing unit.

As shown in Figure 4, it is the structure of the minimum sub-small value search module involved in the decoder of the present invention. The example is a 7-input module, which is sorted in groups of two pairs first, and then connected with 4 to select 2 modules to sort from the two groups. Select the smallest and second smallest values from the 4 numbers.

As shown in Figure 5, it is a structural diagram of an embodiment of the decoder of the present invention. The layered block irregular LDPC decoder includes: a decoding processing module, an external information storage unit, n cyclic shift There are three large modules of bit registers, among which the decoding processing module can be divided into three parts: bit node processing unit, check node processing unit and information bit processing unit.

As shown in Figure 6, the connection network diagram between several modules of an embodiment of the decoder of the present invention, wherein the circular shift register is a ping-pong register, the number of which is n (the number of columns of the n mother matrix), and the number of check nodes is m (m is the number of rows of the parent matrix), each bit node processing unit and information bit processing unit has a row-heavy addition or subtraction node.

In the decoding processing module, the external information storage unit outputs the soft value passed from the check node to the information node in the last iteration, that is, the check update value, to the decoding processing module. The circular shift register transmits the update value of the posterior probability likelihood ratio of the information node to the decoding processing module. The decoding processing module transmits the check update value passed from the check node to the information node in this iteration to the external information storage unit, and transmits the update value of the posterior probability likelihood ratio of the information node to the circular shift register.

As shown in FIG. 7 , the block diagram of the decoding core processing module of the decoding processing module includes: a first 2-to-1 selector 501, a bit node processing unit 502, a check node processing unit 509, and an information bit processing unit 512, Wherein: the first 2-to-1 selection module 501 selects the input data, and outputs the selected result to the bit node processing unit. The bit node processing unit calculates the bit update value of the information node, and transmits it to the check node processing unit and the information bit processing unit. The check node processing unit calculates the check update value of this iteration according to the received bit update value of the information node sent by the bit node processing unit, and transmits it to the information bit processing unit and the external information storage unit 509 . The information bit processing unit calculates the update value of the information node posterior probability likelihood ratio according to the bit update value sent by the bit node processing unit and the check update value of this iteration sent by the check node processing unit, and outputs it to the cyclic shift Register 515.

The decoding processing module, its execution flow is as follows:

(1) Select input data

The first 2-to-1 selector 501 selects the input data. If the information node participates in decoding for the first time in the decoding process, then select the cyclic shift register 514 or 515 that just stored the channel information, otherwise select the information node read out from another cyclic shift register 514 or 515 Probability Likelihood Ratio. The output llrSum of the first 2-to-1 selector 501 is delivered to the bit node processing unit.

(2) Calculate the bit update value of the information node

As shown in Figure 5, the bit node processing unit includes a subtractor 502, a first complement code converter 503 and a first truncation operator 504, and the check update value llr2MsgOld of the last iteration read from the external information storage unit is passed to Subtractor 502. Subtractor 502 subtracts the output llrSum of the first 2-to-1 selector 501 and the check update value llr2MsgOld to obtain the information update value llrNewTmp of the information node. Whether the check update value is read is to select the minimum or second minimum value. llrNewTmp is passed to the first complement converter 503 to convert the number in complement form into the number llrNewUnsigned in sign bit-absolute value form. Since the data bit width may become larger during the accumulation process, the output of the first complement converter 503 needs to be sent to the first truncation operator 504 to rename the bit width to the original predetermined size. The bit update value llr2Check from the first truncation operator 504 is sent to the check node processing unit.

(3) Calculate the check update value passed by the check node to the information node

As shown in FIG. 5 , the check node information update module includes: a minimum sub-smallest value search module and a correction module. The minimum sub-small value search module is composed of some comparators, the structure is shown in Figure 4, and the correction module is composed of three adders for multiplicative correction. The operation of the check node processing unit is divided into the following steps:

① Calculate the minimum value and the second minimum value of the bit update values of all information nodes connected to the current check node. (This embodiment adopts the LMMSA algorithm, so it is necessary to calculate the minimum value and the second minimum value among the bit update values connected to the current check node.)

Directly use a smallest and second smallest module 505 which is formed by connecting many comparators to find out the smallest and second smallest values at one time and use row weight bits to record whether the selection is the smallest or the second smallest.

② Multiplicative correction

The output of the smallest sub-module 505 is directly input to the multiplier 506 for multiplicative correction, that is, it is multiplied by a coefficient alpha, and the output after the multiplier is sent to the second truncation operator 507 . The Alpha value is simulated by scanning the coefficient alpha on the LDPC code general simulation platform, and the coefficient alpha is around 0.8, which has the best performance, and a value around 0.8 can be taken during implementation without re-simulation.

③Truncation operation

The bit width of the information coming out from the multiplier 506 is larger than the bit width of the check update value, so before entering the second complement converter 508, the bit width of the value needs to be adjusted, by the second truncation operator 507 Adjusted to check the bit width of the updated value.

④ Digital format conversion

The output of the second truncation operator 507 is sent to the second complement converter 508 to convert the number in sign bit-absolute value form into the number llr2Msg in complement form.

⑤ Calculate the updated value passed from the check node to the information node

According to the position bit flag, the smallest or the second smallest is selected as the update value delivered by the check node to the information node.

Finally, the check update value of this iteration is stored in the external information storage unit 401 .

(3) Calculate the update value of the posterior probability likelihood ratio of the information node

As shown in FIG. 5 , the information node posterior probability likelihood ratio update module includes a buffer 510 , a third complement converter 511 and an adder 512 . Buffer 510 buffers the bit update value llr2Check and delays it for several cycles, and the data Q from buffer 510 enters the third complement converter 511, converts the sign-absolute value shape into complement form llrNew, and sends it to adder 512 . Another input of the adder 512 is the check update value llr2Msg, and the two values are subtracted to obtain the update value llrSumNew of the posterior probability likelihood ratio of the information node. The sign bit of llrSumNew is the hard judgment result, and is stored in the circular shift register 514 or 515 of the ping-pong simultaneously.

When adopting the present embodiment system to a code length is 8064, code rate 1/2 non-regular low density check code, now will decode this code, expansion factor 96, number of layers is 96, namely the sub-matrix The number is 96. The non-regular LDPC is characterized by a weight of 7 for all rows. The specific decoding process includes the following steps:

Step 1, receiving channel information, the channel information will be sequentially divided into 8064/96=84 sub-modules, corresponding to 84 cyclic shift registers, one of the ping-pong cyclic shift registers will be used to shift and store channel information, The other is used for iterative decoding, and then the exchange function is used for ping-pong.

Step 2, the first 2-to-1 selection module 501 will select the circular shift register for iterative decoding, and send the selection result llrSum to the decoding processing module;

Step 3: Subtract the check update value llr2MsgOld of the last iteration read from the external information storage unit 509 and the posterior probability likelihood ratio llrSum of the information node as the llr information, perform complement conversion and truncation, and obtain the absolute value sum symbol;

Step 4, during the processing, the decoding processing module first obtains the bit update value llr2Check of the information node. According to the bit update value llr2Check of the information node, the check update value llr2Msg passed to the information node by the check node in this iteration is obtained and stored in the external information storage unit 509 . Next, the decoding processing module obtains the update value llrSumNew of the posterior probability likelihood ratio of the information node according to the bit update value llr2Check of the information node and the check update value llr2Msg passed to the information node by the check node in this iteration, and stores it in the circular shift register . After completing one iteration in this way, enter the next iteration. And so on, until the iteration ends.

The check update value llr2MsgOld of the last iteration entering the decoding processing module and the posterior probability likelihood ratio llrSum of the information node are subtracted as the two inputs of the subtractor 502 to obtain the information update value llrNewTmp of the information node. The llrNewTmp is passed to the first complement converter 503, and the number in the complement form is converted into the number llrNewUnsigned in the sign bit-absolute value form. The output of the first complement code converter 503 is sent to the first truncation operator 504. The data llr2Check from the first truncation operator 504 is stored in the buffer 510 in sequence. At the same time, the bit update value llr2Check is passed to the smallest second smallest value module. Step 5: In the check node processing unit, the smallest second-smallest module 505 selects the smallest and second-smallest values from the 7 llr2Checks corresponding to the same row, and inputs them to the multiplier 506 for multiplicative correction, that is, multiplying by 0.8125, and then from the multiplier The bit width of the information from 506 is larger than the bit width of the update value of the check node, so before entering the second complement converter 508, the bit width of the value needs to be adjusted, which is adjusted by the second truncation operator 507 is the bit width of the check node. The output of the second truncation operator 507 is sent to the second complement converter 508, the number of sign bit-absolute value form is converted into the number llr2Msg of the complement form, and the information llr2Msg coming out from the second complement converter 508 That is, the updated value of the bit check node is stored in the external information storage unit 509 .

Step 6, the Q from the register 510 enters the third complement converter 511, is converted from the sign-absolute value shape into the complement form llrNew, and is sent to the adder 512. Another input of the adder 512 is the check update value llr2Msg, and the two values are subtracted to obtain the update value llrSumNew of the posterior probability likelihood ratio of the information node. The sign bit of llrSumNew is the hard judgment result, and then stored in the circular shift register.

Step seven, the next cycle or iteration ends.

In this embodiment, there is no pipeline contention conflict, it uses circular shift register instead of memory, eliminates pipeline conflict, does not need to insert pipeline conflict idle waiting period, has better throughput performance, and working sequence is relatively simple; no need to consume The interweaving network of huge resources saves a lot of hardware resources, and the resource consumption of the whole decoder is relatively small.

Although the content of the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description should not be considered as limiting the present invention. Various modifications and alterations to the present invention will become apparent to those skilled in the art upon reading the above disclosure. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (10)

1. hierarchical block irregular low-density check code device, comprise: decoding processing module, external information memory cell, circulating register, it is characterized in that, the posterior probability likelihood ratio of using circulating register to come the stored information node, use minimum sub-minimum to search disposable output minimum of module and sub-minimum, decoding iterative process layered approach, respectively get delegation as one deck in the k that layered approach adopts mother matrix to expand is capable, each layer decoding quantity is a mother matrix, the number of plies cyclic extensions factor that is as the criterion; Wherein:

The external information memory cell is that the checksum update value is exported to the decoding processing module with the soft value that the check-node of last iteration passes to information node, and the check updating value in this iteration of transmitting of storage decoding processing module;

Circulating register passes to the decoding processing module with the posterior probability likelihood ratio of information node, and the posterior probability likelihood ratio updating value of the information node that transmits of storage decoding processing module;

The decoding processing module passes to the external information memory cell with the checksum update value that passes to information node by check-node in this iteration, and the posterior probability likelihood ratio updating value of information node is passed to circulating register through decoding processing module interleaving network.

2. hierarchical block irregular low-density check code device according to claim 1, it is characterized in that, described decoding processing module comprises: the one 2 selects 1 selector, bit node processing unit, code check node processing unit, information bit processing unit, wherein:

The one 2 selects 1 selector to select between the channel information and the information node posterior probability likelihood ratio of reading from circulating register, and the result that will select exports to the bit node processing unit;

The bit updating value of bit node processing unit computing information node passes to code check node processing unit and information bit processing unit;

The bit updating value of the information node that the bit node processing unit that code check node processing unit basis receives is sent here is calculated the checksum update value of this iteration, and is passed to information bit processing unit and external information memory cell;

The checksum update value of this iteration that bit updating value that the information bit processing unit transmits according to the bit node processing unit and code check node processing unit transmit is come computing information node posterior probability likelihood ratio updating value, and exports to circulating register through decoding processing module interleaving network.

3. hierarchical block irregular low-density check code device according to claim 2 is characterized in that, described bit node processing unit comprises: subtracter, the first complement code transducer and the first cut position arithmetic unit, wherein:

Subtracter subtracts each other the checksum update value of the last iteration that first information node posterior probability likelihood ratio and external information memory cell are read, and obtains the information updating value of information node, passes to the first complement code transducer;

The first complement code transducer is converted to the numeral of sign bit-absolute value form with the information updating value of information node, and is transferred to the first cut position arithmetic unit;

The first cut position arithmetic unit carries out the cut position operation to the dateout of the first complement code transducer, bit wide is become the bit wide of original information node information of being scheduled to, become big situation to avoid in the process that adds up, occurring data bit width, promptly obtain the bit updating value of information node.

4. hierarchical block irregular low-density check code device according to claim 2 is characterized in that, described code check node processing unit comprises: minimum is inferior searches module, multiplier, the second cut position arithmetic unit and the second complement code transducer for a short time, wherein:

For a short time search the information that module transmits from the bit node processing unit for minimum time and find out minimum value and sub-minimum, so that the further property taken advantage of correcting process is saved in the external information memory cell;

Multiplier multiply by a constant with minimum inferior output of searching module for a short time, this constant obtains by software emulation, the output of multiplier is again by the second cut position arithmetic unit, the bit wide of verification updating value is retrained within the specific limits, again through the second complement code transducer, obtain the checksum update value of final this iteration afterwards.

5. hierarchical block irregular low-density check code device according to claim 4 is characterized in that, described minimum time searches for a short time that module is made up of many four inputs, two output junior units and junior units are exported in two inputs two;

Two nodal informations of described two inputs, two output junior units inputs are output as and arrange good former state data by size, and effect is that two numbers are sorted, and is made of selector;

Four inputs of described four inputs, two output junior units are four outputs of two two inputs, two outputs or other two each and every one four inputs, two outputs, and effect is minimum and the sub-minimum selected inside two groups of input data that sequence size in four.

6. hierarchical block irregular low-density check code device according to claim 2 is characterized in that, described information bit processing unit comprises: buffer, the 3rd complement code transducer, adder, wherein:

Buffer is used to deposit the bit updating value of the information node that the bit node processing unit transmits, and its length equals the number of the information node that links to each other with current check-node, and the row that promptly equals the corresponding current check-node of check matrix is heavy;

The buffer that the 3rd complement code transducer receives in the code check node processing unit transmits data, and the data of symbol-absolute value form are converted to complement form;

The checksum update value addition of this iteration that adder transmits the output and the code check node processing unit of the 3rd complement code transducer obtains information node posterior probability likelihood ratio updating value, passes to the decoding circulating register.

7. hierarchical block irregular low-density check code device according to claim 1, it is characterized in that, described external information memory cell uses memory to realize, the memory number is the check-node number, data bit width is that the data bit width twice of external information adds up anharmonic ratio spy, storage maximum, minimum value and minimum value position, storage depth is the mother matrix spreading factor;

Described circulating register number has the bit node number, and each circulating register input and output tap number is the column weight of bit node corresponding to mother matrix.

8. a kind of hierarchical block irregular low-density check code method according to claim 1 is characterized in that, may further comprise the steps:

Step 1, the input data that obtain decoder are channel value;

Step 2, selector is selected the input data of information node posterior probability likelihood ratio, if this information node participates in decoding for the first time in decode procedure, the shift register of then selecting firm input channel information is as information node posterior probability likelihood ratio, otherwise the data of reading from the another one circulating register pass to the decoding processing module as the information node posterior probability likelihood ratio of current iteration;

Step 3, reading the soft value that check-node the last iteration passes to information node from the external information memory cell is the checksum update value, passes to the decoding processing module;

Step 4, bit node processing unit read out the checksum update value of the last iteration that information node posterior probability likelihood ratio and external information memory cell read, and obtain the bit updating value of information node, pass to the code check node processing unit;

Step 5, code check node processing unit are calculated the checksum update value of this iteration according to the bit updating value that passes to all information nodes of current check-node, and this checksum update value deposits the external information memory cell in;

Step 6 utilizes the 4th bit updating value and the 5th that goes on foot the information node that calculates to go on foot the checksum update value of this iteration that calculates, and the posterior probability likelihood ratio updating value of computing information node deposits shift register then in.

9. a kind of hierarchical block irregular low-density check code method according to claim 8, it is characterized in that, described decoding iterative process layered approach, respectively get delegation as one deck in the k that layered approach adopts mother matrix to expand is capable, each layer decoding quantity is a mother matrix, the number of plies cyclic extensions factor that is as the criterion does not need interleaving network, does not have the flowing water conflict.

10. hierarchical block irregular low-density check code processing method according to claim 8, it is characterized in that, the posterior probability likelihood ratio of described circulating register stored information node, each time in each layer decoding iteration, circulating register content displacement once, data but also import down one piece of data the last period had not only been exported in several sections junctions of a shift register loop.

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