CN101355406B - Decoder for layered non-rule low density checkout code and method for processing decode - Google Patents
Decoder for layered non-rule low density checkout code and method for processing decode Download PDFInfo
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Abstract
The invention provides a laminated irregular low-density check code decoder and an encoding processing method in the field of channel coding of the communication technology. The method comprises the following steps: a first memory unit transmits a soft value which is transmitted to an information node by a check node in last iteration to a decoding processing module; a second memory unit transmits an updated value of posterior probability likelihood ratio of the information node to the decoding processing module; the decoding processing module transmits a verified updated value in current iteration to the first memory unit, and simultaneously transmits the updated value of the posterior probability likelihood ratio of the information node to the second memory unit through an interlaced network of the decoding processing module; the interlaced network of the decoding processing module is used for adjusting the sequence of data entering the second memory unit; an interlaced network of an iteration stopping module is used for adjusting a hard decision result outputted by the decoding processing module; the iteration stopping module verifies the hard decision result to determine whether the hard decision result meets the condition for iteration stopping or not. The decoder and the method greatly improve the universality of the decoder, and reduce the power consumption in decoding process and the consumption of hardware resources.
Description
Technical field
The present invention relates to a kind of decoder and decoding process method of communication technical field, specifically is a kind of irregular low-density check code device and decoding process method of layering.
Background technology
Loe-density parity-check code (Low Density Parity Check Codes, LDPC Codes) is a kind of coding techniques that Gallager in 1963 at first proposes, has performance near shannon limit, become a research focus of coding field, be widely applied in the various wireless communication field standards, comprise the digital TV ground transmission standard of China, European second generation satellite digital video broadcast standard, IEEE802.11n, IEEE802.16e etc.In the present radio communication, the communication of high data rate more and more is subject to people's attention, and therefore simple in structure, the ldpc decoder that throughput is high is the research emphasis of LDPC sign indicating number always.In addition, in actual applications,, need to use the sign indicating number of different code length and code check to transmit according to the different and different channel conditions of the information of transmission.Therefore the ldpc decoder structure of supporting flexible code length, flexible code check also is to need one of emphasis of considering in the decoder architecture design.The structure of ldpc code decoder has three kinds of forms: serial structure, full parallel organization and part parallel structure.Part parallel structure ldpc decoder is because its moderate complexity and hardware resource consumption and extensive use.In addition, for ldpc decoder, different algorithms, for example belief propagation algorithm, minimum-sum algorithm, band correction minimum-sum algorithm, layering belief propagation algorithm, layering band correction minimum-sum algorithm etc., will influence the structure of ldpc decoder, influence the various aspects of decoder simultaneously, comprise throughput, performance, resource use etc.
Find through literature search prior art, number of patent application is 200710044708 Chinese patent, patent name is " low-density check code encoder of layering and a decoding process method ", carry and provided a kind of low-density check code encoder based on the correction minimum-sum algorithm, this decoder mainly is made up of processing module, first memory cell, second memory cell and first interleaving network, second interleaving network, this decoder needs two interleaving networks, because the design feature of interleaving network makes this decoder understand the more hardware resource of consumption rate; Simultaneously, the processing module of this decoder is not supported the heavy non-rule low density checkout code of any row that comes out by unit matrix quasi-cyclic shift extended architecture; Because the structural limitations of processing module, this decoder can only be unfavorable for dynamically adjusting throughput in specific moment output decode results; And this decoder is deciphered under given iterations, has obtained correct code word even deciphered, and decode procedure will continue, and makes that this decoder can the more power consumption of consumption rate.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, propose a kind of irregular low-density check code device and decoding process method of layering, the decoding processing module of improved decoder only needs an interleaving network, has saved hardware resource consumption; In addition, owing to adopted the method for inserting the idle clock cycle, this decoder is applicable to the heavy non-rule low density checkout code of any row that comes out by unit matrix quasi-cyclic shift extended architecture, and versatility is better; Decoder of the present invention can be supported dynamic throughput adjustment in any time of decode procedure output decode results; In the decoding iterative process, improved decoder carries out the judgement of iteration termination, and when deciphering when obtaining correct code word, decode procedure finishes, and helps reducing the power consumption of decoder.
The present invention is achieved by the following technical solutions:
The present invention relates to a kind of irregular low-density check code device of layering, comprise: decoding processing module, first memory cell, second memory cell, decoding processing module interleaving network, iteration termination module interleaving network and iteration termination processing module, wherein:
First memory cell is that the checksum update value is exported to the decoding processing module with the soft value that the check-node of last iteration passes to information node, and the check updating value in this iteration of transmitting of storage decoding processing module;
Second memory cell passes to the decoding processing module with the posterior probability likelihood ratio of information node, and the posterior probability likelihood ratio updating value of the information node that transmits of storage decoding processing module;
The number of decoding processing module equals the degree of parallelism k of decoder, the decoding processing module passes to first memory cell with the checksum update value that passes to information node by check-node in this iteration, the posterior probability likelihood ratio updating value of information node is passed to second memory cell through decoding processing module interleaving network, will decipher simultaneously and declare the result firmly and export to iteration termination module interleaving network;
Decoding processing module interleaving network is responsible for adjusting the transmission sequence of posterior probability likelihood ratio updating value that the decoding processing module outputs to the information node of second memory cell;
What iteration termination module interleaving network was responsible for adjusting the output of decoding processing module declares the result firmly, and sends into the iteration termination processing module;
The iteration termination processing module is declared the result firmly to this and is carried out verification, judges whether to satisfy the condition of iteration termination.
Described decoding processing module comprises: the one 2 selects 1 selector, bit information computing module, check-node information calculations module, information node posterior probability likelihood ratio computing module, wherein:
The one 2 selects 1 selector to select between the channel information and the information node posterior probability likelihood ratio of reading from second memory cell, and the result that will select exports to the bit information computing module;
The bit updating value of bit information computing module computing information node passes to check-node information calculations module and information node posterior probability likelihood ratio computing module;
The bit updating value of the information node that the bit information computing module that check-node information calculations module basis receives is sent here is calculated the checksum update value of this iteration, and is passed to the information node posterior probability likelihood ratio computing module and first memory cell;
The checksum update value of this iteration that bit updating value that information node posterior probability likelihood ratio computing module transmits according to the bit information computing module and check-node information calculations module transmit is come computing information node posterior probability likelihood ratio updating value, and exports to second memory cell through decoding processing module interleaving network.
The described the 1 selects 1 selector that the data of input are selected, if this information node participates in decoding for the first time in decode procedure, and selective channel information then, otherwise select the information node posterior probability likelihood ratio of from second memory cell, reading.
Described bit information computing module comprises: subtracter, the first complement code converter and the first cut position arithmetic unit, wherein:
Subtracter selects the checksum update value of the last iteration that the information node posterior probability likelihood ratio that 1 selector transmits and first memory cell read to subtract each other with the 1, obtains the information updating value of information node, passes to the first complement code transducer;
The first complement code transducer is converted to the numeral of sign bit-absolute value form with the information updating value of information node, and is transferred to the first cut position arithmetic unit;
The first cut position arithmetic unit carries out the cut position operation to the dateout of the first complement code transducer, bit wide is become the bit wide of original information node information of being scheduled to, become big situation to avoid in the process that adds up, occurring data bit width, promptly obtain the bit updating value of information node.
Described check-node information calculations module comprises: buffer, first comparator, first register, the 22 select 1 selector, second register, second comparator, multiplier, the second cut position arithmetic unit and the second complement code transducer, wherein:
Buffer is used to deposit the bit updating value of the information node that the bit information computing module transmits, and its length equals the number (promptly equaling the row weight RowWt of the corresponding current check-node of check matrix) of the information node that links to each other with current check-node;
An input of first comparator is current bit updating value, another input is that check-node receives current minimum value and the current sub-minimum in the information, first comparator upgrades minimum value and the sub-minimum that check-node receives information according to these two inputs, first comparator carries out XOR respectively with the sign bit of current bit updating value and the sign bit of current minimum value and current sub-minimum simultaneously, as the sign bit that upgrades back minimum value and sub-minimum, the output of first comparator gives the 22 to select 1 selector by first register transfer; After the comparison of finishing RowWt data, the output of first comparator passes to second register, and all information nodes that link to each other with current check-node pass to minimum value and the sub-minimum in its information exactly;
The 22 to select the input of 1 selector be the output of first register, be used for the data of comparison as output according to current the selection relatively constantly, if current time, the bit updating value that passes to first comparator is first information of certain check-node, then the 22 select 1 selector to select 11 ... 1 as current minimum value and the output of current sub-minimum, and wherein 1 number equals the bit wide of data; Otherwise the 22 selects 1 selector to select the output of first register, passes to first comparator;
Second comparator receives the output of second register and the output of buffer, second comparator selective value from the result of check-node passes to information node, the concrete operations mode of second comparator is: when from the data of buffer and minimum value identical, second comparator is chosen sub-minimum, otherwise chooses minimum value; The sign bit of the value that second comparator also will be chosen out carries out XOR with sign bit from the data of buffer, obtains the sign bit of dateout, and the output of second comparator passes to multiplier;
Multiplier multiply by a constant with the output of second comparator, this constant obtains by software emulation, the output of multiplier is again by the second cut position arithmetic unit, the bit wide of verification updating value is retrained within the specific limits, again through the second complement code transducer, obtain the checksum update value of final this iteration afterwards.
Described information node posterior probability likelihood ratio computing module comprises: the 3rd complement code transducer, adder, wherein:
The buffer that the 3rd complement code transducer receives in the check-node information calculations module transmits data, and the data of symbol-absolute value form are converted to complement form;
The checksum update value addition of this iteration that adder transmits the output and the check-node information calculations module of the 3rd complement code transducer, obtain information node posterior probability likelihood ratio updating value, pass to decoding processing module interleaving network, the sign bit of information node posterior probability likelihood ratio updating value passes to iteration termination module interleaving network as declaring the result firmly simultaneously.
Described iteration termination processing module, calculate the check results of each check equations, the result that declares firmly of the information node that soon is associated with this check equations carries out XOR, if check results is 0, be currently to declare the result firmly and satisfy this check equations, otherwise do not satisfy; If the check results of all check equations all is 0, then decode procedure has converged to legal-code, sends control signals to the decoding processing module simultaneously, ends the work of decoding processing module.
Described iteration termination processing module comprises: the 3rd register, the 4th register, the 5th register, the 3rd comparator, the 32 select 1 selector, accumulator and the 4th comparator, wherein:
The k that the 3rd register is sent iteration termination module interleaving network here declares the result than ultrahard and stores, and passes to the 3rd comparator then;
The 32 selects 1 selector to be used for the data of comparison as output according to current the selection relatively constantly, if current time, what pass to the 3rd comparator declares first information that the result is the check equations that comprises of certain submatrix firmly, then the 32 select 1 selector to select 00 ... 0 as output, wherein 0 number equals the degree of parallelism k of decoder, otherwise the 32 selects 1 selector to select the output of the 4th register, pass to the 3rd comparator, after the comparison of finishing RowWt data, the output of the 3rd comparator passes to the 5th register.The check results of the check equations that current submatrix comprises that Here it is.
The 3rd comparator is according to two inputs, upgrade the check results of the check equations that current submatrix comprises, if the data of two inputs of the 3rd comparator are identical, the check results of the check equations that corresponding submatrix comprises is 0, otherwise the comparative result that is 1, the three comparator gives the 32 to select 1 selector by the 4th register transfer;
The 5th register is exported to accumulator with the check results of storage;
Accumulator is used to add up the number that check results is 0 submatrix, and after the check results of all submatrixs all obtained, the result that accumulator will be added up exported to the 4th comparator;
Another input of the 4th comparator is the number of the submatrix of check matrix, if two inputs of the 4th comparator are identical, illustrate that then all submatrixs all satisfy, be that decode procedure has been deciphered the code word that obtains restraining, then making the iteration termination signal is 1, end the work of decoding processing module, otherwise the iteration termination signal is changed to 0.
Described decoding processing module interleaving network is responsible for deciphering information node posterior probability likelihood ratio updating value cyclic shift that processing module obtains to correct position, and is deposited second memory cell in.
Described iteration termination module interleaving network is responsible for the cyclic shift of declaring firmly as a result of last iteration is sent into the iteration termination module then and handled to correct position.
The present invention relates to a kind of irregular low-density check code processing method of layering, may further comprise the steps:
Step 2, the one 2 selects 1 selector that the input data of information node posterior probability likelihood ratio are selected, if this information node participates in decoding for the first time in decode procedure, then selective channel information is as information node posterior probability likelihood ratio, otherwise the data of reading from second memory cell pass to the decoding processing module as the information node posterior probability likelihood ratio of current iteration;
Step 3, reading the soft value that check-node the last iteration passes to information node from first memory cell is the checksum update value, passes to the decoding processing module;
Step 4, the bit information computing module reads out the one 2 checksum update value of selecting the last iteration that the information node posterior probability likelihood ratio that 1 selector transmits and first memory cell read, obtain the bit updating value of information node, pass to check-node information calculations module, for the heavy bigger check-node of row, the bit information computing module inserts after information node posterior probability likelihood ratio that reads out and checksum update value waits for the clock cycle;
Step 5, check-node information calculations module are calculated the checksum update value of this iteration according to the bit updating value that passes to all information nodes of current check-node, and this checksum update value deposits first memory cell in; For the heavy bigger check-node of row, before the bit updating value of check-node information calculations module sense information node, insert and wait for the clock cycle;
Step 6, utilize the 4th bit updating value and the 5th that goes on foot the information node that calculates to go on foot the checksum update value of this iteration that calculates, the posterior probability likelihood ratio updating value of computing information node, pass to decoding processing module interleaving network, the sign bit of information node posterior probability likelihood ratio updating value passes to iteration termination module interleaving network as declaring the result firmly simultaneously;
Step 7, the data of iteration termination module interleaving network output are sent into the iteration termination processing module and are carried out the iteration termination processing, specifically: judge whether iterations reaches preset value or whether satisfy the iteration termination condition, if iterations reaches preset value or satisfies the iteration termination condition, then operation stops, otherwise, return second step beginning next iteration.
Described iteration termination is handled, and may further comprise the steps:
The first step, the result is declared in the decoding that obtains last iteration firmly, will declare the result firmly by iteration termination module interleaving network and adjust to correct position;
In second step, calculate the check results of the check equations that each submatrix comprises;
In the 3rd step, if satisfy the termination condition, the check results of promptly all check equations is 0 all, stops decode procedure, and the result is declared in output firmly; Otherwise return the first step, judge the correctness of decode results next time.
Described bit information computing module inserts after information node posterior probability likelihood ratio that reads out and checksum update value waits for the clock cycle, is specially: concrete processing method may further comprise the steps:
When the bit information computing module heavily is the information node of RowWt1 at the processing row, when reading the checksum update value of corresponding RowWt1 last iteration and RowWt1 information node posterior probability likelihood ratio from first memory cell and second memory cell, need insert (RowWtl-RowWt2) individual wait clock cycle in the back of checksum update value and information node posterior probability likelihood ratio, these data are through subtracter, the first complement code transducer, the first cut position arithmetic unit is sent into check-node information calculations module, wherein, RowWt0 and RowWt2 are that adjacent going of two check-nodes weighs.
Described before the bit updating value of check-node information calculations module sense information node, insert and wait for the clock cycle, specific as follows: when calculating the checksum update value of this iteration, read row heavily before the bit updating value for the relevant information node of the check-node of RowWt1 from buffer, insert (RowWtl-RowWt0) individual wait clock cycle.
The method of clock cycle is waited in described insertion, come the heavier different check-node value of information of newline and the bit posterior probability likelihood ratio of information node accordingly, be because for the bigger check-node of row anharmonic ratio, need the more clock cycle to upgrade its relevant information, can produce the flowing water conflict, adopt the method for inserting the wait clock cycle can avoid the flowing water conflict.Adopted and inserted the heavy non-rule low density checkout code of any row that the method for waiting for the clock cycle makes this decoder support come out by unit matrix quasi-cyclic shift extended architecture.
The present invention has following beneficial effect:
(1) decode procedure only needs a decoding processing module interleaving network, with respect to existing required first interleaving network and second interleaving network of ldpc decoder based on layering minimum and correction algorithm, reduced an interleaving network, the consumption of having saved hardware resource;
(2) owing to adopted and insert the processing method of waiting for the clock cycle, this decoder can be supported the heavy non-rule low density checkout code of any row that comes out by unit matrix quasi-cyclic shift extended architecture;
(3) support abundant more code check and code length;
(4) therefore stored information node posterior probability likelihood ratio updating value in the decode procedure, can export the judgement decode results at any time, supports dynamic throughput adjustment;
(5) have the iteration termination function, can end to restrain the decode procedure of code word in advance, save power consumption.
Description of drawings
Fig. 1 is the structural representation of H matrix of the LDPC sign indicating number of accurate cyclic extensions method construct among the present invention;
Fig. 2 is the structural representation of the check matrix among the present invention;
Fig. 3 is the structural representation of the submatrix of check matrix among the present invention;
Fig. 4 is the system architecture diagram of decoder of the present invention;
Fig. 5 is the structured flowchart of the decoding processing module in the decoder of the present invention;
Fig. 6 is the structured flowchart of the iteration termination processing module in the decoder of the present invention.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
As shown in Figure 1, be existing mother matrix and the extended method thereof of degree of parallelism that use as the quasi-cyclic LDPC code that decoder adopted of k.Needing the size of the code word of structure is m*n, and then the size of corresponding mother matrix is (m/k) * (n/k), and each element in the mother matrix expands to the matrix of a k*k.In the mother matrix 0 is extended to the null matrix of a k*k; In the mother matrix 1 is extended to the cyclic shift form of the cell matrix of a k*k, and among the figure, the left side is the mother matrix schematic diagram, and the right side is certain nonzero element expansion schematic diagram in the mother matrix.
As shown in Figure 2, be that existing suitable degree of parallelism is the LDPC code check matrix structure chart of the decoder of k.Check matrix comprise (layer of the line number of check matrix/k), every layer line number is k, each layer is called submatrix, h
0Or h
1It is exactly the example of a submatrix.
As shown in Figure 3, be the structural representation of submatrix in the check matrix.Submatrix is divided into N/k little square formation (such as 301, N is a code length) at column direction, and the columns of each little square formation is k.Little square formation in the submatrix has two kinds of forms: null matrix and unit cyclic shift matrix.Wherein the number of unit cyclic shift matrix is that going of this submatrix is heavy.For non-rule low density checkout code, the row of submatrix is heavy different, because the number of single-place shift cyclic matrix is also inequality in the submatrix.
As shown in Figure 4, present embodiment relates to a kind of irregular low-density check code device of layering, comprise: k decoding processing module, first memory cell 401, second memory cell 402 and decoding processing module interleaving network 403, iteration termination module interleaving network 404 and iteration termination processing module 405, wherein:
Decoding processing module number equals the degree of parallelism k of decoder, and first memory cell 401 is that the checksum update value is exported to the decoding processing module with the soft value that the check-node of last iteration passes to information node.Second memory cell 402 passes to the decoding processing module with the updating value of the posterior probability likelihood ratio of information node.The decoding processing module passes to first memory cell 401 with the checksum update value that passes to information node by check-node in this iteration, the posterior probability likelihood ratio updating value of information node is passed to second memory cell 402 through decoding processing module interleaving network 403, will decipher simultaneously and declare the result firmly and export to iteration termination module interleaving network 404.Decoding processing module interleaving network 403 is used to adjust the order of dateout.What iteration termination module interleaving network 404 was used to adjust the output of decoding processing module declares the result firmly, and sends into iteration termination processing module 405.This declares 405 pairs of iteration termination processing modules the result firmly and carries out verification, judges whether to satisfy the condition of iteration termination.
As shown in Figure 5, described decoding processing module, comprise: the one 2 selects 1 to select mould device 501, bit information computing module, check-node information calculations module, information node posterior probability likelihood ratio computing module, wherein: the one 2 selects 1 to select the data of 501 pairs of inputs of module to select, and the result that will select exports to the bit information computing module.The bit updating value of bit information computing module computing information node passes to check-node information calculations module and information node posterior probability likelihood ratio computing module.The bit updating value of the information node that the bit information computing module that check-node information calculations module basis receives is sent here is calculated the checksum update value of this iteration, and is passed to the information node posterior probability likelihood ratio computing module and first memory cell 401.The checksum update value of this iteration that bit updating value that information node posterior probability likelihood ratio computing module transmits according to the bit information computing module and check-node information calculations module transmit is come computing information node posterior probability likelihood ratio updating value, and exports to second memory cell 402 through decoding processing module interleaving network 403.
Described decoding processing module, it is as follows that it carries out flow process:
(1) selects the input data
The one 2 selects the data of 501 pairs of inputs of 1 selector to select.If this information node participates in decoding for the first time in decode procedure, selective channel information llrChan then, otherwise select the information node posterior probability likelihood ratio of from second memory cell 402, reading.The one 2 selects the output llrSum of 1 selector 501 to pass to the bit information computing module.
(2) the bit updating value of computing information node
As shown in Figure 5, the bit information computing module comprises subtracter 502, the first complement code converter 503 and the first cut position arithmetic unit 504, the checksum update value llr2MsgOld of the last iteration of reading from first memory cell passes to subtracter 502, subtracter 502 selects the output llrSum of 1 selector 501 and checksum update value llr2MsgOld to subtract each other with the 1, obtains the information updating value llrNewTmp of information node.LlrNewTmp passes to the first complement code transducer 503, the digital translation of complement form is become the digital llrNewUnsigned of sign bit-absolute value form.Become big situation owing to may occur data bit width in the process that adds up, therefore the output of the first complement code transducer 503 need be sent to the first cut position arithmetic unit 504, bit wide is renamed as original predetermined size.The bit updating value llr2Check that the first cut position arithmetic unit 504 comes out sends into check-node information calculations module.
(3) the calculation check node passes to the checksum update value of information node
As shown in Figure 5, the check-node information updating module comprises: buffer 505, first comparator 506, first register the 507, the 22 select 1 selector 508, second register 509, second comparator 510, multiplier 511, the second cut position arithmetic unit 512 and the second complement code transducer 513, and wherein the output llr2Check of the first cut position arithmetic unit 504 deposits in the buffer 505 in order.It is heavy that the length of buffer 505 equals the maximum row of H matrix.The operation of check-node information calculations module is divided into following a few step again:
1. calculate the minimum value and the sub-minimum of the bit updating value of all information nodes that link to each other with current check-node.(present embodiment adopts the LMMSA algorithm, so minimum value and sub-minimum in the bit updating value that needs calculate with current check-node links to each other.)
The bit updating value llr2Check that an input of first comparator 506 is current information nodes, another is input as minimum value and sub-minimum that current check-node receives the bit updating value of information node.As llr2Check during less than the minimum value of the bit updating value of the current information node that receives, current sub-minimum is replaced by minimum value, and minimum value is replaced by the bit updating value llr2Check of this information node; When the minimum value of llr2Check greater than the bit updating value of the current information node that receives, during less than the sub-minimum of the bit updating value of the current information node that receives, current minimum value is constant, and sub-minimum is replaced by llr2Check; As llr2Check during greater than the sub-minimum of the bit updating value of the current information node that receives, minimum value and sub-minimum are constant.After relatively intacter, the renewal result of minimum value and sub-minimum deposits in first register 507.
The 22 to select 1 selector 508 be that first comparator 506 is selected suitable comparison numerical value.If bit updating value llr2Check is first information that passes to certain check-node, then the 22 select 1 selector 508 to select 11 ... 1 (1 number equals the bit wide of data) exports as current minimum value and current sub-minimum, otherwise the 22 selects 1 selector 508 to select the output of first register 507.After the comparison of finishing RowWt data, the output of first comparator 506 enters in second register 509, minimum value and sub-minimum in the bit updating value that Here it is with current check-node links to each other.
2. the calculation check node passes to the updating value of information node
After all information nodes that second register 509 obtains linking to each other with current check-node pass to minimum value and sub-minimum in its information, take out corresponding data Q from buffer 505 in order, the information that passes over first register 507 is together as the input of second comparator 510.Second comparator 510 selects suitable value to pass to information node from the result of check-node, and the concrete operations mode is: when Q and minimum value big or small identical, second comparator 510 will be chosen sub-minimum, otherwise choose minimum value.Next second comparator 510 will carry out the sign bit of XOR as this module output valve to the sign bit of the value of choosing out with the sign bit of Q, and the order of magnitude of output valve then is the size of second comparator, 510 output valves.
3. the property taken advantage of correction
The output of second comparator 510 is input to the property taken advantage of correction in the multiplier 511, is about to it and multiply by a coefficient alpha, and the output of multiplier 511 is exactly the checksum update value that check-node passes to information node.
Send into the second cut position arithmetic unit 512 through the output after the multiplier.
4. cut position computing
The bit wide of the information of coming out from multiplier 511 is bigger than the bit wide of checksum update value, so before entering the second complement code transducer 513, need adjust the bit wide that this value is carried out, is adjusted into the bit wide of checksum update value by the second cut position arithmetic unit 512.
5. number format conversion
The second complement code transducer 513 is sent in the output of the second cut position arithmetic unit 512, is the digital llr2Msg of complement form with the digital translation of sign bit-absolute value form.
At last, the information llr2Msg that comes out from the second complement code converter 513 is the checksum update value of this iteration, deposits first memory cell 401 in.
(3) computing information node posterior probability likelihood ratio updating value
As shown in Figure 5, information node posterior probability likelihood ratio update module comprises the 3rd complement code transducer 514 and adder 515.The data Q that comes out from buffer 505 enters the 3rd complement code transducer 514, is converted into complement form llrNew by symbol-absolute value shape, sends into adder 515.Another input of adder 515 is checksum update value llr2Msg, and two values are subtracted each other, and obtains information node posterior probability likelihood ratio updating value llrSumNew.The sign bit of llrSumNew just is declares the result firmly, exports to iteration termination module interleaving network 404.Simultaneously, llrSumNew is through depositing second memory cell 402 in after the decoding processing module interleaving network 403.
The result that declares firmly that the iteration termination processing module is sent iteration termination module interleaving network 404 here carries out verification, judges whether to satisfy the iteration termination condition.
As shown in Figure 6, described iteration termination processing module comprises: the 3rd register 601, the 4th register 602, the 5th register 603, the 3rd comparator the 604, the 32 select 1 selector 605, accumulator 606 and the 4th comparator 607.The k that the 3rd register 601 is sent iteration termination module interleaving network 404 here declares the result than ultrahard and stores, and passes to the 3rd comparator 604 then.The 3rd comparator 604 is according to two inputs, upgrades the check results of the check equations that current submatrix comprises.If the data of 604 two inputs of the 3rd comparator are identical, the check results of the check equations that corresponding submatrix comprises is 0, otherwise is 1.The comparative result of the 3rd comparator 604 passes to the 4th register 602.The output of the 4th register 602 passes to the 32 and selects 1 selector 605.The 32 selects 1 selector 605 to select the suitable data that are used for comparison as output relatively constantly according to current, passes to the 3rd comparator 604.After the comparison of finishing RowWt data, the output of the 3rd comparator 604 passes to the 5th register 603.The check results of the check equations that current submatrix comprises that Here it is.The 5th register 603 is exported to accumulator 606 with the check results of storage.Accumulator 606 is used to add up the number that check results is 0 submatrix.After the check results of all submatrixs all obtained, the result that accumulator 606 will be added up exported to the 4th comparator 607.Another input of the 4th comparator 607 is the number of the submatrix of check matrix.If two inputs of the 4th comparator 607 are identical, illustrate that then all submatrixs all satisfy, promptly decode procedure has been deciphered the code word that obtains restraining, and then making the iteration termination signal is 1, end the work of decoding processing module, otherwise the iteration termination signal equals 0.
Suppose to have now that a code length is 5376, code check is 4/7 non-rule low density checkout code, will decipher this sign indicating number now, degree of parallelism is 32, the number of plies is 72, promptly the number of submatrix is 72.The characteristics of this non-rule low density checkout code are that the 34th layer row heavily is 8, and the row of remainder layer heavily is 7.
Table one: decoding processing module
| Module | Number |
| The decoding processing module | 32 |
Table two: the parameter of decoding memory cell
| Memory cell | The degree of depth |
| |
505 |
| |
168 |
Table three: decoding processing module neutron number of modules
| Module | Number |
| The one 2 selects 1 |
1 |
| |
1 |
| The first complement code transducer 503 | 1 |
| The first cut position |
1 |
| |
1 |
| |
1 |
| |
1 |
| The 22 selects 1 |
1 |
| |
1 |
| |
1 |
| |
1 |
| The second cut position |
1 |
| The second |
1 |
| The 3rd |
1 |
| |
1 |
Table four: the number of submodule in the iteration termination processing module
| Module | Number |
| The 3rd register 601 | 1 |
| The 4th register 602 | 1 |
| The 5th register 603 | 1 |
| The 3rd comparator 604 | 1 |
| The 32 selects 1 selector 605 | 1 |
| Accumulator 606 | 1 |
| The 4th comparator 607 | 1 |
The irregular low-density check code processing method of the layering that present embodiment relates to, specific as follows:
Step 2, the one 2 selects 1 to select module 501 to select between the output of the channel information subcode piece llrChan that receives and second memory cell 402, and selection result llrSum is sent into the decoding processing module.The current information node participates in decoding for the first time, then selects corresponding channel information subcode piece as input, otherwise the output of selecting second memory cell 402 is as input.After iteration finished for the first time, all channel information subcode piece llrChan were admitted to the decoding processing module;
Step 3, the checksum update value llr2MsgOld and the information node posterior probability likelihood ratio llrSum of the last iteration of reading from first memory cell 401 are transferred to by the decoding processing module and handle;
Step 4, in processing procedure, the decoding processing module at first obtains the bit updating value llr2Check of information node.Obtaining this iteration check-node according to the bit updating value llr2Check of information node passes to the checksum update value llr2Msg of information node and deposits first memory cell 401 in.Then, the decoding processing module obtains information node posterior probability likelihood ratio updating value llrSumNew according to the bit updating value llr2Check of information node with the checksum update value llr2Msg that this iteration check-node passes to information node, through decoding processing module interleaving network 403, deposit second memory cell 402 then in.So 72 cycles of circulation, just finished iteration one time.Enter next iteration afterwards.And the like, finish up to iteration.
The checksum update value llr2MsgOld and the information node posterior probability likelihood ratio llrSum that enter the last iteration of decoding processing module subtract each other as two inputs of subtracter 502, obtain the information updating value llrNewTmp of information node.LlrNewTmp is passed to the first complement code transducer 503, the digital translation of complement form is become the digital llrNewUnsigned of sign bit-absolute value form.The output of the first complement code transducer 503 is sent to the first cut position arithmetic unit 504.The data llr2Check that the first cut position arithmetic unit 504 comes out deposits in the buffer 505 in order, and the length of buffer 505 is 8.Simultaneously, bit updating value llr2Check passes to first comparator 506.
Step 5, in the check-node information calculations module, the bit updating value llr2Check that an input of first comparator 506 is current information nodes, another is input as minimum value and sub-minimum that current check-node receives the bit updating value of information node.As llr2Check during less than the minimum value of the bit updating value of the current information node that receives, current sub-minimum is replaced by minimum value, and minimum value is replaced by the bit updating value llr2Check of this information node; When the minimum value of llr2Check greater than the bit updating value of the current information node that receives, during less than the sub-minimum of the bit updating value of the current information node that receives, current minimum value is constant, and sub-minimum is replaced by llr2Check; As llr2Check during greater than the sub-minimum of the bit updating value of the current information node that receives, minimum value and sub-minimum are constant.After relatively intacter, the renewal result of minimum value and sub-minimum deposits in first register 507.First comparator 506 also carries out XOR respectively with the sign bit of llr2Check and the sign bit of current minimum value and current sub-minimum, as the sign bit that upgrades back minimum value and sub-minimum.
The 22 to select 1 selector 508 be that first comparator 506 is selected suitable comparison numerical value.If bit information value llr2Check is first information that passes to certain check-node, then the 22 select 1 selector 508 to select 11 ... 1 (1 number equals the bit wide of data) exports as current minimum value and current sub-minimum, otherwise selects the output of first register 507.After the comparison of finishing RowWt data, the output of first comparator 506 enters in second register 509, and all information nodes that Here it is links to each other with current check-node pass to minimum value and the sub-minimum in its information.
After all information nodes that second register 509 obtains linking to each other with current check-node pass to minimum value and sub-minimum in its information, take out corresponding data Q from buffer 505 in order, the information that passes over second register 509 is together as the input of second comparator 510.Second comparator 510 selects suitable value to pass to information node from the result of check-node, and the concrete operations mode is: when Q and minimum value big or small identical, second comparator 510 will be chosen sub-minimum, otherwise choose minimum value.Next second comparator 510 will carry out the sign bit of XOR as this module output valve to the sign bit of the value of choosing out with the sign bit of Q, and the order of magnitude of output valve then is the size of second comparator, 510 output valves.
The output of second comparator 510 is input to the property taken advantage of correction in the multiplier 511, promptly multiply by 0.8125, and the output of multiplier 511 is exactly the checksum update value that check-node passes to information node.
The bit wide of the information of coming out from multiplier 511 is bigger than the bit wide of the updating value of check-node, so before entering the second complement code transducer 513, need adjust the bit wide that this value is carried out, is adjusted into the bit wide of check-node by the second cut position arithmetic unit 512.
The second complement code transducer 513 is sent in the output of the second cut position arithmetic unit 512, with the digital translation of sign bit-absolute value form is the digital llr2Msg of complement form, the ascend the throne updating value of check-node of the information llr2Msg that comes out from the second complement code converter 513 deposits first memory cell 401 in.
Step 6, the Q that comes out from buffer 505 enters the 3rd complement code transducer 514, is converted into complement form llrNew by symbol-absolute value shape, sends into adder 515.Another input of adder 515 is checksum update value llr2Msg, and two values are subtracted each other, and obtains information node posterior probability likelihood ratio updating value llrSumNew.The sign bit of llrSumNew just is declares the result firmly, exports to iteration termination module interleaving network 404.Simultaneously, llrSumNew is through depositing second memory cell 402 in after the decoding processing module interleaving network 403.
Step 7, in the iteration termination processing module, the k that the 3rd register 601 is sent iteration termination module interleaving network 404 here declares the result than ultrahard and stores, and passes to the 3rd comparator 604 then.The 3rd comparator 604 is according to two inputs, upgrades the check results of the check equations that current submatrix comprises.The comparative result of the 3rd comparator 604 passes to the 4th register 602.The output of the 4th register 602 passes to the 32 and selects 1 selector 605.The 32 selects 1 selector 605 to select the suitable data that are used for comparison as output relatively constantly according to current, passes to the 3rd comparator 604.After the comparison of finishing RowWt data, the output of the 3rd comparator 604 passes to the 5th register 603.The 5th register 603 is exported to accumulator 606 with the check results of storage.After the check results of all submatrixs all obtained, another input that the result that accumulator 606 will be added up exports to the 4th comparator 607, the four comparators 607 was a submatrix number 72.If two inputs of the 4th comparator 607 are identical, illustrate that decode procedure deciphered the code word that obtains restraining, then making the iteration termination signal is 1, end the work of decoding processing module, otherwise the iteration termination signal is changed to 0.
In the present embodiment, the RowWt that a check-node in the submatrix is arranged is 8, and all the other all are 7, and the processing of this check-node being inserted the method for waiting for the clock cycle is specific as follows:
When the processing row weighs 8 bit update calculation module, when selecting 1 selector to obtain 501 corresponding 8 check-node updating value llr2MsgOld and 8 information node posterior probability likelihood ratio updating value llrSum from first memory cell the 401 and the 1, need wait for the clock cycle 1 of the back of a check-node updating value and information node posterior probability likelihood ratio updating value insertion, these data are sent into check-node information calculations module through subtracters 502, the first complement code transducer 503, the first cut position arithmetic unit 504.
Send into after the check-node information calculations module, need 8 clock cycle to seek maximum and minimum value that row heavily is 8 check-node; Simultaneously, because the water operation of this decoder, row heavily is that 7 previous check-node is just read corresponding llr2Check from buffer 505 and come the information that passes over second register 509 together as the input of second comparator 510, calculate the checksum update value that this check-node passes to information node, after 7 clock cycle, renewal is finished, and the llr2Check that will read row this moment and heavily be 8 check-node from buffer 505 carries out the renewal of corresponding check node value.At this moment, need from the data that buffer 505 is read, add 1 and wait for that the clock cycle waits for that it heavily is the maximum and the minimum value of 8 check-nodes that first register 507 obtains row.After obtaining the maximum and minimum value that row heavily is 8 check-node, can from buffer 505, read information that corresponding llr2Check passes over second register 509 together as the input of second comparator 510, calculate the checksum update value that this check-node passes to information node.Because we in decoding at first, be expert at heavily is to have added one after the bit updating value of relevant information node of 8 check-node to wait for the clock cycle, at this moment, to seek row heavily be that the maximum and the minimum value of 7 next check-node is to be 8 clock cycle the needed time for first comparator 506 and first register 507.At last, heavily be that the maximum and the minimum value of 7 next check-node is when first comparator 506 and first register 507 find row, row heavily is that 8 check-node has also been finished the calculating that check-node passes to the checksum update value of information node.
Comprised that one is waited for clock cycle and 8 valid data so the row that comes out from the second complement code transducer 513 heavily is the updating value llr2Msg of 8 check-node, deposited before first memory cell 8 valid data in 401.
When information node posterior probability likelihood ratio is upgraded, the row that comes out from the 3rd complement code transducer 514 heavily is that 8 information node posterior probability likelihood ratio updating value has comprised that 1 is waited for clock cycle and 8 valid data, wherein, 8 valid data enter decoding processing module interleaving network 403, send into second memory cell 402 then.
In the present embodiment, decoding treatment process only need promptly be deciphered the processing module interleaving network with an interleaving network, and the order of data is adjusted.Compare with second interleaving network with first interleaving network that the low-density check code encoder of the layering of mentioning in the background technology is required, saved an interleaving network, can reduce hardware resource consumption.
In the present embodiment, improved decoder has adopted and inserted the method for idle waiting clock cycle heavily is 8 to a particular row, remaining row heavily is that 7 non-rule low density checkout code is handled, and the low-density check code encoder of the layering of mentioning in the background technology is not supported the non-rule low density checkout code of this form.
In the present embodiment,, can export decode results at any time, compare, support dynamic throughput adjustment with the low-density check code encoder of mentioning layering in the background technology because second cell stores is information node posterior probability likelihood ratio.
In the present embodiment, improved decoder has optional iteration termination processing module.Compare with the low-density check code encoder of mentioning layering in the background technology, under high s/n ratio, can finish decode procedure in advance, saved the power consumption of decoder.
In the present embodiment, mention the low-density check code encoder of layering in improved decoder and the background technology and compare, support abundant more code check and code length.
Claims (10)
1. the irregular low-density check code device of a layering, comprise: decoding processing module, first memory cell, second memory cell, it is characterized in that, also comprise: decoding processing module interleaving network, iteration termination module interleaving network and iteration termination processing module, wherein:
First memory cell is that the checksum update value is exported to the decoding processing module with the soft value that the check-node of last iteration passes to information node, and the check updating value in this iteration of transmitting of storage decoding processing module;
Second memory cell passes to the decoding processing module with the posterior probability likelihood ratio of information node, and the posterior probability likelihood ratio updating value of the information node that transmits of storage decoding processing module;
The number of described decoding processing module equals the degree of parallelism k of decoder; This deciphers processing module:
(1) the checksum update value of the last iteration that reads according to information node posterior probability likelihood ratio and first memory cell obtains the bit updating value of information node; For the heavy bigger check-node of row, after information node posterior probability likelihood ratio that reads out and checksum update value, insert and wait for the clock cycle;
(2) according to the bit updating value that passes to all information nodes of current check-node, calculate the checksum update value of this iteration, this checksum update value deposits first memory cell in; For the heavy bigger check-node of row, before the bit updating value of sense information node, insert and wait for the clock cycle;
(3) according to the bit updating value and the checksum update value of information node, the posterior probability likelihood ratio updating value of computing information node, pass to decoding processing module interleaving network after, deposit it in second memory cell;
Deciphering processing module simultaneously will decipher and declare the result firmly and export to iteration termination module interleaving network;
Decoding processing module interleaving network is responsible for adjusting the transmission sequence of posterior probability likelihood ratio updating value that the decoding processing module outputs to the information node of second memory cell;
What iteration termination module interleaving network was responsible for adjusting the output of decoding processing module declares the result firmly, and sends into the iteration termination processing module;
The iteration termination processing module is declared the result firmly to this and is carried out verification, judges whether to satisfy the condition of iteration termination.
2. the irregular low-density check code device of layering according to claim 1, it is characterized in that, described decoding processing module comprises: the one 2 selects 1 selector, bit information computing module, check-node information calculations module, information node posterior probability likelihood ratio computing module, wherein:
The one 2 selects 1 selector to select between the channel information and the information node posterior probability likelihood ratio of reading from second memory cell, and the result that will select exports to the bit information computing module as the information node posterior probability likelihood ratio of current iteration;
The bit updating value of bit information computing module computing information node passes to check-node information calculations module and information node posterior probability likelihood ratio computing module;
The bit updating value of the information node that the bit information computing module that check-node information calculations module basis receives is sent here is calculated the checksum update value of this iteration, and is passed to the information node posterior probability likelihood ratio computing module and first memory cell;
The checksum update value of this iteration that bit updating value that information node posterior probability likelihood ratio computing module transmits according to the bit information computing module and check-node information calculations module transmit is come computing information node posterior probability likelihood ratio updating value, and exports to second memory cell through decoding processing module interleaving network.
3. the irregular low-density check code device of layering according to claim 2, it is characterized in that, the described the 1 selects 1 selector that the data of input are selected, if this information node participates in decoding for the first time in decode procedure, selective channel information then, otherwise select the information node posterior probability likelihood ratio of from second memory cell, reading.
4. the irregular low-density check code device of layering according to claim 2 is characterized in that, described bit information computing module comprises: subtracter, the first complement code converter and the first cut position arithmetic unit, wherein:
Subtracter selects the checksum update value of the last iteration that the information node posterior probability likelihood ratio that 1 selector transmits and first memory cell read to subtract each other with the 1, obtains the information updating value of information node, passes to the first complement code transducer;
The first complement code transducer is converted to the numeral of sign bit-absolute value form with the information updating value of information node, and is transferred to the first cut position arithmetic unit;
The first cut position arithmetic unit carries out the cut position operation to the dateout of the first complement code transducer, bit wide is become the bit wide of original information node information of being scheduled to, become big situation to avoid in the process that adds up, occurring data bit width, promptly obtain the bit updating value of information node.
5. the irregular low-density check code device of layering according to claim 2, it is characterized in that, described check-node information calculations module, comprise: buffer, first comparator, first register, the 22 select 1 selector, second register, second comparator, multiplier, the second cut position arithmetic unit and the second complement code transducer, wherein:
Buffer is used to deposit the bit updating value of the information node that the bit information computing module transmits, and its length equals the number of the information node that links to each other with current check-node;
An input of first comparator is current bit updating value, another input is that check-node receives current minimum value and the current sub-minimum in the information, first comparator upgrades minimum value and the sub-minimum that check-node receives information according to these two inputs, first comparator carries out XOR respectively with the sign bit of current bit updating value and the sign bit of current minimum value and current sub-minimum simultaneously, as the sign bit that upgrades back minimum value and sub-minimum, the output of first comparator gives the 22 to select 1 selector by first register transfer; After the comparison of finishing RowWt data, the output of first comparator passes to second register, and all information nodes that link to each other with current check-node pass to minimum value and the sub-minimum in its information exactly; RowWt is that the row of the corresponding current check-node of check matrix is heavy;
The 22 to select the input of 1 selector be the output of first register, be used for the data of comparison as output according to current the selection relatively constantly, if current time, the bit updating value that passes to first comparator is first information of certain check-node, then the 22 select 1 selector to select 11 ... 1 as current minimum value and the output of current sub-minimum, and wherein 1 number equals the bit wide of data; Otherwise the 22 selects 1 selector to select the output of first register, passes to first comparator;
Second comparator receives the output of second register and the output of buffer, second comparator selective value from the result of check-node passes to information node, the concrete operations mode of second comparator is: when from the data of buffer and minimum value identical, second comparator is chosen sub-minimum, otherwise chooses minimum value; The sign bit of the value that second comparator also will be chosen out carries out XOR with sign bit from the data of buffer, obtains the sign bit of dateout, and the output of second comparator passes to multiplier;
Multiplier multiply by a constant with the output of second comparator, this constant obtains by software emulation, the output of multiplier is again by the second cut position arithmetic unit, the bit wide of verification updating value is retrained within the specific limits, again through the second complement code transducer, obtain the checksum update value of final this iteration afterwards.
6. the irregular low-density check code device of layering according to claim 2 is characterized in that, described information node posterior probability likelihood ratio computing module comprises: the 3rd complement code transducer, adder, wherein:
The buffer that the 3rd complement code transducer receives in the check-node information calculations module transmits data, and the data of symbol-absolute value form are converted to complement form;
The checksum update value addition of this iteration that adder transmits the output and the check-node information calculations module of the 3rd complement code transducer, obtain information node posterior probability likelihood ratio updating value, pass to decoding processing module interleaving network, the sign bit of information node posterior probability likelihood ratio updating value passes to iteration termination module interleaving network as declaring the result firmly simultaneously.
7. the irregular low-density check code device of layering according to claim 1, it is characterized in that, described iteration termination processing module comprises: the 3rd register, the 4th register, the 5th register, the 3rd comparator, the 32 select 1 selector, accumulator and the 4th comparator, wherein:
The k that the 3rd register is sent iteration termination module interleaving network here declares the result than ultrahard and stores, and passes to the 3rd comparator then;
The 32 selects 1 selector to be used for the data of comparison as output according to current the selection relatively constantly, if current time, what pass to the 3rd comparator declares first information that the result is the check equations that comprises of certain submatrix firmly, then the 32 select 1 selector to select 00 ... 0 as output, wherein 0 number equals the degree of parallelism k of decoder, otherwise the 32 selects 1 selector to select the output of the 4th register, pass to the 3rd comparator, after the comparison of finishing RowWt data, the output of the 3rd comparator passes to the 5th register, the check results of the check equations that current submatrix comprises that Here it is; RowWt is that the row of the corresponding current check-node of check matrix is heavy;
The 3rd comparator is according to two inputs, upgrade the check results of the check equations that current submatrix comprises, if the data of two inputs of the 3rd comparator are identical, the check results of the check equations that corresponding submatrix comprises is 0, otherwise the comparative result that is 1, the three comparator gives the 32 to select 1 selector by the 4th register transfer;
The 5th register is exported to accumulator with the check results of storage;
Accumulator is used to add up the number that check results is 0 submatrix, and after the check results of all submatrixs all obtained, the result that accumulator will be added up exported to the 4th comparator;
Another input of the 4th comparator is the number of the submatrix of check matrix, if two inputs of the 4th comparator are identical, illustrate that then all submatrixs all satisfy, be that decode procedure has been deciphered the code word that obtains restraining, then making control signal is 1, end the work of decoding processing module, otherwise control signal is changed to 0.
8. the irregular low-density check code processing method of a layering is characterized in that, may further comprise the steps:
Step 1, the input data or the channel value of acquisition decoder;
Step 2, the one 2 selects 1 selector that the input data of information node posterior probability likelihood ratio are selected, if this information node participates in decoding for the first time in decode procedure, then selective channel information is as information node posterior probability likelihood ratio, otherwise the data of reading from second memory cell pass to the decoding processing module as the information node posterior probability likelihood ratio of current iteration;
Step 3, reading the soft value that check-node the last iteration passes to information node from first memory cell is the checksum update value, passes to the decoding processing module;
Step 4, the decoding processing module reads out the one 2 checksum update value of selecting the last iteration that the information node posterior probability likelihood ratio that 1 selector transmits and first memory cell read, obtain the bit updating value of information node, pass to check-node information calculations module, for the heavy bigger check-node of row, the decoding processing module is inserted after information node posterior probability likelihood ratio that reads out and checksum update value and is waited for the clock cycle;
Step 5, check-node information calculations module are calculated the checksum update value of this iteration according to the bit updating value that passes to all information nodes of current check-node, and this checksum update value deposits first memory cell in; For the heavy bigger check-node of row, before the bit updating value of check-node information calculations module sense information node, insert and wait for the clock cycle;
Step 6, utilize the 4th bit updating value and the 5th that goes on foot the information node that calculates to go on foot the checksum update value of this iteration that calculates, the posterior probability likelihood ratio updating value of computing information node, after passing to decoding processing module interleaving network, deposit it in second memory cell, the sign bit of information node posterior probability likelihood ratio updating value passes to iteration termination module interleaving network as declaring the result firmly simultaneously;
Step 7, the data of iteration termination module interleaving network output are sent into the iteration termination processing module and are carried out the iteration termination processing, judge whether iterations reaches preset value or whether satisfy the iteration termination condition, if iterations reaches preset value or satisfies the iteration termination condition, then operation stops, otherwise, return second step beginning next iteration.
9. the irregular low-density check code processing method of layering according to claim 8 is characterized in that, the described insertion after information node posterior probability likelihood ratio that reads out and checksum update value waited for the clock cycle, is specially:
When the processing row heavily is the information node of RowWt1, when reading the checksum update value of corresponding RowWt1 last iteration and RowWt1 information node posterior probability likelihood ratio from first memory cell and second memory cell, need insert (RowWt1-RowWt2) individual wait clock cycle in the back of checksum update value and information node posterior probability likelihood ratio, these data are through subtracter, the first complement code transducer, the first cut position arithmetic unit is sent into check-node information calculations module, wherein, RowWt0 and RowWt2 are that the row of adjacent two check-nodes is heavy, RowWt1 more than or equal to RowWt0 simultaneously also more than or equal to RowWt2.
10. the irregular low-density check code processing method of layering according to claim 8, it is characterized in that, described before the bit updating value of check-node information calculations module sense information node, insert and wait for the clock cycle, specific as follows: when calculating the checksum update value of this iteration, read row heavily before the bit updating value for the relevant information node of the check-node of RowWt1 from buffer, insert (RowWt1-RowWt0) individual wait clock cycle, wherein, RowWt0 and RowWt2 are that the row of adjacent two check-nodes is heavy, RowWt1 more than or equal to RowWt0 simultaneously also more than or equal to RowWt2.
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| CN102394661B (en) * | 2011-11-08 | 2015-05-06 | 北京邮电大学 | LDPC (low density parity check) decoder and decoding method based on layer decoding processing |
| CN103973316B (en) * | 2013-02-04 | 2017-08-08 | 爱思开海力士有限公司 | Coding/decoding method with the variable node renovator using scaling constant conciliates code system |
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