CN113590377A

CN113590377A - Decoding device, decoding method, storage medium and computer equipment

Info

Publication number: CN113590377A
Application number: CN202110812128.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2021-07-16
Filing date: 2021-07-16
Publication date: 2021-11-02

Abstract

The application discloses a decoding device, a decoding method, a storage medium and computer equipment. The decoding device includes: the first storage unit is used for storing a base matrix of a plurality of check matrixes with different cycle lengths aiming at different code lengths; the data selector is used for selecting a target base matrix from the first storage unit according to the code length of the code word to be decoded; the first displacement circuit is respectively connected with the first storage unit and the data selector and is used for receiving the target base matrix read from the first storage unit in a layering manner and translating the unit matrix in a first direction to obtain a target check matrix; and the second shift circuit is used for carrying out shift in a second direction on the sum of the current values of the amplitudes to be updated of the variable nodes and the information update values sent by the current check node to the variable nodes connected with the current check node according to the target basis matrix so as to obtain the log-likelihood ratio update values of the variable nodes. The method and the device can reduce the error rate and improve the error correction capability of the code words.

Description

Decoding device, decoding method, storage medium and computer equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a decoding apparatus, a decoding method, a storage medium, and a computer device.

Background

With the development of technology, flash memory devices such as data storage flash (NAND FLASH) are becoming more widely used. The redundancy spaces (Runtant Space) provided by different manufacturers of data storage flash memory (NAND FLASH) are different, i.e., the code length and code rate of the code are different. In the related art, error correction can be performed by using a Low Density Parity Check Code (LDPC) with the same H structure, that is, error correction is performed by using the same Check matrix for codewords with different Code lengths. During Error correction, 0 is supplemented to code words with shorter code length or code bits of codes with the longest code length to decode different FLASH, but the original Bit Error Rate (RBER) is higher, and the Error correction capability of the code words is reduced.

Disclosure of Invention

In view of this, the present application provides a decoding apparatus, a decoding method, a storage medium, and a computer device to solve the problems of the existing scheme, such as high error rate and reduced capability of correcting and correcting code words.

In a first aspect, an embodiment of the present application provides a decoding apparatus, including:

a first storage unit configured to store a base matrix of a plurality of check matrices of different cycle lengths (cyclic sizes) for different code lengths;

the data selector is connected with the first storage unit and used for selecting a corresponding target base matrix from the first storage unit according to the code length of the code word to be decoded;

the first displacement circuit is respectively connected with the first storage unit and the data selector and is used for receiving the target base matrix read from the first storage unit in a layered mode and translating an identity matrix (index martrix) in a first direction according to the target base matrix to obtain a target check matrix;

the second storage unit is used for storing the current information values sent by the current check node of the target check matrix to the variable nodes connected with the current check node;

the third storage unit is connected with the second storage unit and used for storing the current values of the amplitudes to be updated of the variable nodes;

a second shift circuit, connected to the first storage unit, the second storage unit, and the third storage unit, respectively, and configured to receive the target base matrix read from the first storage unit in a layered manner, and perform a shift in a second direction on a sum of current values of to-be-updated amplitudes of the variable nodes and information update values sent by the current check node to the variable nodes connected to the current check node according to the target base matrix, so as to obtain log-likelihood ratio update values of the variable nodes;

and a fourth storage unit connected to the first shift circuit and the second shift circuit, respectively, for storing log likelihood ratio update values of the plurality of variable nodes.

Optionally, the translation in the first direction is a right movement, and the translation in the second direction is a left movement.

Optionally, the check matrix includes a plurality of sub-matrices, and a plurality of displacement values of the plurality of sub-matrices with respect to the identity matrix form the base matrix.

Optionally, the first storage unit includes a Read Only Memory (ROM), and the first shift circuit is further configured to receive the target basis matrix Read from the ROM in a hierarchical manner, and right shift the identity matrix according to a plurality of shift values in the target basis matrix, so as to obtain the target check matrix.

Optionally, the decoding apparatus further includes:

and the subtracter is respectively connected with the first displacement circuit and the second storage unit and is used for correspondingly subtracting the current log-likelihood ratios of the variable nodes and the current information values sent by the current check node to the variable nodes connected with the current check node to obtain the current values of the amplitudes to be updated of the variable nodes.

Optionally, the third storage unit is further configured to calculate information update values sent by the current check node to the variable nodes connected to the current check node, and send the information update values sent by the current check node to the variable nodes connected to the current check node to the second storage unit for storage.

Optionally, the third storage unit is further configured to calculate symbol function value update values and amplitude update values of the multiple variable nodes, and obtain, according to the symbol function value update values and the amplitude update values of the multiple variable nodes, information update values sent by the current check node to the multiple variable nodes connected to the current check node.

Optionally, the symbol function value update values and the amplitude update values of the plurality of variable nodes are obtained according to amplitude current values to be updated of other variable nodes except the target variable node in the plurality of variable nodes connected to the current check node.

Optionally, the decoding apparatus further includes:

and the adder is respectively connected with the second storage unit, the third storage unit and the second displacement circuit and is used for correspondingly adding the current values of the amplitudes to be updated of the variable nodes and the information update values sent by the current check node to the variable nodes connected with the current check node.

Optionally, the adder is further configured to, after delaying for a preset time, perform corresponding addition on the current values of the amplitudes to be updated of the plurality of variable nodes and the information update values sent by the current check node to the plurality of variable nodes connected thereto, where the preset time is equal to or longer than a storage time occupied by the third storage unit to store the current values of the amplitudes to be updated of the plurality of variable nodes.

Optionally, the first shift circuit, the second shift circuit and the identity matrix have the same size.

In a second aspect, an embodiment of the present application provides a decoding method, including:

providing a decoding device according to any one of the above;

designing a plurality of check matrixes with different cycle lengths aiming at different code lengths;

writing the base matrixes of the check matrixes with different cycle lengths into different address areas of a first storage unit;

the data selector selects a target base matrix corresponding to the code length from the first storage unit according to the code length of the code word to be decoded;

the first displacement circuit receives the target base matrix read from the first storage unit in a layered mode, and conducts first-direction translation on the identity matrix according to the target base matrix to obtain a target check matrix;

and decoding the code word to be decoded based on the target check matrix.

Optionally, the decoding the codeword to be decoded based on the target check matrix includes:

reading the current information values of a plurality of variable nodes connected with the current check node of the target check matrix from a second storage unit;

respectively and correspondingly subtracting the current values of the log-likelihood ratios of the variable nodes and the current values of the information sent by the current check node to the variable nodes connected with the current check node to obtain current values of the amplitudes to be updated of the variable nodes, and storing the current values of the amplitudes to be updated of the variable nodes in a third storage unit;

reading information updating values sent by the current check node to a plurality of variable nodes connected with the current check node from the second storage unit;

adding the current values of the amplitudes to be updated of the variable nodes and the information update values sent by the current check node to the variable nodes connected with the current check node;

a second shift circuit receives the target base matrix read from the first storage unit in a layered mode, and according to the target base matrix, the sum of the current values of the amplitudes to be updated of the variable nodes and the information update values sent by the current check node to the variable nodes connected with the current check node is translated in a second direction, so that log-likelihood ratio update values of the variable nodes are obtained;

storing the log-likelihood ratio update values of the plurality of variable nodes in a fourth storage unit;

and generating a decoding result according to the log-likelihood ratio update values of the variable nodes, and determining whether decoding is successful according to the decoding result.

Optionally, the method further includes:

and if the current times of decoding iteration reaches the preset maximum iteration times, ending the decoding.

In a third aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed on a computer, the computer program is enabled to execute the procedures in the decoding method provided by the embodiment of the present application.

In a fifth aspect, an embodiment of the present application provides a computer device, which includes a memory and a processor, where the processor executes a flow in the decoding method provided by the embodiment of the present application by calling a computer program stored in the memory.

In the decoding apparatus, the decoding method, the storage medium, and the computer device according to the embodiments of the present application, the first storage unit is configured to store a base matrix of a plurality of check matrices with different cycle lengths for different code lengths; the data selector is used for selecting a target base matrix corresponding to the code length from the first storage unit according to the code length of the code word to be decoded; the first shift circuit is used for receiving the target base matrix read from the first storage unit in a layered mode and performing first-direction translation on the unit matrix according to the target base matrix to obtain a target check matrix. A plurality of check matrixes aiming at different code lengths are designed, a base matrix of each check matrix is stored in a first storage unit, a target base matrix corresponding to the code length to be decoded is read from a corresponding address area of the first storage unit, and the identity matrix is translated according to the value of the target base matrix to obtain the target check matrix. Because different code lengths do not adopt a method of 0 complementing for different check matrixes, and different check matrixes use the same displacement circuit, the error rate can be reduced, and the error correction capability of the code words can be improved.

Drawings

The technical solutions and advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.

FIG. 1 is a flow chart of a decoding method in the related art;

FIG. 2 is a diagram illustrating error correction capability curves obtained by using a 0-complementing method for different code lengths in the related art;

FIG. 3 is a schematic structural diagram of a decoding apparatus according to an embodiment of the present application;

FIG. 4 is a schematic diagram of right shifting an identity matrix provided by an embodiment of the present application;

fig. 5 is a schematic structural diagram of a check matrix provided in an embodiment of the present application;

fig. 6 is a schematic structural diagram of an identity matrix of a check matrix provided in an embodiment of the present application;

fig. 7 is a schematic structural diagram of a base matrix of a check matrix provided in an embodiment of the present application;

fig. 8 is a Tanner schematic diagram of a check matrix provided in an embodiment of the present application;

FIG. 9 is a diagram illustrating a structure of an LDPC layered decoder using a min-sum algorithm (min-sum algorithm) in the related art;

FIG. 10 is a flowchart illustrating a decoding method according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a computer device provided in an embodiment of the present application.

Detailed Description

Referring to the drawings, wherein like reference numbers refer to like elements, the principles of the present application are illustrated as being implemented in a suitable computing environment. The following description is based on illustrated embodiments of the application and should not be taken as limiting the application with respect to other embodiments that are not detailed herein.

With the development of technology, flash memory devices such as data storage flash memory are increasingly used. The redundancy spaces provided by different manufacturers of flash memories are different, i.e. the code length and code rate of the codes are different. In the related art, the error correction can be performed by using a low density parity check code with the same H structure, that is, the error correction can be performed by using the same check matrix for codewords with different code lengths.

Referring to fig. 1, fig. 1 is a flow chart illustrating a decoding method in the related art. The decoding method comprises the following steps: designing an H matrix which can be used for 7 code lengths; for different FLASH manufacturers, the same cycle length is used for complementing 0 to code words with shorter code length or code bits which are insufficient to longest codes; reading the same shift value (shift value shifted left or right) from the ROM; inputting the read right shift value into a shift circuit, wherein the shift circuit can be a Barrel shift circuit (Barrel shift); after decoding, different code word correcting capabilities are obtained for FLASH of different manufacturers. Because the same check matrix is adopted for different code lengths, namely the same H matrix is adopted for different code lengths, and a 0 complementing mode is adopted, the error correction capability of the LDPC code with the short code length is poor.

Referring to fig. 2, fig. 2 is a schematic diagram of an error correction capability curve obtained by complementing 0 for different code lengths in the related art. In fig. 2, the abscissa is Error bits (errors) that can be corrected, the ordinate is Bit Error Rate (BER), and the BER is the number of Error bits divided by the total number of bits transmitted over a period of time. In fig. 2, the error correction capability curve of the LDPC code having a code length of 1104 Bytes (Bytes), 1110 Bytes, 1128 Bytes, 1140 Bytes, 1146 Bytes, 1152 Bytes, and 1160 Bytes is shown in the order from left to right. In fig. 2, the legend portion is a legend of error correction capability curves of LDPC codes of 1104 bytes, 1110 bytes, 1128 bytes, 1140 bytes, 1146 bytes, 1152 bytes, and 1160 bytes in this order from bottom to top.

Specifically, the rightmost side is an error correction capability curve of an LDPC code having a code length of 1160 bytes, and the remaining curves are error correction capability curves of LDPC codes having a code length of 1104 bytes, 1110 bytes, 1128 bytes, 1140 bytes, 1146 bytes, 1152 bytes, which is complemented by 0 to 1160 bytes. Under the condition of the same error rate, the correction capability (namely, the error correction capability) of the 1160-byte LDPC code is the strongest, and the number of bits capable of correcting error bits is the largest. And the code length of 1104 bytes, 1110 bytes, 1128 bytes, 1140 bytes, 1146 bytes and 1152 bytes reduces the amount of data by complementing 1160 bytes with 0, resulting in a reduction in the correction capability. It is understood that the more the number of bits of 0 complement, the weaker the error correction capability of the codeword.

Therefore, in the related art, when the error correction is more correct, 0 is supplemented to the code word with a shorter code length or the code bit of the code less than the longest code to decode different FLASH, but this results in a higher original bit error rate and a reduced error correction capability of the code word. In addition, in the related art, each submatrix in the check matrix has its own shift circuit, that is, different submatrixes have their own shift circuits with different structures, and when the number of the submatrixes is large, many shift circuits need to be designed, which results in complex circuit design, increased volume of the decoder, and increased design cost.

In order to solve the above problem, an embodiment of the present application provides a decoding apparatus, where the decoding apparatus designs different check matrices for different code lengths to submit error correction capability of a codeword to be decoded.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a decoding device according to an embodiment of the present disclosure. The decoding apparatus includes a first memory cell 101, a data selector 102, a first shift circuit 103, a second memory cell 104, a third memory cell 105, a second shift circuit 106, and a fourth memory cell 107.

The first storage unit 101 is configured to store a base matrix of a plurality of check matrices with different cycle lengths for different code lengths. In the embodiment of the application, the check matrixes with different code rates can be designed according to different code lengths. For example, when there are 7 different code lengths, check matrices of 7 different code rates may be designed. By designing check matrixes with different code rates according to different code lengths, the number of data is not reduced, and therefore the error correction capability of the code words can be improved.

For example, in one embodiment, the check matrix includes a plurality of sub-matrices that form a basis matrix with respect to a plurality of shift values of the identity matrix. Specifically, the check matrix is divided into a plurality of sub-matrices, each sub-matrix is a square matrix, the size of each sub-matrix is the same, and the displacement value of each sub-matrix relative to the identity matrix can form a basis matrix.

In the embodiment of the present application, each check matrix is a rightward shift of the identity matrix.

Referring to fig. 4, fig. 4 is a schematic diagram of shifting the unit matrix to the right according to the embodiment of the present application. The identity matrix is represented by 0, the identity matrix is shifted to the right by 1 bit, represented by 1, the identity matrix is shifted to the right by 2 bits, represented by 2, and so on, the identity matrix is shifted to the right by n bits, represented by n, n being an integer greater than 0, i.e. the number represents the number of bits that the sub-matrix is shifted to the right relative to the identity matrix. In the embodiment of the present application, all 0 sub-matrices are represented by-1.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a check matrix according to an embodiment of the present disclosure. The structure of the check matrix in fig. 5 is described as an example, and the check matrix includes 18 sub-matrices, and the size of each sub-matrix is 5 × 5. This is equivalent to dividing the check matrix into 18 regions, each region being a 5 × 5 sub-matrix. Row 2 of each sub-matrix is a shift of row 1 to the right, and so on. The displacement of the 1 st row of the submatrix relative to the identity matrix in the check matrix is 0, 2, 1, 0, the displacement of 0 indicates that the submatrix is the identity matrix, the displacement of the 2 nd row of the submatrix relative to the identity matrix is 3, 4, 0, 2, 1, 0, the 1 st submatrix in the 3 rd row of the submatrix is a full 0 matrix, and the displacement of the rest of the submatrix relative to the identity matrix is 1, 2, 3, 1.

From the displacements of the sub-matrices relative to the identity matrix, a base matrix can be constructed, each element in the base matrix being the number of translations of each sub-matrix relative to the identity matrix. Referring to fig. 6, fig. 6 is a schematic structural diagram of an identity matrix of a check matrix according to an embodiment of the present disclosure. The identity matrix is a 5 × 5 square matrix.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a base matrix of a check matrix provided in the embodiment of the present application, where the size of the base matrix of the check matrix may be 3 × 6, and the cycle length may be 5. Each sub-matrix is obtained by translating the unit matrix and can be realized by using a barrel type displacement circuit.

It can be understood that, with different check matrices, the sizes of the corresponding base matrix and the corresponding identity matrix may also change correspondingly, and the size of the check matrix is not particularly limited in the embodiments of the present application. By storing the base matrix in the first storage unit 101 instead of directly storing the check matrix, the occupied storage space of the first storage unit 101 is reduced, and the storage space is saved.

The data selector 102 is connected to the first storage unit 101, and is configured to select a corresponding target base matrix from the first storage unit 101 according to a code length of a codeword to be decoded. The data selector 102 is a multiplexer, and the multiplexer can select any one of the paths according to the requirement in the multi-path data transmission process. In this embodiment, the data selector 102 may select a target base matrix from the plurality of base matrices stored in the first storage unit 101 according to the code length of the codeword to be decoded. Because the code lengths and code rates of the codes provided by different FLASH manufacturers are different, for the code length of the current codeword to be decoded, one base matrix corresponding to the code length of the current codeword to be decoded can be selected from the plurality of base matrices stored in the first storage unit 101, and the base matrix corresponding to the code length of the current codeword to be decoded is the target base matrix.

The first shift circuit 103 is connected to the first storage unit 101 and the data selector 102, respectively, and is configured to receive the target base matrix read from the first storage unit 101 in a layered manner, and perform a first-direction shift on the identity matrix according to the target base matrix to obtain a target check matrix. For example, in one embodiment, the translation in the first direction may be a right shift. Firmware (Firmware) in the FLASH will read the corresponding target base matrix from the first storage unit 101 for different FLASH manufacturers. When the firmware reads the target base matrix from the first storage unit 101, a layered reading mode may be adopted, where each row in the target base matrix is a layer, in other words, when reading the target base matrix, reading is performed row by row. The firmware feeds the hierarchically read target basis matrices to the first shift circuit 103.

If the row number of the target base matrix is 3, the target base matrix is divided into 3 layers. For example, after the firmware reads the shift value of the layer 1 of the target base matrix, the read shift value of the layer 1 is sent to the first shift circuit 103, and the unit matrix is shifted to the right in the first shift circuit 103 according to the shift value of the layer 1. After the firmware reads the displacement value of the 2 nd layer of the target base matrix, the read displacement value of the 2 nd layer is sent to the first displacement circuit 103, the unit matrix is shifted to the right in the first displacement circuit 103 according to the displacement value of the 2 nd layer, and so on, after the firmware reads the displacement value of the 3 rd layer of the target base matrix, the read displacement value of the 3 rd layer is sent to the first displacement circuit 103, and the unit matrix is shifted to the right in the first displacement circuit 103 according to the displacement value of the 3 rd layer.

For example, in one embodiment, the first storage unit 101 may include a read-only Memory (ROM), which may be a Mask-programmed ROM (MROM), a Programmable ROM (PROM), an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), or a Flash Memory, etc.

When the base matrices corresponding to different check matrices are stored in the ROM, the requirements of different check matrices on the ROM storage space are different. Taking an Error Correction Code (ECC) of 1K as an example, when data bit + check bit is 1160 Bytes (Bytes) ═ 9280 bits (bits), if a check matrix with a size of 4 × 40 is designed, where the cycle length of each sub-matrix is 232, the number of variable nodes is 232 × 40 ═ 9280, and the number of check nodes is 232 × 4 ═ 928, this is a check Code with a (n, K) ═ 9280,8352 and a Code rate of 9/10. Where n is the length of the transmitted codeword and k is the length of the information bit.

For example, if the size of the base matrix is 4 × 40, the minimum memory space of the ROM is 160 bytes. Can be calculated by: due to 2⁷＝128，2⁸＝256，2⁷＜232＜2⁸When 232 is stored in the ROM, the binary system is used for storing 232, the binary system corresponding to 128 is 10000000, the binary system corresponding to 256 is 100000000, 8 bits are needed for storing 128, and 9 bits are needed for storing 256, since 232 is located between 128 and 256, 8 bits are needed for storing 232, and 8 bits are one byte, so that the minimum storage space of the ROM required by the base matrix with the size of 4 × 40 is 4 × 40 bytes, i.e., 160 bytes.

For another example, if a check matrix with a size of 8 × 80 is designed, where the cycle length of each sub-matrix is 116, the number of variable nodes is 116 × 80-9280, and the number of check nodes is 116 × 8-928, this is a check code with a (n, k) ═ 9280,8352 and a code rate of 9/10. Where n is the length of the transmitted codeword and k is the length of the information bit.

The size of the base matrix is 8 x 80, requiring a minimum memory space of 560 bytes of ROM. Can be calculated by: due to 2⁶＝64，2⁷＝128，2⁶＜116＜2⁷When storing 116 into the ROM, the binary system is used for storing, the binary system corresponding to 64 is 1000000, the binary system corresponding to 128 is 10000000, 7 bits are required for storing 64, 8 bits are required for storing 128, and since 116 is located between 64 and 128, 7 bits are required for storing 116, and therefore the minimum storage space of the ROM required by the base matrix with the size of 8 × 80 is 8 × 80 × 7 ÷ 8 bytes, namely 560 bytes.

The first shift circuit 103 may be further configured to receive a target base matrix read by the firmware from the rom in a hierarchical manner, and shift the identity matrix to the right according to a plurality of shift values in the target base matrix to obtain a target check matrix. Namely, the firmware reads the target base matrix from the read-only memory in a layering way and respectively shifts the unit matrix to the right according to the displacement value of each layer in the target base matrix. The advantages of using a ROM memory base matrix are: the data stored in the ROM is relatively stable, the stored data cannot be changed when the power supply is cut off, the structure of the ROM is simple, and the data can be read simply, conveniently and quickly.

It can be understood that, in another embodiment, according to specific requirements, the first storage unit 101 may include a Random Access Memory (RAM), and the RAM can be read and written at any time, and the reading and writing speed is fast, so that data reading is simple, fast, and data writing function is provided, which can meet application scenarios with reading and writing requirements.

The second storage unit 104 is configured to store current values of information sent by a current check node of the target check matrix to a plurality of variable nodes connected thereto. If the target check matrix is an m × n matrix, and the target check matrix is represented by a Tanner graph, the number of check nodes in the Tanner graph (represented by the Tanner graph) is m, and the number of variable nodes is n. The Tanner graph represents a check matrix. For example, if the target check matrix is a 4 × 6 matrix, please refer to fig. 8, and fig. 8 is a Tanner schematic diagram of the check matrix according to the embodiment of the present application. The number of check nodes is 4, and the number of variable nodes is 6. The 4 check nodes are denoted as c1, c2, c3, c4, and the 6 variable nodes are denoted as v1, v2, v3, v4, v5, v 6. The element of 1 in the target check matrix, and the corresponding check node is connected with the variable node. For example, if the elements in the row 3, column 1, row 3, column 5 and row 3, column 6 in the target check matrix are all 1, it indicates that the check node c3 is connected to the variable nodes v1, v5 and v6, respectively.

If the current layer is the layer 3, the current check node is c3, and the second storage unit 104 may store the current value of the information sent by the check node c3 on the layer 3 to the variable nodes v1, v5, and v 6.

In the embodiment of the application, the l-th layer is used as the current layer, the l + 1-th layer is used as the next layer, and the jth check node is used as the current check node

And the current information value of the jth check node on the ith layer sent to the ith variable node connected with the jth check node is represented.

The third storage unit 105 is connected to the second storage unit 104, and is configured to store current values of the amplitudes to be updated of a plurality of variable nodes (i.e., each variable node connected to the current check node). For example, the third storage unit 105 may store the amplitude value to be updated of each variable node connected to the current check node on the current layer. Can use

And representing the current value of the amplitude to be updated of the ith variable node connected with the jth check node on the ith layer.

For example, in one embodiment, the third storage unit 105 may also be used to calculate the number of variable nodes (each variable node connected to the current check node) to which the current check node is sentPoint) and sends the information update value sent by the current check node to the plurality of variable nodes connected thereto to the second storage unit 104 for storage. Can use

And the information updating value which represents that the jth check node on the l +1 th layer sends to the ith variable node connected with the jth check node is updated. The third storage unit 105 may calculate updated information values sent by the jth check node on the l +1 th layer to the variable nodes connected thereto, and send the updated information values to the second storage unit 104 for storage.

For example, in an embodiment, the third storage unit 105 may be further configured to calculate a symbol function value update value and an amplitude update value of a plurality of variable nodes, and obtain, according to the symbol function value update value and the amplitude update value of the plurality of variable nodes, an information update value sent by the current check node to the plurality of variable nodes connected thereto. The symbol function value updating values and the amplitude updating values of the variable nodes are obtained according to amplitude current values to be updated of other variable nodes except the target variable node in the variable nodes connected with the current check node.

For example, using

Represents the updated value of the symbol function value of the ith variable node on the l layer, wherein sgn () represents the symbol operation with the value of +1 or-1, and II sgn () is the total product of the symbol function values, V_j\ i represents a set of all variable nodes connected to the jth check node except the ith variable node. It can be understood that the symbol function value update value of the ith variable node connected to the jth check node

The symbol function value of the current value of the amplitude to be updated of all other variable nodes except the ith variable node and connected with the jth check node

The product of (a).

By using

And representing the amplitude update value of the ith variable node connected with the jth check node on the ith layer. Wherein the content of the first and second substances,

in the calculation of

And then, except for the ith variable node, the minimum value in the absolute values of the current values of the amplitudes to be updated of all other variable nodes connected with the jth check node.

The absolute values of the amplitude current values to be updated of all variable nodes connected with the jth check node on the ith layer can be calculated, and the minimum two values are determined in all the absolute values and are respectively the minimum value and the second minimum value, wherein the minimum value is smaller than the second minimum value. Comparing the absolute value of the current value of the amplitude to be updated of the ith variable node with the minimum value and the second minimum value to obtain the minimum value, assigning the minimum value to the minimum value, and calculating the amplitude update value of the ith variable node connected with the jth check node on the ith layer according to the minimum value

Obtaining the information update values sent by the current check node to the variable nodes connected with the current check node according to the symbol function value update values and the amplitude update values of the variable nodes, namely according to the symbol function value update values and the amplitude update values of the variable nodes

And

obtaining the information updating value sent to the ith variable node by the (l + 1) th layer and the jth check node

The second shift circuit 106 is connected to the first storage unit 101, the second storage unit 104, and the third storage unit 105, respectively, and is configured to receive a target base matrix read by the firmware from the first storage unit 101 in a hierarchical manner, that is, read the target base matrix row by row, and perform a shift in a second direction according to a sum of current values of amplitudes to be updated of the variable nodes and information update values sent by a current check node to the variable nodes connected to the current check node, so as to obtain log-likelihood ratio update values of the variable nodes.

For example, in one embodiment, the translation in the second direction may be a left translation. Current value of amplitude to be updated of ith variable node connected with jth check node on ith layer

And the information updating value sent to the ith variable node by the jth check node on the l +1 th layer

After the addition, the second shift circuit 106 may receive a target base matrix read by the firmware from the first storage unit 101 in a hierarchical manner, and shift the sum left according to a shift value in the target base matrix to obtain a log likelihood ratio update value of the ith variable node on the l +1 th layer

For example, in one embodiment, the first shift circuit 103, the second shift circuit 106, and the identity matrix are the same size. That is, the number of rows and columns of the first shift circuit 103, the second shift circuit 106, and the unit matrix are the same. Since the matrix sizes of the first shift circuit 103 and the second shift circuit 106 are designed, the size of the unit matrix can be obtained according to the matrix size of the first shift circuit 103 or the second shift circuit 106, so that the unit matrix can be obtained, and therefore, the unit matrix does not need to be stored in the first memory cell 101, so as to further save the storage space of the first memory cell 101.

A fourth storage unit 107 is connected to the first shift circuit 103 and the second shift circuit 106, respectively, and is used for storing log likelihood ratio update values of a plurality of variable nodes, for example, storing log likelihood ratio update values of the ith variable node on the l +1 th layer

It should be noted that In the embodiment of the present application, the second storage unit 104, the third storage unit 105, and the fourth storage unit 107 may employ a memory, such as a RAM, a First In First Out (FIFO), a memory bank, a flash memory Card (Trans-flash Card), and the like.

It can be understood that, in the embodiment of the present application, the first storage unit 101 is used to store the base matrices of the check matrices with different code rates, and in terms of hardware implementation, the shift value of the base matrix of the corresponding address area in the first storage unit 101 is read, and after the unit matrix is shifted according to the shift value, the check matrix with the corresponding code length can be obtained. By adopting the check matrixes with different code rates, the error rate is lower and the error correction capability is better than that of a mode of using the same check matrix to complement 0 in the related technology, so that the error rate can be reduced and the error correction capability of the code word can be improved.

In addition, in the embodiment of the present application, only the first storage unit 101 is required to record the base matrix of the check matrix, the displacement value in the base matrix is input to the first displacement circuit 103, and the corresponding check matrix can be obtained after the unit matrix is translated according to the displacement value. And aiming at the check matrixes with different code lengths, the same set of displacement circuits are used, namely the check matrixes with different code lengths use the displacement circuits (the first displacement circuit 103 and the second displacement circuit 106) with the same set of structure, so that the circuit design can be simplified, the size of a decoding device is reduced, and the design cost is reduced.

In the related art, an LDPC layered decoder adopting a minimum sum algorithm is used for decoding. For check matrixes with different code lengths, each sub-matrix of the check matrix needs a corresponding displacement circuit, so that N sets of displacement circuits (N right-shift circuits and N left-shift circuits) are needed, and N is the row weight of the check matrix. For example, as shown in fig. 9, fig. 9 is a schematic structural diagram of an LDPC layered decoder employing a minimum sum algorithm in the related art. For 7 check matrixes with different code lengths, 7 sets of shift circuits (7 right shift circuits and 7 left shift circuits) are needed, namely 7 different check matrixes need 7 sets of shift circuits with different structures, the circuit design is complex, the size of the LDPC layered decoder is increased, and the design cost is increased. R in fig. 9 represents an information value sent by the check node to the variable node, Q represents an amplitude value to be updated of the variable node connected to the check node, and CNU represents a storage unit for storing the amplitude value to be updated of the variable node connected to the check node, and Λ represents a log likelihood ratio of the variable node.

For example, in the embodiment of the present application, please refer to the decoding apparatus in fig. 3, a shift value of each sub-matrix with respect to the identity matrix is recorded in the first storage unit 101, and the identity matrix is shifted according to the shift value by using the same set of shift circuits (the first shift circuit 103 and the second shift circuit 106), so as to obtain the check matrix. Compared with the LDPC layered decoder adopting the minimum sum algorithm in the related art, the decoding device in the embodiment of the application only needs to use one set of displacement circuit, so that the embodiment of the application can simplify the circuit design, reduce the volume of the decoding device and reduce the design cost.

For example, in an embodiment, the decoding apparatus may further include subtracters 108, where the subtracters 108 are respectively connected to the first displacement circuit 103 and the second storage unit 104, and are configured to perform corresponding subtraction on current values of log-likelihood ratios of the variable nodes and current values of information sent by the current check node to the variable nodes connected thereto, respectively, so as to obtain current values of amplitudes to be updated of the variable nodes. For example, the log-likelihood ratio of the ith variable node on the ith layer may be set in subtractor 108

The current information value sent to the ith variable node connected with the jth check node on the ith layer

Subtracting to obtain the current value of the amplitude to be updated of the ith variable node connected with the jth check node on the ith layer

Obtained

May be stored in the third storage unit 105.

For example, in an embodiment, the decoding apparatus may further include an adder 109, where the adder 109 is respectively connected to the second storage unit 104, the third storage unit 105, and the second shift circuit 106, and is configured to correspondingly add the current values of the amplitudes to be updated of the variable nodes and the updated values of the information sent by the current check node to the variable nodes connected thereto. For example, the current value of the amplitude to be updated of the ith variable node connected to the jth check node on the ith layer may be added in adder 109

Adding to obtain updated log likelihood ratio value of ith variable node on the l +1 th layer

For example, in an embodiment, the adder 109 is further configured to perform corresponding addition on the current values of the to-be-updated amplitudes of the variable nodes and the information update values sent by the current check node to the variable nodes connected thereto, respectively, after delaying for a preset time, where the preset time is equal to or longer than a storage time taken by the third storage unit 105 to store the current values of the to-be-updated amplitudes of the variable nodes, so as to meet different application scenarios.

For example, in one embodiment, the preset time may be set to be equal to the storage time taken by the third storage unit 105 to store the current values of the to-be-updated amplitudes of the plurality of variable nodes. Specifically, when the third storage unit 105 stores the current value of the amplitude to be updated of the ith variable node connected to the jth check node on the ith layer

In other words, the third storage unit 105 needs to complete the current value of the to-be-updated amplitude of the ith variable node connected to the jth check node on the ith layer after the storage time T elapses

To be stored. The preset time is set to be the same as the storage time T. When the current value of the amplitude to be updated of the ith variable node connected with the jth check node on the ith layer is subjected to updating

After the storage is finished, that is, after the subtraction operation is finished by the subtractor 108 and the preset time is delayed, the current value of the amplitude to be updated of the ith variable node connected with the jth check node on the ith layer can be updated

Information updating value sent by jth check node to ith variable node on l +1 th layer

Reading into the adder 109, adding in the adder 109 to obtain the updated value of the log likelihood ratio of the ith variable node on the l +1 th layer

It is understood that, in other embodiments, the preset time may also be set to be greater than the storage time T. At this time, the current value of the amplitude to be updated of the ith variable node connected with the jth check node on the ith layer is completed in the third storage unit 105

After the storage, the user may not need to perform the subsequent addition operation temporarily, that is, the addition operation is not performed in the adder 109 immediately, and when the user has a need, the current value of the amplitude to be updated of the ith variable node connected to the jth check node on the ith layer is waited to be updated

Reading into an adder 109, and adding in the adder 109 to obtain the updated log-likelihood ratio value of the ith variable node on the l +1 th layer

At this time, the delayed preset time is greater than the storage time T.

The decoding device can be suitable for decoding a plurality of different FLASH. Different FLASH can be FLASH of different manufacturers, or different FLASH can be FLASH of different particle types, such as Single-Level Cell (SLC), double-Level Cell (MLC), triple-Level Cell (TLC), four-Level Cell (QLC), and non-volatile memory chip (3D X-point).

Fig. 10 shows a flowchart of a decoding method according to an embodiment of the present application, where fig. 10 is a schematic flowchart of the decoding method according to the embodiment of the present application. The decoding method may include:

201. a decoding device is provided.

In an embodiment of the present application, a decoding apparatus is provided, and the decoding apparatus may be the decoding apparatus provided in the embodiment of the present application.

202. And designing a plurality of check matrixes with different cycle lengths aiming at different code lengths.

In the embodiment of the application, for different code lengths provided by different FLASH manufacturers, check matrixes with different cycle lengths can be designed, that is, different code lengths correspond to check matrixes with different cycle lengths, but not all code lengths use the same check matrix, so that a 0 supplementing mode is not needed, the number of data cannot be reduced, the error rate can be reduced, and the error correction capability of code words can be improved.

203. The base matrixes of the check matrixes with different cycle lengths are written into different address areas of the first memory unit.

In the embodiment of the present application, after a plurality of check matrices with different cycle lengths are designed, the base matrix of each check matrix may be written into different address regions of the first storage unit, and for the specific structure of the base matrix, reference may be made to an embodiment in the decoding apparatus, which is not described herein again.

204. And the data selector selects a target base matrix corresponding to the code length from the first storage unit according to the code length of the code word to be decoded.

In this embodiment, the data selector may select, according to the code length of the current codeword to be decoded, a base matrix corresponding to the code length, that is, a target base matrix, from the first storage unit.

205. The first shift circuit receives the target base matrix read from the first storage unit in a layered mode, and performs first-direction translation on the unit matrix according to the target base matrix to obtain a target check matrix.

In this embodiment of the application, the first shift circuit may receive a target base matrix read by firmware from the first storage unit in a hierarchical manner, that is, the target base matrix read by firmware line by line, and perform translation in a first direction, for example, perform right shift on the identity matrix according to a shift value of each element in the target base matrix, so as to obtain the target check matrix.

206. And decoding the code word to be decoded based on the target check matrix.

In the embodiment of the application, after the target check matrix is obtained, the codeword to be decoded can be decoded based on the target check matrix. For example, in decoding, a hierarchical min-sum algorithm (Layer min-sum algorithm) may be used for decoding.

For example, in an embodiment, the decoding of the codeword to be decoded based on the target check matrix in 206 may include:

the second shift circuit receives the target base matrix read from the first storage unit in a layered mode, and performs shift in a second direction on the sum of the current values of the amplitudes to be updated of the variable nodes and the information update values sent by the current check node to the variable nodes connected with the current check node according to the target base matrix so as to obtain log-likelihood ratio update values of the variable nodes;

For example, the current information value sent by the jth check node on the ith layer of the target check matrix to the ith variable node connected with the jth check node is read from the second storage unit

Current value of log-likelihood ratio of ith variable node on l-th layer

The jth check node on the ith layer sends the current information value of the ith variable node connected with the jth check node

Namely, it is

Obtaining the current value of the amplitude to be updated of the ith variable node connected with the jth check node on the ith layer

Is stored in the third storage unit.

Reading the information updating value sent by the jth check node on the l +1 th layer to the ith variable node connected with the jth check node from the second storage unit

Information updating value sent to ith variable node connected with jth check node on l +1 th layer

For the calculation, reference may be made to the embodiment in the decoding apparatus, and details are not described herein. Waiting for ith variable node connected with jth check node on ith layerUpdating the magnitude nonce

The addition is performed.

The second shift circuit can receive a target base matrix read by the firmware from the first storage unit in a layered mode, and according to the shift value in the target base matrix, the current value of the amplitude to be updated of the ith variable node connected with the jth check node on the ith layer

The added sum is shifted in a second direction, such as left shift, to obtain updated log-likelihood ratio value of ith variable node on the l +1 th layer

Namely, it is

Updating the log likelihood ratio of the ith variable node on the l +1 th layer

And storing the data in a fourth storage unit.

And generating a decoding result matrix according to the log-likelihood ratio update value of each variable node on the (l + 1) th layer, determining whether decoding succeeds or not according to the decoding result matrix, and if decoding succeeds, ending decoding and taking the decoding result matrix as a final decoding result. If the current number of decoding iterations reaches the preset maximum iteration number, the decoding is finished and the decoding fails.

The present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed on a computer, the computer is caused to execute the flow in the decoding method provided in this embodiment.

The embodiment of the present application further provides a computer device, which includes a memory and a processor, where the processor is used to execute the flow in the decoding method provided in this embodiment by calling the computer program stored in the memory.

For example, the computer device may be a terminal device having a corresponding function, such as a mobile phone, a tablet computer, a personal computer, a cloud computer, and the like. Referring to fig. 11, fig. 11 is a schematic structural diagram of a computer according to an embodiment of the present disclosure.

The computer device 300 may include a memory 301, a processor 302, and the like. Those skilled in the art will appreciate that the computer device architecture illustrated in FIG. 11 is not intended to be limiting of computer devices and may include more or less components than those illustrated, or combinations of certain components, or different arrangements of components.

The memory 301 may be used to store applications and data. The memory 301 stores applications containing executable code. The application programs may constitute various functional modules. The processor 302 executes various functional applications and data processing by running an application program stored in the memory 301.

The processor 302 is a control center of the computer device, connects various parts of the computer device by various interfaces and lines, performs various functions of the computer device and processes data by running or executing an application program stored in the memory 301 and calling the data stored in the memory 301, thereby monitoring the computer device as a whole.

In this embodiment, the processor 302 in the computer device loads the executable code corresponding to the processes of one or more application programs into the memory 301 according to the following instructions, and the processor 302 runs the application programs stored in the memory 301, so as to execute:

providing the decoding device in the embodiment of the present application;

and decoding the code word to be decoded based on the target check matrix.

In an embodiment, when performing the decoding of the codeword to be decoded based on the target check matrix, the processor 302 may further perform:

In one embodiment, the processor 302 may further perform: and if the current times of decoding iteration reaches the preset maximum iteration times, ending the decoding.

In the embodiments of the computer device and the readable storage medium provided in the present application, all technical features of the embodiments of the method are included, and the content of the expansion and the explanation of the specification is the same as the adaptability of the embodiments of the positioning method, and will not be described herein again.

Embodiments of the present application further provide a chip, which includes a memory and a processor, where the memory is used to store a program, and the processor is used to call and run the program from the memory, so that a device in which the chip is installed performs the method in the above various possible embodiments.

In the above embodiments, the descriptions of the embodiments have respective emphasis, and parts that are not described in detail in a certain embodiment may refer to the above detailed description for the decoding apparatus, and are not described herein again.

The decoding method provided in the embodiment of the present application and the decoding apparatus in the above embodiments belong to the same concept, and the specific implementation process thereof is described in the embodiment of the decoding apparatus for details, which is not described herein again.

It should be noted that, for the decoding method described in the embodiment of the present application, it can be understood by those skilled in the art that all or part of the process for implementing the decoding method described in the embodiment of the present application can be implemented by controlling the relevant hardware through a computer program, where the computer program can be stored in a computer-readable storage medium, such as a memory, and executed by at least one processor, and during the execution, the process of the embodiment of the decoding method can be included. The storage medium may be a magnetic disk, an optical disk, a read-only Memory (rom), a Random Access Memory (RAM), or the like.

The decoding device, the decoding method, the storage medium, and the computer device provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and implementations of the present application, and the descriptions of the above embodiments are only used to help understand the method and the core ideas of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A decoding apparatus, comprising:

the first storage unit is used for storing a base matrix of a plurality of check matrixes with different cycle lengths aiming at different code lengths;

the first displacement circuit is respectively connected with the first storage unit and the data selector and is used for receiving the target base matrix read from the first storage unit in a layered mode and translating the identity matrix in a first direction according to the target base matrix to obtain a target check matrix;

2. The decoding device according to claim 1, wherein the translation in the first direction is a right shift and the translation in the second direction is a left shift.

3. The decoding apparatus according to claim 2, wherein the check matrix comprises a plurality of sub-matrices, and a plurality of displacement values of the sub-matrices with respect to an identity matrix constitute the base matrix.

4. The decoding apparatus according to claim 3, wherein the first storage unit comprises a read only memory, and the first shift circuit is further configured to receive the target basis matrix read hierarchically from the read only memory, and right-shift the identity matrix according to a plurality of shift values in the target basis matrix to obtain the target check matrix.

5. The decoding device according to claim 1, further comprising:

6. The decoding device according to claim 1, wherein the third storage unit is further configured to calculate information update values sent by the current check node to the plurality of variable nodes connected thereto, and send the information update values sent by the current check node to the plurality of variable nodes connected thereto to the second storage unit for storage.

7. The decoding device according to claim 1, wherein the third storage unit is further configured to calculate a symbol function value update value and an amplitude update value of the plurality of variable nodes, and obtain an information update value sent by the current check node to the plurality of variable nodes connected thereto according to the symbol function value update value and the amplitude update value of the plurality of variable nodes.

8. The decoding device according to claim 7, wherein the updated values of the sign function values and the updated values of the amplitudes of the plurality of variable nodes are obtained from current values of the amplitudes to be updated of variable nodes other than the target variable node among the plurality of variable nodes connected to the current check node.

9. The decoding device according to claim 1, further comprising:

10. The decoding device according to claim 9, wherein the adder is further configured to perform corresponding addition on the amplitude current values to be updated of the plurality of variable nodes and the information update values sent by the current check node to the plurality of variable nodes connected thereto, respectively, after delaying for a preset time, where the preset time is equal to or longer than a storage time taken by the third storage unit to store the amplitude current values to be updated of the plurality of variable nodes.

11. The decoding apparatus according to claim 1, wherein the first shift circuit, the second shift circuit, and the identity matrix are the same size.

12. A decoding method, comprising:

providing a decoding device according to any one of claims 1 to 11;

and decoding the code word to be decoded based on the target check matrix.

13. The decoding method according to claim 12, wherein the decoding the codeword to be decoded based on the target check matrix comprises:

14. The coding method according to claim 13, wherein the method further comprises:

15. A computer-readable storage medium, on which a computer program is stored, which, when executed on a computer, causes the computer to carry out the method according to any one of claims 12 to 14.

16. A computer device comprising a memory and a processor, wherein the processor executes the method of any one of claims 12 to 14 by calling a computer program stored in the memory.