CN102263550B - Logic signal transmission circuit - Google Patents
Logic signal transmission circuit Download PDFInfo
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- CN102263550B CN102263550B CN 201010189709 CN201010189709A CN102263550B CN 102263550 B CN102263550 B CN 102263550B CN 201010189709 CN201010189709 CN 201010189709 CN 201010189709 A CN201010189709 A CN 201010189709A CN 102263550 B CN102263550 B CN 102263550B
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Abstract
The invention provides a logic signal transmission circuit which comprises a Complementary Metal Oxide Semiconductor inverter, a first transistor switch and an inverter. The Complementary Metal Oxide Semiconductor inverter comprises a P-type transistor and an N-type transistor, and is used for inputting a signal in an inverted way. The first transistor switch connects with an input terminal of the Complementary Metal Oxide Semiconductor inverter. The inverter is between the P-type transistor and the first transistor switch for connection, wherein when the first transistor switch is connected, the inverter turns off the P-type transistor, and when the first transistor switch is disconnected, the inverter turns on the P-type transistor.
Description
Technical field
The present invention relates to a kind of electronic installation, particularly relate to a kind of logical signal transfer circuit.
Background technology
In generally in order to the circuit that transmits external logic signal (as: clock signal), though the low voltage level of external logic signal is to be fixed on earthed voltage, the high-voltage level of external logic signal can change under different situations.For example, the high-voltage level of external logic signal may change in the scope between 1.5V and the 5.0V.
Yet if the unsettled words of the high-voltage level of external logic signal, the circuit that continues after the logical signal transfer circuit may move according to unsettled logical signal, and therefore the situation of misoperation is arranged.
In addition, when logical signal when low voltage level is transferred to high-voltage level, can a large amount of transmission delay (Propagation Delay) be arranged because of the process that shifts, make the transmission of logical signal effectively to carry out.
Summary of the invention
A purpose of the present invention provides a kind of logical signal transfer circuit, uses when solving logical signal and transmitting unstable and have a problem of transmission delay.
A technical scheme of the present invention is about a kind of logical signal transfer circuit, and it comprises a complementary MOS inverter, a first transistor switch and an inverter.Complementary MOS inverter comprises a P transistor npn npn and a N transistor npn npn, and in order to an anti-phase input signal.The first transistor switch is connected in an input of complementary MOS inverter.Inverter is connected between P transistor npn npn and the first transistor switch, and wherein when the first transistor switch open, inverter cuts out the P transistor npn npn, and when the first transistor switch cut out, inverter was opened the P transistor npn npn.
Another technical scheme of the present invention is about a kind of logical signal transfer circuit, and it comprises a complementary MOS inverter, a first transistor switch and an inverter.Complementary MOS inverter comprises a P transistor npn npn and a N transistor npn npn, and wherein the N transistor npn npn repeatedly is connected with P transistor npn npn string.The control end of the first transistor switch is connected in the grid of N transistor npn npn.Inverter has an input and an output, and output is connected in the grid of P transistor npn npn, and the first transistor switch is connected between an inverter and the earthed voltage.
According to the present invention, application of aforementioned logical signal transfer circuit not only can be under the situation of unstable change in the scope of high-voltage level between 1.5V and 5.0V of external logic signal, with the external logic conversion of signals is required logical signal, also can avoid producing breakdown current (shoot throughcurrent), and the transmission of logical signal even can carry out effectively because of less transmission delay (PropagationDelay).
Description of drawings
Fig. 1 is the schematic diagram that illustrates a kind of logical signal transfer circuit according to one embodiment of the invention.
Fig. 2 is the schematic diagram that illustrates a kind of logical signal transfer circuit according to another embodiment of the present invention.
Fig. 3 is the schematic diagram that illustrates a kind of logical signal transfer circuit according to further embodiment of this invention.
Fig. 4 is the B-H loop schematic diagram that illustrates the relative output logic signal of a kind of input signal according to the embodiment of the invention.
The reference numeral explanation
100,200,300: the logical signal transfer circuit
The 110:CMOS inverter
120: current source
Embodiment
Hereinafter in conjunction with the accompanying drawings illustrated embodiment is elaborated, but the embodiment that is provided not is the scope that contains in order to restriction the present invention, and the description of structure running is non-in order to limit the order of its execution, any structure that reconfigures by assembly, the device with impartial effect that produces is all the scope that the present invention is contained.Wherein accompanying drawing is not mapped according to life size only for the purpose of description.
Fig. 1 is the schematic diagram that illustrates a kind of logical signal transfer circuit according to one embodiment of the invention.Logical signal transfer circuit 100 can be applicable in the grid pulse modulator (gate pulse modulator), and comprise a CMOS (Complementary Metal Oxide Semiconductor) (Complementary Metal OxideSemiconductor, CMOS) inverter 110, a transistor switch M1 and an inverter IV1.CMOS inverter 110 has an input IN, and does anti-phase action in order to the input signal VIN that input IN is transmitted, to export a logical signal VFLK or a VFLKB.CMOS inverter 110 comprises a P transistor npn npn MP4A and a N transistor npn npn MN4, and wherein transistor MN4 string repeatedly is connected in transistor MP4A, and its grid is connected in input IN.Transistor switch M1 has a control end, and it is connected in the grid of input IN and transistor MN4, thereby is controlled by input signal VIN.Inverter IV1 is connected between transistor MP4A and the transistor switch M1, and also has an input and an output, and its output is connected in the grid of transistor MP4A.Transistor switch M1 is connected between the input and an earthed voltage GND of inverter IV1.
In operation, when transistor switch M1 opened, inverter IV1 closed transistor MP4A, and when transistor switch M1 closes, inverter IV1 turn-on transistor MP4A.
Particularly, when input signal VIN is issued to input IN (or grid of transistor MN4) and has high level (as: between 1.5V and 5.0V), transistor switch M1 is opened by input signal VIN, the input of inverter IV1 draws via transistor switch M1 and reduces to earthed voltage GND (low level), and the output of inverter IV1 is pulled up to a supply voltage VDD (high level), to close transistor MP4A.Therefore, transistor MN4 is opened by input signal VIN, draws with the output OUT with CMOS inverter 110 and reduces to earthed voltage GND.
On the other hand, when input signal VIN sends and has low level (as earthed voltage), transistor switch M1 is closed by input signal VIN, the input of inverter IV1 is pulled up to VDD (high level) via for example transistor M5, and the output of inverter IV1 draws and reduces to earthed voltage (low level), with turn-on transistor MP4A, make the output OUT of CMOS inverter 110 be pulled up to VDD (high level) via for example current source 120, wherein current source 120 is connected between voltage VDD and the transistor MP4A, and can realize that transistor MP4 is continued to open by low level voltage VSS control by a transistor MP4.Thus, transistor MN4 just can be closed by input signal VIN.
It should be noted that, when the voltage level of input signal VIN increase and before reaching a maximum (that is, be transferred to by low level and reach before the high level), for example reach the critical voltage (as 0.7V) of transistor switch M1, make that the input of inverter IV1 drew immediately via transistor switch M1 and reduces to earthed voltage GND when transistor switch M1 opened, the output of inverter IV1 is pulled up to voltage VDD immediately, closing transistor MP4A, and transistor MN4 is opened by input signal VIN.Therefore, even the high-voltage level of input signal VIN changes between 1.5V and 5.0V astatically, logical signal transfer circuit 100 still can be converted to input signal VIN required logical signal.
Moreover, because the voltage level of input signal VIN is transferred to high level from low level, need a period of time in fact, cause the transmission delay in the logical signal transfer circuit 100, so can increase by the voltage level of input signal VIN and reach before the high level, under the situation that transistor switch M1 opens, the input of inverter IV1 draws immediately via transistor switch M1 and reduces to earthed voltage GND, then the output of inverter IV1 is pulled up to voltage VDD immediately to close transistor MP4A, makes the time of transmission delay therefore reduce.Thus, the breakdown current (shoot through current) that is produced in the time of just can avoiding CMOS inverter 110 to switch, and the transmission of logical signal can effectively be carried out because of less transmission delay.
In the present embodiment, logical signal transfer circuit 100 also can comprise and opens beginning transistor MENI, and it has a control end, opens beginning signal PGB in order to receive one, and is connected between the grid and earthed voltage GND of transistor MN4.Particularly,, open beginning signal PGB and send and turn-on transistor MENI,, use the initial condition of setting the CMOS inverter 110 and the circuit that continues so that CMOS inverter 110 can't be operated when logical signal transfer circuit 100 as yet not during stable operation.
In the present embodiment, logical signal transfer circuit 100 also can comprise an Electrostatic Discharge transistor ME, wherein transistor ME has a control end, in order to receive by open beginning signal PGB anti-phase and a signal PG, and be connected in the grid of transistor MN4 and in order between the input node that receives external logic signal VFLK_IN.Transistor ME is controlled by signal PG, carrying out the operation of static discharge, and transmits logical signal VFLK_IN as input signal VIN.
Fig. 2 is the schematic diagram that illustrates a kind of logical signal transfer circuit according to another embodiment of the present invention.Compared to Fig. 1, logical signal transfer circuit 200 also comprises transistor switch M2, and it repeatedly is connected with transistor switch M1 string, and transistor switch M2 is connected between the input of transistor switch M1 and inverter IV1.Transistor switch M2 has a control end, and control end is connected in the grid (or input IN) of transistor MN4, makes transistor switch M2 be controlled by input signal VIN.
In operation, comprise the logical signal transfer circuit 200 of transistor switch M1 and M2, be similar to the action of the logical signal transfer circuit 100 that comprises transistor switch M1 among Fig. 1.For example, when input signal VIN is issued to input IN (or grid of transistor MN4) and has high level, transistor switch M1 and M2 open by input signal VIN, the input of inverter IV1 draws via transistor switch M1 and M2 and reduces to earthed voltage GND (low level), and the output of inverter IV1 is pulled up to supply voltage VDD (high level), to close transistor MP4A.
Similarly, when the voltage level of input signal VIN increase and before reaching a maximum (that is, be transferred to by low level and reach before the high level), for example reach the critical voltage of transistor switch M1 and M2, make that the input of inverter IV1 drew immediately via transistor switch M1 and M2 and reduces to earthed voltage GND when transistor switch M1 and M2 opened, and the output of inverter IV1 is pulled up to voltage VDD immediately, closing transistor MP4A, and transistor MN4 is opened by input signal VIN.Therefore, even the high-voltage level of input signal VIN changes between 1.5V and 5.0V astatically, logical signal transfer circuit 200 still can be converted to input signal VIN required logical signal.
Moreover, reach by the voltage level increase of input signal VIN before the high level, under the situation that transistor switch M1 and M2 open, the input of inverter IV1 draws immediately via transistor switch M1 and M2 and reduces to earthed voltage GND, can make the time of transmission delay therefore reduce.Thus, just can avoid producing breakdown current, and therefore the transmission of logical signal can be carried out effectively.
Fig. 3 is the schematic diagram of a kind of logical signal transfer circuit of illustrating according to further embodiment of this invention.Compared to Fig. 2, logical signal transfer circuit 300 also comprises a magnetic hysteresis (hysteresis) transistor M3, and it is in order to giving a hysteresis characteristic to logical signal transfer circuit 300, and is controlled by inverter IV1.Hysteresis transistor M3 repeatedly is connected with transistor switch M2 string, and is connected in parallel with transistor switch M1, and also has a control end, is connected in the output of inverter IV1, to receive the signal HYS that is exported by inverter IV1.
When hysteresis transistor M3 and transistor switch M1 and M2 co-operate, hysteresis transistor M3 can give hysteresis characteristic to logical signal transfer circuit 300.Fig. 4 is the B-H loop schematic diagram of the relative output logic signal VFLK of a kind of input signal VIN that illustrates according to the embodiment of the invention.With reference to Fig. 3 and Fig. 4, when the voltage level of input signal VIN increased to two critical voltages (2VTH) with turn-on transistor switch M1 and M2, the signal HYS that is exported by inverter IV1 can be pulled up to voltage VDD (high level) simultaneously, to open hysteresis transistor M3.At this moment, hysteresis transistor M3 is than transistor switch M1 conducting or unlatching more (for example: the conducting resistance rds of M3, on is littler than M1), so node NX can be considered ideally with earthed voltage GND and is connected.Afterwards, when the voltage level of input signal VIN was reduced to a critical voltage (VTH), transistor switch M2 can close.Thus, when hysteresis transistor M3 and transistor switch M1 and M2 co-operate, logical signal transfer circuit 300 just can be endowed hysteresis characteristic by the operation of hysteresis transistor M3.
Secondly, also can be by changing one of them size of transistor switch M1 and M2, or change the size of transistor switch M1 and M2 simultaneously, adjust the transfer point (being voltage VTH or 2VTH) among Fig. 4.In addition, transistor switch M1 string repeatedly is connected in transistor switch M2, transfer point is increased to above 1.0V.In addition, if omit transistor switch M2, then the transfer point critical voltage that may be positioned at transistor MN4 (is generally 0.7V～0.9V).
By the embodiment of the invention described above as can be known, application of aforementioned logical signal transfer circuit, not only can be under the situation of unstable change in the scope of high-voltage level between 1.5V and 5.0V of external logic signal, with the external logic conversion of signals is required logical signal, also can avoid producing breakdown current (shoot through current), and the transmission of logical signal even can carry out effectively because of less transmission delay (Propagation Delay).
Though the present invention discloses as above with execution mode; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (18)
1. logical signal transfer circuit comprises:
One complementary MOS inverter comprises a P transistor npn npn and a N transistor npn npn, and in order to an anti-phase input signal;
One the first transistor switch is connected in an input of this complementary MOS inverter;
One inverter is connected between this P transistor npn npn and this first transistor switch, and wherein when this first transistor switch open, this inverter cuts out this P transistor npn npn, and when this first transistor switch cut out, this inverter was opened this P transistor npn npn; And
One transistor seconds switch is connected between the input of this first transistor switch and this inverter, and by this input signal control.
2. logical signal transfer circuit as claimed in claim 1, wherein when this input signal sends and has high level, this N transistor npn npn is opened by this input signal, draws with the output with this complementary MOS inverter and reduces to an earthed voltage.
3. logical signal transfer circuit as claimed in claim 2, wherein when this input signal sends and has low level, this the first transistor switch cuts out by this input signal, makes this P transistor npn npn open and this output of this complementary MOS inverter is pulled up to a supply voltage.
4. logical signal transfer circuit as claimed in claim 1, wherein increase and when before reaching a maximum, making this first transistor switch open when the voltage level of this input signal, one input of this inverter draws via this first transistor switch and reduces to an earthed voltage, and an output of this inverter is pulled up to a supply voltage.
5. logical signal transfer circuit as claimed in claim 1, wherein increase and when before reaching a maximum, making this first transistor switch and this transistor seconds switch open when the voltage level of this input signal, this input of this inverter draws via this first transistor switch and this transistor seconds switch and reduces to an earthed voltage, and an output of this inverter is pulled up to a supply voltage.
6. logical signal transfer circuit as claimed in claim 1 also comprises:
One hysteresis transistor is in order to give this logical signal transfer circuit one hysteresis characteristic.
7. logical signal transfer circuit as claimed in claim 6, wherein this hysteresis transistor repeatedly is connected with this transistor seconds switch series, and this hysteresis transistor and this first transistor switch in parallel are joined.
8. logical signal transfer circuit as claimed in claim 7, wherein this hysteresis transistor is controlled by this inverter.
9. logical signal transfer circuit as claimed in claim 1 also comprises:
One opens the beginning transistor, in order to open this complementary MOS inverter of beginning.
10. logical signal transfer circuit comprises:
One complementary MOS inverter comprises a P transistor npn npn and a N transistor npn npn, and this N transistor npn npn repeatedly is connected with this P transistor npn npn string;
One the first transistor switch, the control end of this first transistor switch is connected in the grid of this N transistor npn npn;
One inverter has an input and an output, and this output is connected in the grid of this P transistor npn npn, and this first transistor switch is connected between this inverter and the earthed voltage; And
One transistor seconds switch, the control end of this transistor seconds switch is connected in the grid of this N transistor npn npn, and this transistor seconds switch repeatedly is connected with this first transistor switch series, and is connected between this input of this first transistor switch and this inverter.
11. logical signal transfer circuit as claimed in claim 10, wherein be issued to the grid of this N transistor npn npn when this input signal, and the voltage level of this input signal increases and when making this first transistor switch and this transistor seconds switch open before reaching a maximum, this input of this inverter draws via this first transistor switch and this transistor seconds switch and reduces to this earthed voltage, and this output of this inverter is pulled up to a supply voltage.
12. logical signal transfer circuit as claimed in claim 10 also comprises:
One hysteresis transistor, the control end of this hysteresis transistor are connected in this output of this inverter, and this hysteresis transistor repeatedly is connected with this transistor seconds switch series, and this hysteresis transistor and this first transistor switch in parallel are joined.
13. logical signal transfer circuit as claimed in claim 12, wherein when this hysteresis transistor and this first transistor switch and this transistor seconds switch co-operate, this hysteresis transistor is given this logical signal transfer circuit one hysteresis characteristic.
14. logical signal transfer circuit as claimed in claim 12 also comprises:
One opens the beginning transistor, and this opens transistorized control end of beginning and opens the beginning signal in order to receive one, and is connected between the grid and this earthed voltage of this N transistor npn npn.
15. logical signal transfer circuit as claimed in claim 14 also comprises:
One current source is connected between a supply voltage and this P transistor npn npn.
16. logical signal transfer circuit as claimed in claim 15 also comprises:
One static discharge transistor, the transistorized control end of this static discharge opens a signal that begins signal inversion and get in order to receive by this, and this static discharge transistor is connected in the grid of this N transistor npn npn and imports between the node in order to receive one of an input signal.
17. logical signal transfer circuit as claimed in claim 10, wherein be issued to the grid of this N transistor npn npn when an input signal, and the voltage level of this input signal increases and when making this first transistor switch open before reaching a maximum, this input of this inverter draws via this first transistor switch and reduces to this earthed voltage, and this output of this inverter is pulled up to a supply voltage.
18. logical signal transfer circuit as claimed in claim 10, wherein when an input signal is issued to the grid of this N transistor npn npn and has high level, this N transistor npn npn is opened by this input signal, draw with a output and to reduce to this earthed voltage, and this first transistor switch is opened by this input signal this complementary MOS inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010189709 CN102263550B (en) | 2010-05-26 | 2010-05-26 | Logic signal transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010189709 CN102263550B (en) | 2010-05-26 | 2010-05-26 | Logic signal transmission circuit |
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| Publication Number | Publication Date |
|---|---|
| CN102263550A CN102263550A (en) | 2011-11-30 |
| CN102263550B true CN102263550B (en) | 2013-07-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010189709 Expired - Fee Related CN102263550B (en) | 2010-05-26 | 2010-05-26 | Logic signal transmission circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1122534A (en) * | 1994-08-29 | 1996-05-15 | 株式会社日立制作所 | Low distortion switch |
| US6529050B1 (en) * | 2001-08-20 | 2003-03-04 | National Semiconductor Corporation | High-speed clock buffer that has a substantially reduced crowbar current |
| CN200953546Y (en) * | 2006-06-12 | 2007-09-26 | 北京希格玛和芯微电子技术有限公司 | Pulse sequence generating device |
-
2010
- 2010-05-26 CN CN 201010189709 patent/CN102263550B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1122534A (en) * | 1994-08-29 | 1996-05-15 | 株式会社日立制作所 | Low distortion switch |
| US6529050B1 (en) * | 2001-08-20 | 2003-03-04 | National Semiconductor Corporation | High-speed clock buffer that has a substantially reduced crowbar current |
| CN200953546Y (en) * | 2006-06-12 | 2007-09-26 | 北京希格玛和芯微电子技术有限公司 | Pulse sequence generating device |
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| Publication number | Publication date |
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| CN102263550A (en) | 2011-11-30 |
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Granted publication date: 20130731 Termination date: 20180526 |