CN102263039B - Method for manufacturing crystal grain assembly - Google Patents
Method for manufacturing crystal grain assembly Download PDFInfo
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- CN102263039B CN102263039B CN2010101927492A CN201010192749A CN102263039B CN 102263039 B CN102263039 B CN 102263039B CN 2010101927492 A CN2010101927492 A CN 2010101927492A CN 201010192749 A CN201010192749 A CN 201010192749A CN 102263039 B CN102263039 B CN 102263039B
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- crystal grain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention relates to a method for manufacturing a crystal grain assembly. The method comprises the following steps: (a) providing a tested upper wafer and at least one lower wafer; (b) cutting the at least one lower wafer, thereby forming a plurality of lower crystal grains containing a plurality of known qualified crystal grains; (c) according to a wafer map of the upper wafer, selecting and rearranging the known qualified crystal grains on a carrier; (d) connecting the upper wafer to the carrier; (e) removing the carrier; and (f) performing a cutting process. The method can be used for ensuring that the crystal grains of the crystal grain assembly are all known qualified crystal grains, thereby avoiding the yield loss caused by different yields of the upper wafer and the lower wafer.
Description
Technical field
The present invention is about a kind of crystal grain assembly and manufacture method thereof, in detail, and about a kind of crystal grain assembly and manufacture method thereof of utilizing wafer that wafer (Wafer to Wafer) storehouse is manufactured.
Background technology
Present three-dimensional IC packaged type mainly adopts two kinds of stackings: one is that wafer is to wafer (Wafer to Wafer, storehouse WtW); Another then is that (Chip to Chip, storehouse CtC) or chip are to wafer (Chip toWafer, storehouse CtW) to chip for chip.With respect to chip to chip (Chip to Chip, CtC) storehouse or chip are to wafer (Chip to Wafer, CtW) storehouse, (Wafer to Wafer, storehouse WtW) a kind ofly can reach the easy packaged type of high production and processing step to wafer to wafer.
Yet, wafer is to wafer (Wafer to Wafer, WtW) shortcoming of the technology maximum of storehouse namely is that the yield of wafer influenced about output can be subjected to, for example: the yield of the wafer of two desire storehouses distinctly is 50% and 100%, even wherein the yield of a slice is higher, but behind the directly mutual storehouse of two wafer, the yield of its output qualified products only is 50%, and its yield loss (Yield Loss) is up to 50%.Unless the technology of two kinds of wafers is all highly stable up and down by the time, could effectively promote the output capacity of final products.
Therefore, be necessary to provide crystal grain assembly and the manufacture method thereof of a kind of innovation and tool progressive, to address the above problem.
Summary of the invention
The invention provides a kind of manufacture method of crystal grain assembly, may further comprise the steps: wafer and at least one wafer down on one (a) are provided, and wafer and this time wafer wherein should be gone up wafer and have crystal grain on several known good for testing on this; (b) this at least one wafer down of cutting, to form several crystal grain down, crystal grain comprises crystal grain under several known good under these; (c) choose crystal grain under these known good, and crystal grain under these known good is rearranged on a carrier, make under these known good the position of crystal grain on corresponding these known good in the position of crystal grain; (d) engage and to go up wafer and this carrier, make that crystal grain electrically connects crystal grain on these known good under these known good; (e) remove this carrier; And (f) carry out cutting technique, to form several crystal grain assemblies.
In the present invention, owing to rearrange crystal grain under these known good according to the wafer map that should go up wafer, therefore what can guarantee that crystal grain electrically connects on these known good must be crystal grain under these known good, like this then do not have wafer and reach the yield loss (Yield Loss) that time wafer causes because of the yield difference.
Description of drawings
Fig. 1 to Figure 15 shows the schematic diagram of each processing step of the manufacture method of crystal grain assembly of the present invention.
Embodiment
Referring to figs. 1 to Figure 15, show the schematic diagram of each processing step of the manufacture method of crystal grain assembly of the present invention.With reference to figure 1, provide wafer 10 and at least one wafer 20 down on one.Should go up wafer 10 and this time wafer 20 for testing, therefore all have wafer map (Wafer Mapping), wherein should go up wafer 10 and have crystal grain on several known good (Upper Known Good Die) 11 and several known defective crystal grain (Upper Known Bad Die) (not shown) of going up.
With reference to figure 2, crystal grain 11 has a front 111, a back side 112 and several conductive structures 113 on this known good.These conductive structures 113, projection for example is positioned at the front 111 of crystal grain 11 on this known good.
Then, cut this at least one wafer 20 down, to form several crystal grain down, crystal grain comprises (Lower Known Good Die) 21 (Fig. 3) of crystal grain under several known good and several known defective crystal grain (LowerKnown Bad Die) (not shown) down under these.
With reference to figure 3, crystal grain 21 has a front 211, a back side 212, several connection post (Via) 213 and several projections (Bump) 214 under this known good.These are communicated with posts 213 and are positioned under this known good within the crystal grain 21, and these projections 214 are positioned at the front 211 of crystal grain 21 under this known good, and these are communicated with posts 213 and electrically connect these projections 214.
Then, choose crystal grain 21 under these known good, and this rearranges on a carrier 30 as one kind with crystal grain under these known good 21, make the position of crystal grain 11 on corresponding these known good in position of crystal grain 21 under these known good.That is the wafer map after this carrier 30 as one kind rearranges (Wafer Mapping) is identical with the wafer map that should go up wafer 10.In the present embodiment, this carrier 30 as one kind is the wafer (Dummy Wafer) of a no electrical functionality, and utilizes a glue-line 31 that the front 211 of crystal grain 21 under these known good is attached on this carrier 30 as one kind.
In the present embodiment, choose that crystal grain 21 is arranged on this carrier 30 as one kind under these known good.Yet be understandable that, also can more choose these known defective crystal grain down rearranges on this carrier 30 as one kind, to fill up the space of 21 of crystal grain under these known good, corresponding these known defective positions of going up crystal grain, the position of these known defective crystal grain down wherein.
With reference to figure 4, form an insulating barrier 32 crystal grain 21 under these known good, to coat crystal grain 21 under these known good.Preferably, this insulating barrier 32 is a kind of adhesive material, and is full of under these known good crack between 21 of the crystal grain.
With reference to figure 5, the upper surface that grinds this insulating barrier 32 to be appearing crystal grain 21 under these known good, and partly removes the back side 212 of crystal grain 21 under these known good again with etching mode, to manifest the end that these are communicated with posts 213.
With reference to figure 6, be communicated with in these and carry out surface treatment on end that posts 213 manifest and form a surface-treated layer 33.
With reference to figure 7 and Fig. 8, engage and should go up wafer 10 and this carrier 30 as one kind, make that crystal grain 21 electrically connects crystal grain 11 on these known good under these known good.In the present embodiment, utilize some glue mode to form a primer (Underfill) 34 on crystal grain 21 under these known good (as Fig. 7) earlier.Afterwards, recycling one suction nozzle 60 should be gone up wafer 10 heating and be engaged in this carrier 30 as one kind (as Fig. 8), make the connection post 213 of crystal grain 21 under these known good electrically connect the conductive structure 113 (as Figure 11) of crystal grain 11 on these known good, this moment, this primer 34 formed an intermediate gelatine layer 35.
In the present embodiment, this intermediate gelatine layer 35 utilizes some glue mode to form, yet in another embodiment, this intermediate gelatine layer 35 also can utilize following manner to form.
With reference to figure 9, fit one first glued membrane 51 on crystal grain 21 under these known good, then shine UV light to solidify this first glued membrane (Film) 51, partly remove the surface of this first glued membrane 51 again with etching mode, be communicated with post 213 to manifest these.In addition, fit one second glued membrane 52 in this on the wafer 10.The material of this second glued membrane 52 is identical with this first glued membrane 51, and this second glued membrane 52 and this first glued membrane 51 are all whole piece film pattern.With after solidifying this second glued membrane 52, partly remove the surface of this second glued membrane 52 according to UV light again with etching mode, to manifest these conductive structures 113.Then, utilize a suction nozzle 60 should go up wafer 10 heating and be engaged in this carrier 30 as one kind (Figure 10), make the connection post 213 of crystal grain 21 under these known good electrically connect the conductive structure 113 (as Figure 11) of crystal grain 11 on these known good, this moment this second glued membrane 52 with this first glued membrane 51 because heat fusing forms same one deck (i.e. this intermediate gelatine layer 35).
With reference to Figure 11, remove this suction nozzle 60, this carrier 30 as one kind and this glue-line 31.
With reference to Figure 12, carry out cutting technique, should go up wafer 10 and this insulating barrier 32 with cutting, and form several crystal grain assemblies 4.
In the present invention, owing to rearrange crystal grain 21 under these known good according to the wafer map that should go up wafer 10, therefore what can guarantee that crystal grain 11 electrically connects on these known good must be crystal grain 21 under these known good, like this then do not have wafer 10 and reach the yield loss (Yield Loss) that time wafer 20 causes because of the yield difference.
In the present invention, these crystal grain assemblies 4 can carry out following technology again.With reference to Figure 13, these crystal grain assemblies 4 are electrically connected on the substrate 36.In the present embodiment, this substrate 36 has a upper surface 361 and a lower surface 362, and the projection 214 of crystal grain 21 electrically connects the upper surface 361 of this substrate 36 under this known good.Afterwards, with reference to Figure 14, form the front 211 of a lower glue layer 37 crystal grain 21 under this known good and the upper surface 361 of this substrate 36 in a glue mode, to protect these projections 214.
With reference to Figure 15, form an adhesive material 38 to coat these crystal grain assemblies 4.In the present embodiment, this adhesive material 38 coats crystal grain 11, this insulating barrier 32, this intermediate gelatine layer 35 and this lower glue layer 37 on these substrate 36 upper surfaces 361, this known good.At last, form the lower surface 362 that several soldered balls 39 are positioned at this substrate 36, carry out cutting technique again to cut this substrate 36 and this adhesive material 38.
With reference to Figure 15, show the schematic diagram of analysing and observe of crystal grain assembly of the present invention.This crystal grain assembly 4 comprises crystal grain 21 under crystal grain 11 on the known good, the known good, an insulating barrier 32 and an intermediate gelatine layer 35.Preferably, this crystal grain assembly 4 more comprises a substrate 36, a lower glue layer 37, an adhesive material 38 and several soldered balls 39.
This insulating barrier 32 coats the periphery of crystal grain 21 under this known good, and in the present embodiment, this insulating barrier 32 is a kind of colloid as adhesive material, and it coats 21 4 sides of crystal grain under this known good.The side of crystal grain 11 trims on the side of this insulating barrier 32 and this known good, and the front of crystal grain 21 trims under the bottom surface of this insulating barrier 32 and this known good, and under this known good the thickness of crystal grain 21 less than the thickness of this insulating barrier 32.
This intermediate gelatine layer 35 is communicated with post 213 and these conductive structures 113 to protect these between the front 111 of crystal grain 11 on the back side 212 of crystal grain 21 under this known good and this known good.This intermediate gelatine layer 35 includes but not limited to following two kinds of patterns, first, this intermediate gelatine layer 35 is a primer, and it utilizes a some glue mode to form; The second, this intermediate gelatine layer 35 is formed by two glued membranes (as first glued membrane 51 and second glued membrane 52 of Fig. 9) merging.
This substrate 36 has a upper surface 361 and a lower surface 362, and the projection 214 of crystal grain 21 electrically connects the upper surface 361 of this substrate 36 under this known good.This lower glue layer 37 is positioned at the front 211 of crystal grain 21 under this known good and the upper surface 361 of this substrate 36, to protect these projections 214.This adhesive material 38 coats crystal grain 11, this insulating barrier 32, this intermediate gelatine layer 35 and this lower glue layer 37 on these substrate 36 upper surfaces 361, this known good.These soldered balls 39 are positioned at the lower surface 362 of this substrate 36.
Only above-described embodiment only is explanation principle of the present invention and effect thereof, but not in order to limit the present invention.Therefore, practise above-described embodiment being made amendment and changing in the personage of this technology and still do not take off spirit of the present invention.Interest field of the present invention should be listed as claims.
Claims (7)
1. the manufacture method of a crystal grain assembly may further comprise the steps:
(a) provide wafer and at least one wafer down on one, wafer and this time wafer wherein should be gone up wafer and have crystal grain and several known defective crystal grain of going up on several known good for testing on this;
(b) this at least one wafer down of cutting, to form several crystal grain down, crystal grain comprises crystal grain and several known defective crystal grain down under several known good under these;
(c) choose crystal grain under these known good, and crystal grain under these known good and these known defective crystal grain are down rearranged on a carrier, make under these known good the position of crystal grain on corresponding these known good in the position of crystal grain and corresponding these known defective positions of going up crystal grain, the position of these known defective crystal grain down;
(d) engage and to go up wafer and this carrier, make that crystal grain electrically connects crystal grain on these known good under these known good;
(e) remove this carrier; And
(f) carry out cutting technique, to form several crystal grain assemblies.
2. manufacture method as claimed in claim 1, wherein in this step (b), crystal grain has a front, a back side, several connection post and several projections under each known good, these are communicated with posts and are positioned under this known good within the crystal grain, these projections are positioned at the front of crystal grain under this known good, these are communicated with post and electrically connect these projections, and this step (c) utilizes a glue-line that the front of crystal grain under these known good is attached on this carrier.
3. manufacture method as claimed in claim 2, wherein this step (c) comprises more that afterwards a part removes the back side of crystal grain under these known good, to manifest the step that these are communicated with an end of posts.
4. manufacture method as claimed in claim 1, wherein this step (c) comprises more that afterwards one forms insulating barrier crystal grain under these known good, coating the step of crystal grain under these known good, and comprise more that afterwards one grinds a surface of this insulating barrier to appear the step of crystal grain under these known good.
5. manufacture method as claimed in claim 2, wherein in this step (a) on this known good crystal grain have a front, a back side and several conductive structures, these conductive structures are positioned at the front of crystal grain on this known good, this step (d) utilizes some glue mode to form primer on crystal grain under these known good earlier, should go up wafer heating again and be engaged in this carrier, and make the connection post of crystal grain under these known good electrically connect the conductive structure of crystal grain on these known good.
6. manufacture method as claimed in claim 2, wherein in this step (a) on this known good crystal grain have a front, a back side and several conductive structures, these conductive structures are positioned at the front of crystal grain on this known good, this step (d) may further comprise the steps:
(d1) fit one first glued membrane on crystal grain under these known good;
(d2) solidify this first glued membrane;
(d3) part removes the surface of this first glued membrane, is communicated with post to manifest these;
(d4) fit one second glued membrane on wafer on this, the material of this second glued membrane is identical with this first glued membrane;
(d5) solidify this second glued membrane;
(d6) part removes the surface of this second glued membrane, to manifest these conductive structures; And
(d7) should go up wafer heating and be engaged in this carrier, and make the connection post of crystal grain under these known good electrically connect the conductive structure of crystal grain on these known good, and this second glued membrane and this first glued membrane form same one deck.
7. manufacture method as claimed in claim 1 more comprises:
(g) these crystal grain assemblies are electrically connected on the substrate;
(h) form an adhesive material to coat these crystal grain assemblies; And
(i) carry out cutting technique to cut this substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101927492A CN102263039B (en) | 2010-05-24 | 2010-05-24 | Method for manufacturing crystal grain assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101927492A CN102263039B (en) | 2010-05-24 | 2010-05-24 | Method for manufacturing crystal grain assembly |
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| Publication Number | Publication Date |
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| CN102263039A CN102263039A (en) | 2011-11-30 |
| CN102263039B true CN102263039B (en) | 2013-08-14 |
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| CN2010101927492A Active CN102263039B (en) | 2010-05-24 | 2010-05-24 | Method for manufacturing crystal grain assembly |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11049816B2 (en) | 2018-11-20 | 2021-06-29 | Ningbo Semiconductor International Corporation | Alignment mark and semiconductor device, and fabrication methods thereof |
| CN111199951B (en) * | 2018-11-20 | 2021-12-03 | 中芯集成电路（宁波）有限公司 | Semiconductor device, manufacturing method thereof and manufacturing method of alignment mark |
| CN111128979B (en) * | 2019-11-22 | 2022-08-16 | 中国电子科技集团公司第十三研究所 | Wafer-level 3D chip preparation method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040204A (en) * | 1997-09-10 | 2000-03-21 | Robert Bosch Gmbh | Method of stacking chips with a removable connecting layer |
| CN101079372A (en) * | 2006-05-25 | 2007-11-28 | 索尼株式会社 | Substrate treating method and method of manufacturing semiconductor apparatus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10342980B3 (en) * | 2003-09-17 | 2005-01-05 | Disco Hi-Tec Europe Gmbh | Semiconductor chip stack formation method for manufacture of 3D-packages with function testing of chips for removal or unacceptable chips and replacement by acceptable chips |
| US20100109169A1 (en) * | 2008-04-29 | 2010-05-06 | United Test And Assembly Center Ltd | Semiconductor package and method of making the same |
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- 2010-05-24 CN CN2010101927492A patent/CN102263039B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040204A (en) * | 1997-09-10 | 2000-03-21 | Robert Bosch Gmbh | Method of stacking chips with a removable connecting layer |
| CN101079372A (en) * | 2006-05-25 | 2007-11-28 | 索尼株式会社 | Substrate treating method and method of manufacturing semiconductor apparatus |
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| CN102263039A (en) | 2011-11-30 |
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