CN102253354B - Self-diagnosable system and test circuit judges method - Google Patents

Abstract

The invention provides self-diagnosable system and test circuit judges method, it can interpolate that the normality of the test circuit for diagnostic test objective circuit.Self-diagnosable system according to an aspect of the present invention includes: test circuit, it includes the first and second diagnosing controllers, and the first and second diagnosing controllers judge the normality of test target circuit by the execution result using the test pattern in test target circuit；And test circuit judges unit, it for by relatively judging to test the normality of circuit compared with the normality judged result of the test target circuit exported from second opinion controller by the normality judged result of the test target circuit from the first diagnosing controller output.

Description

Self-diagnosable system and test circuit judges method

Cross-Reference to Related Applications

The application based on and require on April 23rd, 2010 propose Japanese patent application No. The benefit of priority of 2010-099582；The entire disclosure is incorporated herein by reference.

Technical field

The present invention relates to self-diagnosable system and test circuit judges method, and more specifically, Relate to including having the self-diagnosable system of the test circuit of redundant configuration and having superfluous for judgement The method of the test circuit of remaining configuration.

Background technology

In recent years, develop built-in self-test (BIST) circuit the most energetically, wherein will use In implementing LSI (large scale integrated circuit) the LSI tester function mounting tested in chip. Compared with the situation that LSI tester is wherein arranged on chip exterior, BIST circuit is used to make Decrease time and the cost of LSI test.

Japanese Unexamined Patent Application is announced No.2003-068865 and is disclosed a kind of self diagnosis The configuration of device.Self-diagnosis system includes the BIST electricity of the self diagnosis for performing semiconductor device Road.It is described with reference to Figure 11 and announces No.2003-068865 in Japanese Unexamined Patent Application Disclosed in the configuration of self-diagnosis system.Self-diagnosis system include semiconductor device 150 and 160, Master controller 400, BIST controller 200 and memorizer 300.In semiconductor device 150 and 160 Each include multiple functional device and multiple BIST circuit.Master controller 400 controls semiconductor device 150 and 160.BIST controller 200 controls BIST circuit.Memorizer 300 storage is used for controlling The program of BIST controller 200.

Semiconductor device 150 and 160 is intended to the semiconductor device being diagnosed.Semiconductor device 150 Including functional device 151 and 152 and BIST circuit 201 and 202.BIST circuit 201 performs functional device The self diagnosis of 151, and BIST circuit 202 performs the self diagnosis of functional device 152.BIST circuit 201 It is integrated in semiconductor device 150 with 202, and is respectively disposed at functional device 151 and 152 Vicinity.Similarly, semiconductor device 160 includes functional device 161 and 162 and BIST circuit 211 With 212.BIST circuit 211 performs the self diagnosis of functional device 161, and BIST circuit 212 performs The self diagnosis of functional device 162.BIST circuit 201 and 202 is integrated in semiconductor device 160, And it is respectively disposed at the vicinity of functional device 161 and 162.

BIST controller 200 is connected to BIST by holding wire 301,302,311 and 312 respectively Circuit 201,202,211 and 212, and send to BIST circuit 201,202,211 and 212 Conditions for diagnostics corresponding to functional device.Each in BIST circuit sends to functional device to be diagnosed The conditions for diagnostics received from BIST controller 200.Additionally, when receiving diagnostic result from functional device, Each BIST circuit sends described diagnostic result to BIST controller 200.BIST controller 200 will The diagnostic result received from each BIST circuit and the diagnosis expected value phase received from memorizer 300 Relatively.Memorizer 300 is connected to BIST controller 200 by holding wire 210, and stores BIST circuit is for diagnosing the diagnosis expected value of the conditions for diagnostics of each functional device, each functional device Diagnostic result with each functional device.

Master controller 400 is connected to external device (ED) (not shown), such as the test of test The human-computer interface device of device or such as keyboard.Additionally, master controller 400 is by holding wire 220 even Receive BIST controller 200, and respectively by input/output signal line 410,420,430 and 440 input/output terminals being connected to functional device.Master controller 400 is based on from outside human-machine interface The instruction of mouthful device, by using functional device to perform such as prevailing value computing or image procossing Process.Meanwhile, master controller 400 is also based on the diagnostic mode received from external test Perform the diagnosis of each functional device.Additionally, master controller 400 can be sent out to external test etc. Send semiconductor device functional device, the self diagnosis result that obtained by BIST controller 200.

Summary of the invention

Improve self diagnosis reliability field, force to obtain the functional safety of ECU level in Europe Certification, therefore vehicle etc. is checked and observes for standard by government.In this case, more come More need to diagnose functional device to be diagnosed and for improving the test for performing diagnosis control The countermeasure of the reliability of circuit.

The self diagnosis disclosed in No.2003-068865 is announced in Japanese Unexamined Patent Application Device performs the diagnosis of functional device to be diagnosed in self diagnosis.But, it is used for performing diagnosis The reliability non insurance of the test circuit controlled.In other words, if owing to operate at self diagnosis The noise of period and break down, or break down in test circuit, then even if ought be not Correctly during diagnostic function block, self diagnosis result is likely to be wrongly judged as correct result.

A first aspect of the present invention is self-diagnosable system, including: test circuit, it includes first With second opinion controller, described first and second diagnosing controllers are for by using in test The execution result of the test pattern in objective circuit judges the normality of test target circuit；With And test circuit judges unit, it is for by by the test mesh from the first diagnosing controller output The normality judged result of mark circuit and the test target circuit from the output of second opinion controller Normality judged result compares the normality relatively judging to test circuit.

Self-diagnosable system is used to make it possible to obtain from the diagnosis control of redundant configuration test circuit The normality judged result of the test target circuit of device processed output.Thus, it is possible to by compare from The normality judged result of diagnosing controller output judges to test the normality of circuit.

A second aspect of the present invention is test circuit judges method, including: by using in test The execution result of the test pattern in objective circuit judges the first He that test circuit includes The normality of the test target circuit in second opinion controller；And by diagnosing from first The normality judged result of the test target circuit of controller output is defeated with from second opinion controller The normality judged result of the test target circuit gone out is compared and is relatively judged to test the normal of circuit Property.

Test circuit judges method is used to make it possible to obtain from redundant configuration test circuit The normality judged result of the test target circuit of diagnosing controller output.Thus, it is possible to pass through The relatively normality judged result from diagnosing controller output judges to test the normality of circuit.

Illustrative aspects according to the present invention, it is possible to provide self-diagnosable system and test circuit judges side Method, it can interpolate that the normality of the test circuit for performing test target circuit diagnostics.

Accompanying drawing explanation

From the following description of some embodiment combining accompanying drawing, above and other aspects, advantage and Feature will be apparent from, wherein:

Fig. 1 is the block diagram illustrating self-diagnosable system according to a first embodiment of the present invention；

Fig. 2 is to illustrate the process for judging to test the normality of circuit according to first embodiment Flow chart；

Fig. 3 is the block diagram illustrating self-diagnosable system according to a second embodiment of the present invention；

Fig. 4 is the schematic diagram being shown in the signal sequence in the test circuit according to the second embodiment；

Fig. 5 is the block diagram illustrating self-diagnosable system according to a third embodiment of the present invention；

Fig. 6 is to illustrate the output result when not providing the inverting units according to the 3rd embodiment Schematic diagram；

Fig. 7 is to illustrate the output result when providing the inverting units according to the 3rd embodiment Schematic diagram；

Fig. 8 is to illustrate the process for judging to test the normality of circuit according to the 3rd embodiment Flow chart；

Fig. 9 is to illustrate the process for judging to test the normality of circuit according to the 3rd embodiment Flow chart；

Figure 10 is to illustrate the process for judging to test the normality of circuit according to the 3rd embodiment Flow chart；And

Figure 11 is to be shown in Japanese Unexamined Patent Application to announce in No.2003-068865 public The block diagram of the self-diagnosis system opened.

Detailed description of the invention

First embodiment

Referring now to accompanying drawing, embodiments of the invention are described.It is described with reference to Figure 1 according to this The exemplary configuration of the self-diagnosable system of bright first embodiment.Self-diagnosable system includes test target Circuit 10, test circuit judges unit 20 and test circuit 30.

First, the exemplary configuration of test target circuit 10 will be described.Test target circuit 10 wraps Include master controller 11.Master controller 11 performs the test pattern obtained from test circuit 30.Additionally, Master controller 11 exports the execution result of test pattern to test circuit 30.Test target circuit 10 It is performed for the functional device of numerical operation, image procossing etc..

It follows that the exemplary configuration that test circuit 30 will be described.Test circuit 30 includes diagnosis Controller 31 and 32 and memorizer 33.Diagnosing controller 31 includes comparing unit 34, keeps single Unit 35 and memory control unit 36.Similarly, diagnosing controller 32 include comparing unit 37, Holding unit 38 and memory control unit 39.Test circuit 30 operates in response to input clock. When reset signal is set to non-effective level (inactive level), diagnosing controller 31 He 32 are activated.

Memory control unit 36 is storing to read to memorizer 33 output storage control signal The data of storage in device 33.When obtaining memorizer control signal, memorizer 33 is to diagnosis control Device 31 and 32 and the data of master controller 11 output storage.Packet from memorizer 33 output Include test pattern, diagnosis expected value and the diagnosis control letter to perform in test target circuit 10 Number.

Test pattern is imported into master controller 11.Master controller 11 performs the test pattern obtained And check the normality of test target circuit 10.Diagnosis expected value is imported into each the most single Unit 34 and 37.When normally performing operation when performing test pattern, output diagnosis expected value. Each comparing unit 34 and 37 obtains the execution result of test pattern from master controller 11.The most single Unit 34 will diagnose expected value compared with the execution result of test pattern.Comparing unit 34 is to holding Unit 35 exports comparative result.Similarly, comparing unit 37 will diagnosis expected value and test pattern Execution result compare and export comparative result to holding unit 38.

Diagnosis control signal is the signal of the operation for controlling diagnosing controller 31 and 32.Such as, When obtain diagnosis control signal time, diagnosing controller 31 and 32 make comparing unit 34 and 37 start or Complete the comparison process between diagnosis expected value and the execution result of test pattern.Thus, can When operating with the comparison using diagnosis control signal to control in each comparing unit 34 and 37 Sequence.Additionally, during performing test pattern in test target circuit 10, can be examined by use Disconnected control signal controls to forbid from memory control unit 36 or 39 to the access of memorizer 33.

Each holding unit 35 and 38 keeps the comparative result obtained, and to test circuit judges Unit 20 exports comparative result as judging signal.As the ratio exported from comparing unit 34 and 37 Relatively result, exports qualified (PASS) when diagnosing expected value and mating with the execution result of test pattern Signal, and export defective when diagnosing expected value and not mating with the execution result of test pattern (FAIL) signal.PASS signal represents that test target circuit 10 normally operates, and FAIL Signal represents that test target circuit 10 the most normally operates, or represents at described test target electricity Road 10 occurs in that fault etc..

Test circuit judges unit 20 obtains from holding unit 35 and 38 and which provided PASS letter Number or the judgement signal of FAIL signal.When obtaining PASS signal from each holding unit 35 and 38 Time, test circuit judges unit 20 judges that test target circuit 10 and test circuit 30 are normal. When obtaining FAIL signal from each holding unit 35 and 38, test circuit judges unit 20 judges Test target circuit 10 is abnormal and tests circuit 30 is normal.When from holding unit 35 When obtaining different judged result with 38, specifically, when from holding unit 35 (or holding unit 38) obtain PASS signal and obtain FAIL signal from holding unit 38 (or holding unit 35) Time, test circuit judges unit 20 judges that test circuit 30 is abnormal.Now, due to test Circuit judges unit 20 judges that test circuit 30 is abnormal, so test circuit judges unit 20 The normality of test target circuit 10 cannot be judged.In this case, test circuit judges list Test target circuit 10 may also be judged it is abnormal by unit 20.Test circuit judges unit 20 to The output test target circuit such as external device (ED) 10 and the normality judged result of test circuit 30.

Referring next to Fig. 2, description is used for judgement test mesh according to a first embodiment of the present invention The process stream of the normality of mark circuit 10 and test circuit 30.

First, test circuit 30 judges that the reset signal obtained is set to significant level (active Or non-effective level (S1) level).In this case, such as by test circuit 30 The control unit (not shown) included is to judge the level of reset signal.When test circuit 30 Judge when reset signal is set to significant level, repeat the process of step S1.When test circuit 30 judge when reset signal is set to non-effective level, activate diagnosing controller 31 and 32 (S2).

It follows that memory control unit 36 is to memorizer 33 output storage control signal.Can Selection of land, memory control unit 39 can be to memorizer 33 output storage control signal.Accordingly, The data kept in the memory 33 are read and are exported diagnosing controller 31 and 32 and test Objective circuit 10 (S3).

It follows that master controller 11 obtains test pattern from memorizer 33, and surveyed by use Die trial formula carrys out diagnostic test objective circuit 10 (S4).Then, master controller 11 is to test circuit The execution result (S5) of 30 output test patterns.

It follows that comparing unit 34 by use the execution result obtained from master controller 11 and The expected value that diagnoses obtained from memorizer 33 judges the normality (S6) of test target circuit 10. When performing result and mating with diagnosis expected value, comparing unit 34 exports PASS to holding unit 35 Signal.PASS signal represents that test target circuit 10 is normal.When performing result and diagnostic period When prestige value is not mated, comparing unit 34 arranges error flag, or exports FAIL to holding unit 38 Signal (S8).FAIL signal represents that test target circuit 10 is abnormal, or represents occur Fault.Comparing unit 37 also performs the similar process that processes with comparing unit 34, and (S9 arrives S11)。

It follows that diagnosing controller 31 or 32 judges to diagnose whether end address is set to from depositing The data (S12) that reservoir reads.When diagnosing end address and not being set, address is incremented by (S15) And repeat process after step s 3.When diagnosing end address and being set, complete test The diagnosis of objective circuit 10.

After completing the diagnosis of test target circuit 10, test circuit judges unit 20 judges to survey Examination objective circuit 10 and the normality of test circuit 30.As it has been described above, test circuit judges unit 20 diagnostic results based on the test target circuit 10 exported from diagnosing controller 31 and 32 judge Each normality in test target circuit 10 and test circuit 30.Then, test circuit is sentenced Disconnected unit 20 such as exports test target circuit 10 to external device (ED) etc. and tests the normal of circuit 30 Property judged result (S14).

As it has been described above, use self-diagnosable system according to a first embodiment of the present invention to sentence The normality of disconnected test target circuit 10 and can interpolate that the normality of test circuit 30.Thus, Normality judged result reliable of test target circuit 10 in test circuit 30 can be improved Property.

Second embodiment

Referring now to Fig. 3, self-diagnosable system according to a second embodiment of the present invention will be described.At figure Self-diagnosable system shown in 3 is in addition to the assembly of self-diagnosable system shown in FIG Also include delay cell 41 to 44, comparator 45 and holding unit 46.Other are configured similarly to As shown in Fig. 1, the same reference numerals being therefore used in Fig. 1 using is carried out Hereinafter describe.

Delay cell 41 to 44 exports the signal of reception with a clock delay.

Delay cell 41 is connected between memorizer 33 and comparing unit 37.Delay cell 41 is also It is connected between master controller 11 and comparing unit 37.Delay cell 41 postpones from memorizer 33 Output timing to the diagnosis expected value of comparing unit 37 output.Accordingly, comparing unit 37 with The sequential of the diagnosis expected value 121 obtained by comparing unit 34 is compared to have and is lingeringly obtained from prolonging The diagnosis expected value 122 of unit 41 output late.Additionally, delay cell 41 postpones from master controller 11 Output timing to the execution result of comparing unit 37 output.As a result, comparing unit 37 with than The sequential of relatively unit 34 acquisition execution result 131 is compared to have and is lingeringly obtained from delay cell 41 The execution result 132 of output.This prevent the diagnosis being exported diagnosing controller 31 and 32 by redundancy Expected value and execution result break down due to impacts such as noises simultaneously.

Delay cell 42 postpones the diagnosis control signal exported from memorizer 33 to diagnosing controller 32 The output timing of 112.Accordingly, diagnosing controller 32 is to obtain diagnosis control with diagnosing controller 31 The sequential of signal 111 is compared has the diagnosis control letter lingeringly obtained from delay cell 42 output Numbers 113.This allows diagnosing controller 31 and 32 to operate with different timings.Such as, diagnosis control Since device 32 processed, a clock delay of self diagnosis controller 31 operates.Allow diagnosis control Device 31 and 32 operates with different timings, thus prevent diagnosing controller 31 and 32 owing to making an uproar Sound etc. affect and break down simultaneously.

Delay cell 43 is connected between holding unit 35 and test circuit judges unit 20.Prolong Unit 43 postpones from holding unit 35 to the judgement signal of test circuit judges unit 20 output late The output timing of 141.Postpone to judge that the output timing of signal 141 allows to from diagnosis control The output timing judging signal 142 of device 32 output and the judgement signal from delay cell 43 output The output timing of 143 matches, and wherein judges that the output timing of signal 142 diagnoses from by control Control signal 113 arrives test circuit judges with diagnosing controller 32 output postponing to carry out operating Unit 20.This allow test circuit judges unit 20 by use from diagnosing controller 31 and 32 with The judgement signal 142 of identical timing acquisition and judge that signal 143 is to judge test target circuit 10 He The normality of test circuit 30.

Delay cell 44 postpone from memory control unit 36 output memorizer control signal and The memorizer control signal postponed to comparator 45 output.Especially, in memorizer control signal Middle setting comprises the address of the data read from memorizer 33.Hereinafter, from memory control unit 36 and 39 are called address signal to the memorizer control signal of memorizer 33 output.

Different from first embodiment, in the second embodiment of the present invention, when reset signal is set When being set to non-effective level, diagnosing controller 31 is activated, and since self diagnosis controller 31 Delay activate diagnosing controller 32.Diagnosing controller 31 and 32 is activated and memorizer control Unit 36 and 39 processed is to memorizer 33 OPADD signal.In short, to control single with memorizer The address signal of unit 36 output is compared to have and is lingeringly exported from memory control unit 39 output Address signal.From memory control unit 36 and 39 OPADD signal to judge to be output to The normality of the address signal of memorizer 33.Comparator 45 compares from memory control unit 36 He The address signal of 39 outputs.When address signal matches, address signal is judged as by comparator 45 PASS signal is exported normally and by holding unit 46 to test circuit judges unit 20.With Time, when the address signal exported from memory control unit 36 and 39 does not mates, comparator 45 Address signal is judged as abnormal and by holding unit 46 to test circuit judges unit 20 Output FAIL signal.Now, since, the delay of self diagnosis controller 31 activates diagnosing controller 32.Accordingly, it is delayed by unit 44 from the address signal 103 of diagnosing controller 31 output and postpones, and And from described delay cell 44 OPADD signal 104.This allows comparator 45 with identical sequential Obtain the address signal 104 from memory control unit 36 output and control from memorizer single The address signal 102 of unit 39 output.

As a result, comparator 45 can be by using address signal 102 He with identical timing acquisition 104 normality judging address signal.

Alternatively, multiple comparators 45 can be connected in parallel to each other layout and each comparator 45 permissible Judge the normality of address signal.In such a case, it is possible to collect sentencing from comparator 45 Disconnected result, and any judged result can be selected and be output to test circuit judges unit 20。

Referring next to Fig. 4, during by the output of the signal described according to a second embodiment of the present invention Sequence.Test circuit 30 operates based on the clock obtained.Clock (does not shows from clock generator Go out) etc. provide.Control unit (not shown) from the device including self-diagnosable system etc. come defeated Go out reset signal.When reset signal is set to non-effective level (low level), the most sharp Live diagnosing controller 31 and activate diagnosing controller 32 with a clock delay.

From delay cell 41 output diagnosis expected value 122, and therefore with diagnosis expected value 121 phase Than exporting while there is a clock delay described diagnosis expected value 122.Similarly, from delay cell 41 outputs perform result 132, and therefore there is a clock delay compared with performing result 131 Ground output performs result 132.

Export diagnosis control signal 113 from delay cell 42, and therefore with diagnosis control signal 111 compare and export diagnosis control signal 113 with having a clock delay.Accordingly, diagnosis control Device 32 to operate with having a clock delay compared with diagnosing controller 31.

Owing to diagnosing controller 32 is with having a clock delay compared with diagnosing controller 31 quilt Activate, so to have a clock delay ground OPADD signal compared with address signal 101 102.Additionally, due to from delay cell 44 OPADD signal 104, thus with address signal 101 compare with having clock delay OPADD signal 104.Accordingly, address signal 104 Output timing mates with the output timing of address signal 102.In other words, delay cell 42 and 44 There is identical retardation as a result, when comparator 45 obtains address signal 104 and 102, prolong It is cancelled late.

Signal 142 is judged to export while there is compared with judging signal 141 clock delay.This Be because diagnosing expected value 122 and diagnosis perform result 132 with diagnosis expected value 121 and performing 131 sequential being input to comparing unit 34 are compared and are imported into having a clock delay as a result Comparing unit 37.In this case, to have a clock delay compared with judging signal 141 Ground output is from the judgement signal 143 of delay cell 43 output.Accordingly, it is judged that the output of signal 143 Sequential is mated with the output timing judging signal 142.In other words, delay cell 41 and delay are single Unit 43 has identical retardation as a result, judge signal when test circuit judges unit 20 obtains When 142 and 143, postpone to be cancelled.Test circuit judges unit 20 exports based on identical sequential Judge signal 142 and 143 judge test circuit 30 normality.

As it has been described above, use the delay cell of self-diagnosable system according to a second embodiment of the present invention 41 allow redundant signals to export from memorizer 33 and master controller 11 with different timings.This prevents Redundant signals breaks down due to impacts such as noises simultaneously.Additionally, use delay cell 42 The diagnosing controller 31 and 32 making redundancy can operate with different timings, is therefore prevented from diagnosis Controller 31 and 32 breaks down due to impacts such as noises simultaneously.

Additionally, use delay cell 43 and 44, by using test circuit judges unit 20 He With the signal of identical timing acquisition in comparator 45, enabling carry out testing the normal of circuit 30 Property judge.

3rd embodiment

Referring now to Fig. 5, by the example of description self-diagnosable system according to a third embodiment of the present invention Property configuration.Self-diagnosable system shown in Figure 5 is except self diagnosis system shown in figure 3 Inverting units 51 to 57, holding unit 58 and 59, error detection list is also included outside the assembly of system Unit 60 and 61, buffer 62 to 64, branch units 65.Shown in other are configured similarly in figure 3 The configuration gone out, the same reference numerals being therefore used in Fig. 3 using is to carry out following description.

Inverting units 51 is connected in master controller 11, delay cell 41 and comparing unit 34 Each.Inverting units 51 inverts the value of the execution result from master controller 11 output.Inverting units The 51 each outputs in comparing unit 34 and delay cell 41 are for representing the execution result of reversion Signal.Inverting units 52 inverts the value of execution result from delay cell 41 output, and to The value of comparing unit 37 output reversion.Export additionally, inverting units 52 inverts from delay cell 41 Diagnosis expected value and to comparing unit 37 output reversion diagnosis expected value.Accordingly, compare Unit 34 by reversion execution result compared with the diagnosis expected value exported from memorizer 33.? In this case, comparing unit 34 output PASS letter when performing result and being different from diagnosis expected value Number, and the output FAIL signal when performing result coupling diagnosis expected value.Similarly, compare Unit 37 is by diagnosis execution result compared with the diagnosis expected value of reversion, and described diagnosis performs knot Fruit is inverted twice and is restored to the value from master controller 11 output.

Inverting units 55 inverts the judgement signal from holding unit 38 output, and to test circuit The judgement signal of judging unit 20 output reversion.

The judgement that will be described in now testing circuit judges unit 20 processes.Such as, when high electricity Ordinary mail number is set to, when the judgement signal of diagnosing controller 31 output, make PASS and judge, And when low level signal is set to judge signal, makes FAIL and judge.From diagnosis control The judgement signal of device 32 output is inverted unit 55 and inverts.Accordingly, it is set when high level signal For export from diagnosing controller 32 judgement signal time, make FAIL and judge, and work as low level When signal is set to judge signal, makes PASS and judge.

When being judged as PASS from the output of diagnosing controller 31 and 32, test circuit judges Unit 20 judges that test target circuit 10 and test circuit 30 are normal.When from diagnosis control When the output of device 31 and 32 is judged as FAIL, test circuit judges unit 20 judges test target Circuit 10 is abnormal and tests circuit 30 is normal.When from diagnosing controller 31 and 32 One of output when being judged as FAIL, test circuit judges unit 20 judges that test circuit 30 is Abnormal.

Inverting units 56 makes the memorizer exported by delay cell 44 from memory control unit 36 Control signal (address signal) inverts, and controls to the memorizer of comparator 45 output reversion Signal.Accordingly, when the memorizer control signal exported from memory control unit 36 be different from from During the memorizer control signal that memory control unit 39 exports, comparator 45 judges memorizer control Signal processed is normal.When memorizer control signal is mated, comparator 45 judges memorizer control Signal processed is abnormal.When the comparative result signal exported from comparator 45 represents memorizer control When signal is abnormal, test circuit judges unit 20 judges that test circuit 30 is abnormal.

Use inverting units 51,52,55 and 56 as above can improve the opposing to noise. The reason of this situation is described below with reference to Fig. 6 and 7.

Fig. 6 illustrates the example that the non-inverted that wherein signal is not inverted compares.During cycle T, When voltage level increase due to noise and low level signal be judged as high level signal (as Represented by the dotted line in cycle T) time, signal A and B is judged as high level signal.According to This, when being added on signal by noise, signal A and B is mutual with high level during cycle T Coupling.Therefore, the comparative result between signal A and B is judged as normally.

Meanwhile, Fig. 7 illustrates the example that the reversion that wherein signal B is inverted is compared.In the cycle T phase Between, when voltage level increases due to effect of noise and low level signal is judged as high electricity During ordinary mail number (as by represented by the dotted line in cycle T), signal A and B during cycle T with High level mates.Accordingly, the comparative result between signal A and B is judged as exception.Thus During cycle T, when signal A is reversed to high level signal due to noise, can detect Mistake.Therefore, inverting units is used can to improve the opposing to noise.

Return to Fig. 5, the exemplary of self-diagnosable system according to a third embodiment of the present invention will be described Configuration.The diagnosis expected value exported to diagnosing controller 31 from memorizer 33 and diagnosis control signal And diagnosis expected value and the diagnosis control signal exported to diagnosing controller 32 from memorizer 33 leads to Cross different path output.Specifically, it is branched unit 65 branch from the signal of memorizer output, And the signal of branch is output to diagnosing controller 31 and 32.Owing to being output to diagnosis The signal of controller 31 and 32 is exported by different paths, even if so in test circuit 30 Noise occurs, it is also possible to reduce the probability that mistake occurs simultaneously.

Longer individual path makes it possible to eliminate owing in identical path, transmission signal is led The influence of noise caused.To this end, branch units 65 is preferably arranged in the vicinity of memorizer 33.Example As, branch units can be disposed such that the distance of 65 becomes short from memorizer to branch units In from branch units 65 to the distance of diagnosing controller 31 and 32.

Inverting units 53 inverts the diagnosis control letter exported from memorizer 33 to diagnosing controller 32 Number, and to the diagnosis control signal of delay cell 42 output reversion.Inverting units 54 is from delay Unit 42 obtains the diagnosis control signal of reversion, and inverts the to be output of acquisition further and arrive The signal of diagnosing controller 32.As it has been described above, diagnosis control signal is used for starting or completing to compare The comparison process of unit 34 and 37.Accordingly, when the impact due to noise etc. is at diagnosing controller 31 With in the diagnosis control signal of 32 simultaneously occur mistake time, it is provided that inverting units 53 and 54 allows to examine Disconnected controller 31 performs different operations with 32.Such as, one of diagnosing controller can start ratio Relatively process, and another of diagnosing controller can not start comparison process.In this case, Test circuit judges unit 20 can detect survey based on the output result of diagnosing controller 31 and 32 The fault of examination circuit 30.

Error detection units 60 detection is branched unit 65 branch and is output to from memorizer 33 The mistake of the data of diagnosing controller 31 and master controller 11.Such as, such as check bit is used Error-detecting code performs error detection.Error detection units 60 passes through holding unit 58 to test Circuit judges unit 20 output is used for representing whether data have vicious error detection result letter Number.

Error detection units 61 detection is branched unit 65 branch and is output to from memorizer 33 The mistake of the data of diagnosing controller 32.As error-detecting method, use and error detection list Unit's 60 similar methods.Error detection units 61 is defeated to inverting units 57 by holding unit 59 The testing result that makes mistake signal.Inverting units 57 reversion obtain error detection result signal and Signal to test circuit judges unit 20 output reversion.Test circuit judges unit 20 inverts also And the error detection result signal exported from error detection units 60 and 61 is compared.As above Described, use inverting units 57 to improve the opposing to noise.

Will be described in now by using error detection result in test circuit judges unit 20 Signal carries out testing the normality of circuit 30 and judges.Such as, when exporting from error detection units 60 Erroneous detection signal when being set to high level, it is judged that mistake detected and make FAIL and sentence Disconnected.Meanwhile, when erroneous detection signal is set to low level, it is judged that be not detected by mistake And make PASS to judge.Additionally, due to from the error detection letter of error detection units 61 output Number being inverted unit 57 inverts, so when erroneous detection signal is set to high level, making PASS judges.Meanwhile, when erroneous detection signal is set to low level, makes FAIL and judge.

In this case, when being judged as PASS from the output of error detection units 60 and 61 Time, test circuit judges unit 20 judges that test circuit 30 is normal.When from error detection When the output of unit 60 and 61 is judged as FAIL, test circuit judges unit 20 judges test electricity Road 30 is abnormal.When being also judged as from the output of one of error detection units 60 and 61 During FAIL, test circuit judges unit 20 judges that test circuit 30 is abnormal.

As it has been described above, test circuit judges unit 20 is defeated from diagnosing controller 31 and 32 by using Go out judge signal, from error detection units 60 and 61 output erroneous detection signal and from than The comparative result signal of relatively device 45 output judges to test the normality of circuit 30.Thus, when sentencing At least one in disconnected result represents when test circuit 30 is judged as abnormal, tests circuit judges Unit 20 judges that test circuit 30 is abnormal.Meanwhile, test electricity is represented when all judged results When road 30 is judged as normal, test circuit judges unit 20 may determine that test circuit 30 is just Normal.

Buffer 62 obtains the memorizer control signal from memory control unit 36 output.Additionally, The memorizer control signal that buffer 62 obtains to memorizer 33 output.Buffer 63 obtains from depositing The test pattern of reservoir 33 output, diagnosis expected value and diagnosing controller control signal.Buffer 63 export, to diagnosing controller 31 and master controller 11, the signal etc. obtained.Buffer 64 obtain from The diagnosis expected value of memorizer 33 output and diagnosing controller control signal.Then, buffer 64 The signal etc. obtained to diagnosing controller 32 output.Use buffer 62 to 64 example as above As prevented the noise produced between buffer 62 and memorizer 33 memory control unit 36 He Sent between buffer 62.

Referring next to Fig. 8 to 10, description is used for according to a third embodiment of the present invention be used for judge The process stream of the normality of test target circuit 10 and test circuit 30.The flow chart of Fig. 8, at figure In flow chart shown in 2, increase branch process after step s 3 and before step S12.? After step S3, described flow branching is to step S16 shown in fig .9 and S19 and described Branch merged with main flow before step S12.Additionally, after step s 3, described flow branching arrives Step S22 shown in Fig. 10, and described branch merged with main flow before step S12. Other process the process being similar to Fig. 2, therefore omit detailed description.

Referring next to Fig. 9, the process stream of error detection units 60 and 61 will be described.Error detection The unit 60 data to reading from memorizer 33 perform error detection (S16).It follows that mistake Whether detector unit 60 misjudgment testing result is normal (S17).Here, when misdeeming When error detection result is abnormal or when errors are detected, error detection units 60 arranges mistake Mark (S18).Similarly, error detection units 61 performs the process of step S19 to S21.When When completing error detection process in error detection units 60 and 61, perform the place after step S12 Reason.

Referring next to Figure 10, the process stream of comparator 45 will be described.Comparator 45 will be from storage The memorizer control signal of device control unit 36 and 39 output compares (S22).From storage The memorizer control signal of device control unit 36 is exported by inverting units 56.Accordingly, comparator 45 perform reversion compares.Then, comparator 45 judges that comparative result is the most normal (S23).When During two memorizer control signal couplings, comparator 45 judges in one of memorizer control signal Occur abnormal, and error flag (S24) is set.When two memorizer control signals are not mated Time, comparator 45 judges that memorizer control signal is normal.When completing in a comparator 45 During comparison process between memorizer control signal, perform the process after step S12.

As it has been described above, provide reversion single in self-diagnosable system according to a third embodiment of the present invention Unit, thus improves the opposing to noise.

Additionally, the data from memorizer 33 output are branched near memorizer 33, and surveying Sent in examination circuit 30, thus improved the opposing to noise further.

In addition it is possible to use error detection units 60 and 61 judges the data from memorizer 33 output Normality.This improves and is output to the data of diagnosing controller 31 and 32 and is output to survey The reliability of the data of examination objective circuit 10.Thus, also improve examining of test target circuit 10 The reliability of disconnected result.

Note, the invention is not restricted to above example, but can be without departing from the scope of the invention In the case of according to circumstances modify.Such as, those of ordinary skill in the art can be according to the phase Hope and combine first, second, and third embodiment.

Although describing the present invention with regard to several embodiments, but those skilled in the art should Recognize and can implement various amendment and the present invention in the spirit and scope of the appended claims It is not limited to above-mentioned example.

Additionally, the scope of claim is not restricted to the described embodiments.

Additionally, it should be noted that applicant is intended to encompass the equivalent way of all authority requirement element, Even if in course of the review, amendment is also such after a while.

Claims (15)

1. a self-diagnosable system, including:

Test circuit, described test circuit includes the first and second diagnosing controllers, and described first and second diagnosing controllers judge the normality of described test target circuit by the execution result using the test pattern in test target circuit；

Test circuit judges unit, described test circuit judges unit by relatively judging the normality of described test circuit compared with the normality judged result of the described test target circuit exported from described second opinion controller by the normality judged result of the test target circuit from described first diagnosing controller output；And

First delay circuit, described first delay circuit for obtaining the sequential of the expected value obtained when performing the test pattern stored in memory relative to described first diagnosing controller, postpone described second opinion controller and obtain the sequential of described expected value from described memorizer

Wherein, described test circuit includes the memorizer storing expected value, and

Described first and second diagnosing controllers include memorizer control circuit, and described memorizer control circuit controls to read described expected value from described memorizer and export control signal from described memorizer, and

Described first and second diagnosing controllers, in response to described control signal, by the execution result comparing test pattern and the expected value read from described memorizer, determine the normality of described test target circuit.

2. self-diagnosable system as claimed in claim 1, wherein, described first and second diagnosing controllers by being compared to judge the normality of described test target circuit by the execution result of the test pattern in described test target circuit and the described expected value obtained when performing the test pattern stored in which memory.

3. self-diagnosable system as claimed in claim 1, wherein, described first delay circuit is further used for obtaining the sequential of the executions result of test pattern in described test target circuit relative to described first diagnosing controller, postpones the sequential of the execution result of described second opinion controller acquisition test pattern in described test target circuit.

4. self-diagnosable system as claimed in claim 1, farther includes:

First circuit for reversing, described first circuit for reversing is for inverting the signal of the execution result of the test pattern represented in described test target circuit, and the signal inverted to described first diagnosing controller output；And

Second circuit for reversing, the execution result of the test pattern that described second circuit for reversing exports from described first circuit for reversing for reversion further.

5. self-diagnosable system as claimed in claim 1, farther includes:

3rd circuit for reversing, the expected value that described 3rd circuit for reversing obtains when performing the test pattern stored in which memory for reversion, and to the expected value of described second opinion controller output reversion.

6. self-diagnosable system as claimed in claim 2, wherein,

Described memorizer includes the described control signal in the time sequential routine for controlling described first and second diagnosing controllers, and

Described self-diagnosable system farther includes the 3rd delay circuit, and described 3rd delay circuit, for obtaining the sequential of described control signal relative to described first diagnosing controller, postpones described second opinion controller and obtains the sequential of described control signal.

7. self-diagnosable system as claimed in claim 6, farther includes:

4th delay circuit, described 4th delay circuit for postpone from described first diagnosing controller output normality judged result and to described test circuit judges unit output postpone normality judged result so that described test circuit judges unit with identical timing acquisition from described first diagnosing controller output normality judged result and from described second opinion controller output normality judged result.

8. self-diagnosable system as claimed in claim 6, farther includes:

4th circuit for reversing, the control signal that described 4th circuit for reversing exports from described memorizer for reversion, and export the control signal of reversion；And

5th circuit for reversing, the control signal that described 5th circuit for reversing exports from described 4th circuit for reversing for reversion further, and to the control signal of described second opinion controller output reversion.

9. self-diagnosable system as claimed in claim 1, wherein

Each output to memorizer in described first and second diagnosing controllers is used for reading test pattern, expected value and the memorizer control signal of control signal from described memorizer, and described memorizer stores described test pattern,

Described test circuit includes comparing unit, and described comparing unit is used for compare from the memorizer control signal of described first and second diagnosing controllers outputs, and

Described test circuit judges unit judges the normality of described memorizer control signal according to the comparative result of described comparing unit.

10. self-diagnosable system as claimed in claim 9, farther includes:

5th delay circuit, described 5th delay circuit is for the memorizer control signal postponed from described first diagnosing controller output and the memorizer control signal postponed to the output of described comparing unit so that memorizer control signal that described comparing unit export from described second opinion controller with identical timing acquisition and the memorizer control signal exported from described first diagnosing controller.

11. self-diagnosable systems as claimed in claim 1, farther include:

6th circuit for reversing, the normality judged result that described 6th circuit for reversing exports from one of first and second diagnosing controllers for reversion, and to the normality judged result of described test circuit judges unit output reversion.

12. self-diagnosable systems as claimed in claim 10, farther include:

7th circuit for reversing, the memorizer control signal that described 7th circuit for reversing exports from one of first and second diagnosing controllers for reversion, and to the memorizer control signal of described comparing unit output reversion.

13. self-diagnosable systems as claimed in claim 1, farther include:

First error detect circuit, described first error detect circuit is for judging from memorizer to the normality of the signal of described first diagnosing controller output, and exports described signal to described test circuit judges unit；

Second error detect circuit, described second error detect circuit is for judging the normality of signal exported from described memorizer to described second opinion controller；And

8th circuit for reversing, described 8th circuit for reversing is for reversion and exports the expression signal from the judged result of described second error detect circuit output.

14. self-diagnosable systems as claimed in claim 1, farther include:

Branch units, described branch units is used for permission and to the path being used for the described first diagnosing controller described signal of output and is used for the path of the described second opinion controller described signal of output from the signal branch of memorizer output,

Wherein, described branch units is arranged such that to be more than from described memorizer to the distance of described branch units from described branch units to the distance of described first and second diagnosing controllers.

15. 1 kinds of test circuit judges methods, including:

In the first and second diagnosing controllers that test circuit includes, the normality of described test target circuit is judged by the execution result using the test pattern in test target circuit；

By the normality judged result of the test target circuit from described first diagnosing controller output relatively being judged compared with the normality judged result of the test target circuit exported from described second opinion controller the normality of described test circuit；And

Obtained the sequential of the expected value obtained when performing the test pattern stored in memory by the first delay circuit relative to described first diagnosing controller, postpone described second opinion controller and obtain the sequential of described expected value from described memorizer,

Wherein, described first diagnosing controller and described second opinion controller, by the execution result comparing test pattern and the expected value read in control signal from memory response, determine the normality of described test target circuit, and

Controlled the reading of described expected value by described first and second diagnosing controllers, and exported described control signal by the memorizer control circuit included by described first and second diagnosing controllers.