CN102244030A - Silicon on insulator diode device and manufacturing method thereof - Google Patents
Silicon on insulator diode device and manufacturing method thereof Download PDFInfo
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- CN102244030A CN102244030A CN2011101835391A CN201110183539A CN102244030A CN 102244030 A CN102244030 A CN 102244030A CN 2011101835391 A CN2011101835391 A CN 2011101835391A CN 201110183539 A CN201110183539 A CN 201110183539A CN 102244030 A CN102244030 A CN 102244030A
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Abstract
The invention provides a manufacturing method of a silicon on insulator diode device. The method comprises the following steps: providing an SOI (silicon on insulator) substrate which comprises a base layer, a buried oxide layer and a device layer, wherein the buried oxide layer is positioned above the base layer; the device layer is positioned above the buried oxide layer; forming a groove by etching part of the device layer, and forming a first shallow groove isolation in the groove; forming a first type region in the device layer below the first shallow groove isolation; and forming a first type injection region and a second type injection region respectively in the device layer at two sides of the first type region, wherein the injection dosages of the first type injection region and the second type injection region are greater than the injection dosage of the first type region. Correspondingly, the invention also provides a silicon-on-insulator diode device. According to the invention, not only is the existence of parasitic capacitance and side pn junction avoided, but also the pn junction of the diode device is effectively prevented from being in short circuit with the contact layer; and the process is simple, and is compatible with the existing CMOS (complementary metal-oxide-semiconductor transistor) process technology.
Description
Technical field
The present invention relates to semiconductor fabrication, relate in particular to a kind of silicon-on-insulator diode component and manufacture method thereof.
Background technology
Diode is called crystal diode again, is a kind of two-terminal device with unilateal conduction.Diode is one of the semiconductor device the earliest that is born, and its application is very extensive, all can be used in nearly all electronic circuit, plays important effect.
(Silicon-On-Insulator, SOI) technology is to have introduced oxygen buried layer between top layer silicon and silicon substrate to silicon-on-insulator.By on insulator, forming semiconductive thin film, SOI had body silicon incomparable advantage: realized the dielectric isolation of components and parts in the integrated circuit, and thoroughly eliminated the parasitic latch-up in the body silicon CMOS circuit.In addition, the integrated circuit that adopts SOI to make has also that parasitic capacitance is little, integration density is high, speed is fast, technology is simple, short-channel effect is little and is specially adapted to advantage such as low-voltage and low-power dissipation circuit.Therefore, the SOI technology has been subjected to increasing concern, progressively becomes the low pressure of deep-submicron, the mainstream technology of low power consumption integrated circuit.
At present, normally used diode comprises that gate control diode and silicide stop (Silicide Blocking, SAB) diode in silicon-on-insulator CMOS technology.Below, above-mentioned two kinds of diodes commonly used are carried out simple explanation.
At first, please refer to Fig. 1, Fig. 1 is the structural profile schematic diagram of employed gate control diode in the present silicon-on-insulator CMOS technology.As shown in the figure, this gate control diode comprises silicon substrate 102, be positioned at the oxygen buried layer 101 on this silicon substrate 102 and be positioned at top layer silicon 105 on this oxygen buried layer 101, there is gate oxide 103 on the described top layer silicon 105 and is being positioned at polysilicon layer 107 on this gate oxide 103, wherein, these polysilicon layer 107 common electricity ground connection.For the n+-p-p+ diode component, the device layer 105 (promptly being numbered 104 zone) that the n+ injection zone is positioned at polysilicon layer 107 internal zone dividing territory 107a and is positioned at this subregion 107a one side, p+ injection zone polysilicon layer 107 internal zone dividing territory 107b and the device layer 105 (promptly being numbered 106 zone) that is positioned at this subregion 107b one side are in the device layer 105 of p type zone (not shown) between described n+ injection zone and p+ injection zone; For the p+-n-n+ diode component, the device layer 105 (promptly being numbered 104 zone) that the p+ injection zone is positioned at polysilicon layer 107 internal zone dividing territory 107a and is positioned at this subregion 107a one side, n+ injection zone polysilicon layer 107 internal zone dividing territory 107b and the device layer 105 (promptly being numbered 106 zone) that is positioned at this subregion 107b one side are in the device layer 105 of n type zone (not shown) between described p+ injection zone and n+ injection zone.
The shortcoming of above-mentioned gate control diode is: (1) needs to generate gate oxide 103 and polysilicon layer 107, thereby causes all relative complex of device architecture and preparation technology; (2) exist the pn of a parasitism to tie (position that dotted line encloses in reference to figure 1) at polysilicon layer 107, need extra silicide process that its electricity short circuit is got up; (3) between polysilicon layer 107, gate oxide 103 and n type or p type zone, there is parasitic capacitance.
Then, please refer to Fig. 2, Fig. 2 is the generalized section of employed SAB diode structure in the present silicon-on-insulator CMOS technology.As shown in the figure, this SAB diode comprises silicon substrate 202, is positioned at the oxygen buried layer 201 on this silicon substrate and is positioned at top layer silicon 205 on this oxygen buried layer 201.For the n+-p-p+ diode component, n+ injection zone 204 and p+ injection zone 206 all are positioned at described top layer silicon 205, be p type zone between its two, and the degree of depth in p type zone are greater than the degree of depth of described n+ injection zone 204 and p+ injection zone 206; For the p+-n-n+ diode component, p+ injection zone 204 and n+ injection zone 206 are positioned at described top layer silicon 205 equally, between its two is n type zone, and the degree of depth in n type zone is greater than the degree of depth of described p+ injection zone 204 and n+ injection zone 206.There is contact layer 207 (as metal silicide layer) in upper surface at described p+ injection zone and n+ injection zone, be used to reduce the contact resistance of n+ injection zone and p+ injection zone, between described contact layer 207, also have mask layer 203, be used to prevent that the pn knot of diode is touched layer 207 short circuit and the phenomenon that is short-circuited.
Above-mentioned SAB diode is compared with gate control diode, owing to need not to generate gate oxide and polysilicon layer, so its structure is all relative with manufacture craft simple.But, the described SAB diode part that still comes with some shortcomings, promptly, there is side direction pn knot (position that encloses with reference to dotted line among the figure 2) between p+ injection zone and the n type zone in the p+-n-n+ diode (in the n+-p-p+ diode for n+ injection zone and p type zone), the existence of this side direction pn knot, make that area is identical and SAB diodes that girth is different have different I-E characteristics and capacitance-voltage characteristics, thereby brought certain inconvenience for circuit design.
Therefore, need a kind of silicon-on-insulator diode component and manufacture method thereof that addresses the above problem of proposition badly.
Summary of the invention
The purpose of this invention is to provide a kind of silicon-on-insulator diode component and manufacture method thereof, not only avoided the existence of parasitic capacitance and side direction pn knot, the pn knot that can also prevent diode component effectively is touched a layer short circuit, and technology is simple, and is compatible mutually with present main stream of CMOS technology.
According to an aspect of the present invention, provide a kind of manufacture method of silicon-on-insulator diode component, this method may further comprise the steps:
A) provide SOI substrate, this SOI substrate comprises basalis, be positioned at the oxygen buried layer on this basalis and be positioned at device layer on this oxygen buried layer;
B) the described device layer of etched portions forms groove, and in described groove, form first shallow trench isolation from;
C) described first shallow trench isolation from below device layer in form the first type zone, in the device layer of both sides, described first type zone, form the first type injection zone and the second type injection zone respectively, wherein, the implantation dosage of the described first type injection zone and the second type injection zone is greater than the implantation dosage in the described first type zone.
According to a further aspect in the invention, a kind of silicon-on-insulator diode component also is provided, the first type zone, the first type injection zone, the second type injection zone and first shallow trench isolation that this diode component comprises basalis, be positioned at oxygen buried layer on the described basalis, be positioned at device layer on the described oxygen buried layer and be positioned at described device layer from, wherein, described first shallow trench isolation in being embedded in described device layer, and described first shallow trench isolation from upper surface and the upper surface flush of described device layer; The described first type zone be positioned at described first shallow trench isolation under device layer; The described first type injection zone and the second type injection zone are positioned at described first area and first shallow trench isolation device layer from both sides, and the implantation dosage of the described first type injection zone and the second type injection zone is greater than the implantation dosage in the described first type zone.
Compared with prior art, the present invention has the following advantages:
1) silicon-on-insulator diode component proposed by the invention and preparation method thereof is compatible mutually with the main stream of CMOS technology, and compared with prior art, no matter is that structure or manufacture method are all simple relatively;
2) silicon-on-insulator diode component proposed by the invention has avoided occurring in the present gate control diode situation of parasitic capacitance, thereby has improved the operating rate of circuit effectively;
3) there is not the side direction PN junction in silicon-on-insulator diode component proposed by the invention, the diode component that girth is different for area is identical, and its I-E characteristic and capacitance-voltage characteristics are identical, thereby make circuit design more flexible;
4) there is first fleet plough groove isolation structure in silicon-on-insulator diode component proposed by the invention between the pn knot, can prevent effectively that the pn knot is touched a layer short circuit.
Description of drawings
By reading the detailed description of doing with reference to the following drawings that non-limiting example is done, it is more obvious that other features, objects and advantages of the present invention will become:
Fig. 1 is the structural profile schematic diagram of employed gate control diode in the present silicon-on-insulator CMOS technology;
Fig. 2 is the structural profile schematic diagram of employed SAB diode in the present silicon-on-insulator CMOS technology;
Fig. 3 is the flow chart according to silicon-on-insulator diode component manufacture method of the present invention;
Fig. 4 to Figure 20 is a generalized section of making each stage of semiconductor structure according to a preferred embodiment of the present invention according to flow process shown in Figure 3.
Same or analogous Reference numeral is represented same or analogous parts in the accompanying drawing.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition, first feature described below second feature it " on " structure can comprise that first and second features form the embodiment of direct contact, can comprise that also additional features is formed on the embodiment between first and second features, such first and second features may not be direct contacts.Should be noted that the not necessarily drafting in proportion of illustrated in the accompanying drawings parts.The present invention has omitted description to known assemblies and treatment technology and technology to avoid unnecessarily limiting the present invention.
According to an aspect of the present invention, provide a kind of manufacture method of silicon-on-insulator diode component, the step of this manufacture method as shown in Figure 3.Below, will be specifically described manufacture method shown in Figure 3 in conjunction with Fig. 4 to Figure 20, wherein, Fig. 4 to Figure 20 is a generalized section of making each stage of silicon-on-insulator diode component according to a preferred embodiment of the present invention according to flow process shown in Figure 3.
At first, in step S101, provide SOI substrate, this SOI substrate comprises basalis 302, be positioned at the oxygen buried layer 301 on this basalis 302 and be positioned at device layer 303 on this oxygen buried layer 301.
Particularly, please refer to Fig. 4, in the present embodiment, described basalis 302 is a monocrystalline silicon.In other embodiments, described basalis 302 can also comprise other basic semiconductor, for example germanium.Perhaps, described basalis 302 can also comprise compound semiconductor, for example, and carborundum, GaAs, indium arsenide or indium arsenide.Generally, the thickness of described basalis 302 is less than 1mm.
Described oxygen buried layer 301 can be silicon dioxide, silicon nitride or other any appropriate insulation materials, and typically, the thickness range of described oxygen buried layer 301 is 10nm-1um.
Any in the semiconductor that described device layer 303 can comprise for described basalis 302.In the present embodiment, described device layer 303 is a monocrystalline silicon.In other embodiments, described device layer 303 can also comprise other basic semiconductor or compound semiconductors.Typically, the thickness of described device layer 303 is greater than 20nm.
Described SOI substrate can adopt technology known in those skilled in the art such as for example annotating oxygen isolation or smart peeling to realize, no longer gives unnecessary details at this.
Then, execution in step S102, the described device layer 303 of etched portions forms groove 304, and forms first shallow trench isolation from 802 in described groove 304.
Particularly, with reference to figure 5 and Fig. 6, on described SOI substrate, form mask layer to cover the surface of described device layer 303.In the present embodiment, described mask layer is two mask layers, comprises being positioned at first mask layer 401 on the described device layer 303 and being positioned at second mask layer 501 on this first mask layer 401.Wherein, the material of described first mask layer 401 is preferably silicon dioxide, and its thickness range is 10nm-20nm, can form by the mode of for example heat growth; The material of described second mask layer 501 is preferably silicon nitride, and its thickness range is 100nm-200nm, can form by for example mode of deposition.Because silicon dioxide and silicon nitride have opposite stress,, can not exert an influence to device layer 303 so two mask layer structure can be offset the stress between its two just.In other embodiments, described mask layer also can be single layer structure, does not repeat them here.
With reference to figure 7, spin coating photoresist layer on described mask layer, and use active area version photoetching development, form photoresist 601 as mask.With described photoresist 601 is mask, by dry etching mask layer is carried out etching, until the upper surface that exposes described device layer 303, as shown in Figure 8; Then, continuing with photoresist 601 is mask, adopts dry etching that described device layer 303 is carried out etching, in described device layer 303, form groove 304, as shown in Figure 9, wherein, the depth bounds of described groove 304 is preferably the 1/2-1/3 of described device layer 303 thickness.Then, as shown in figure 10, remove described photoresist 601.
After removing described photoresist 601, in described groove 304, form first shallow trench isolation from 802 and around second shallow trench isolation of described device layer 303 from 803, the detailed process of its formation is as follows: as shown in figure 11, spin coating photoresist layer (not shown), use the part shallow trench isolation from (Partial Shallow Trench Isolation, PSTI) the version photoetching development forms the photoresist 701 as mask.After the development, described photoresist 701 covers the zone line of described device layer 303, exposes the zone that described device layer 303 is connected with adjacent diode component; Then, be mask, be etching stop layer with photoresist 701, by 303 area exposed of dry etching removal devices layer, as shown in figure 12 with oxygen buried layer 301; Then, as shown in figure 13, remove described photoresist 701, and deposition of insulative material is to cover described mask layer, described device layer 303 and oxygen buried layer 301 in described groove 304, as shown in figure 14, wherein, described insulating material includes but not limited to silicon dioxide; After the deposition, the described insulating material of CMP is until exposing described mask layer, as shown in figure 15; At last, continue the described mask layer of CMP until exposing described device layer 303, as shown in figure 16.At this moment, the insulating material that embeds in the described device layer 303 forms first shallow trench isolation from 802, the insulating material that is surrounded on described device layer 303 forms second shallow trench isolation from 803, be used for described device layer 303 isolated with adjacent diode component, wherein, described first shallow trench isolation from 802 and second shallow trench isolation from the upper surface flush of 803 upper surface and described device layer 303 (in this paper, term " flushes " difference in height that means between the two in the scope that fabrication error allows).
At last, execution in step S103, in the device layer 303 of described first shallow trench isolation below 802, form the first type zone 307, in the device layer 303 of 307 both sides, described first type zone, form the first type injection zone 305 and the second type injection zone 306 respectively, and the implantation dosage of the described first type injection zone 305 and the second type injection zone 306 is greater than the implantation dosage in the described first type zone 307, wherein, the doping that described first type and described second type are type opposite, promptly, if described first type is the n type, then second type is the p type; If described first type is the p type, then second type is the n type.
Particularly, continue with reference to Figure 16, the structure of the diode of Sheng Chenging is carried out the light dope ion to described device layer 303 and is injected (injection direction is shown in the figure arrow) as required, forms the first type zone in described device layer 303.Wherein, for the n+-p-p+ diode component, doped p type impurity, boron ion for example, the injection energy is 50kev-200kev, implantation dosage is 1e
12/ cm
2-1e
14/ cm
2For the p+-n-n+ diode component, Doped n-type impurity, arsenic ion for example, the injection energy is 50kev-200kev, implantation dosage is 1e
12/ cm
2-1e
14/ cm
2
Then, with reference to Figure 17, spin coating photoresist layer (not shown), use electrode 1 reticle to carry out photoetching development, form photoresist 901, expose the device layer 303 of described first shallow trench isolation, and be mask with this photoresist 901 from 802 1 sides, device layer 303 area exposed are carried out heavy doping ion inject (injection direction is shown in the figure arrow), form the first type injection zone.For the n+-p-p+ diode component, doped p type impurity, boron ion for example, the injection energy is 10kev-50kev, implantation dosage is 5e
14/ cm
2-3e
15/ cm
2For the p+-n-n+ diode component, Doped n-type impurity, arsenic ion for example, the injection energy is 10kev-50kev, implantation dosage is 5e
14/ cm
2-3e
15/ cm
2After the described first type injection zone forms, remove described photoresist 901.
Then, as shown in figure 18, spin coating photoresist layer (not shown), use electrode 2 reticle to carry out photoetching development, form photoresist 902 and cover the described first type injection zone, and be mask with described photoresist 902, the exposed region of device layer 303 is carried out the opposite heavy doping ion of impurity inject (injection direction is shown in the figure arrow).For the n+-p-p+ diode component, Doped n-type impurity, arsenic ion for example, the injection energy is 10kev-50kev, implantation dosage is 5e
14/ cm
2-3e
15/ cm
2For the p+-n-n+ diode component, doped p type impurity, boron ion for example, the injection energy is 10kev-50kev, implantation dosage is 5e
14/ cm
2-3e
15/ cm
2After the described second type injection zone forms, remove described photoresist 902.
Thus, as shown in figure 19, below 802, formed the first lower type zone 307 of implantation dosage at described first shallow trench isolation, and, in the device layer 303 of 802 both sides, first injection zone 305 that implantation dosage is higher and impurity is opposite and second injection zone 307 have been formed at described first type zone 307 and first shallow trench isolation.
Preferably, after forming described first injection zone 305 and second injection zone 306, upper surface at the described first type injection zone 305 and the second type injection zone 306 further forms contact layer 1000 (hereinafter representing with metal silicide layer), as shown in figure 20.Particularly, the depositing metal layers (not shown) covers described first injection zone 305, second injection zone 306, first shallow trench isolation from 802 and second trench isolations 803, wherein, the material of described metal level comprises a kind of or its combination in any in cobalt, titanium, the nickel.Then described diode component is carried out annealing operation, the upper surface of described metal level and the described first type injection zone 305 and the second type injection zone 306 is reacted, form metal silicide layer 1000, this metal silicide layer 1000 comprises a kind of or its combination in any in cobalt silicon, titanizing silicon, the nickel silicon, in order to reduce the contact resistance of the described first type injection zone 305 and the second type injection zone 306.Meanwhile, annealing operation can also activate the impurity in the described first type zone 307, the first type injection zone 305 and the second type injection zone 306.After annealing finishes, the residual metallic layer that selective removal does not react.
The manufacture method of silicon-on-insulator diode component provided by the present invention has the following advantages: 1) manufacture method is with the main stream of CMOS technology is compatible mutually at present; 2) compared with prior art,, so not only manufacture craft is simple relatively, can also avoid the appearance of parasitic capacitance, thereby improve the operating efficiency of circuit effectively owing to need not on the SOI substrate, to be formed on gate oxide and polysilicon layer; 3) can not form side direction pn knot, so, the diode component that girth is different for area is identical, its I-E characteristic and capacitance-voltage characteristics are identical, thereby make circuit design more flexible; 4) between the pn of described diode knot, formed first shallow trench isolation from, prevent that effectively the pn knot is touched layer short circuit and causes short circuit phenomenon.
According to another aspect of the present invention, a kind of silicon-on-insulator diode component also is provided, as shown in figure 19, this diode component comprises basalis 302, is positioned at oxygen buried layer 301 on the described basalis 302, is positioned on the described oxygen buried layer 301 device layer 303, the first type zone 307, the first type injection zone 305, the second type injection zone 306 and first shallow trench isolation from 802.Wherein, the material composition of described basalis 302, oxygen buried layer 301 and device layer 303 and thickness range can not repeat them here with reference to the corresponding contents in the silicon diode device making method on the aforementioned dielectric body.
Described first shallow trench isolation is from 802, be embedded in the described device layer 300, and described first shallow trench isolation is from the upper surface flush of 802 upper surface and described device layer 303 (in this paper, term " flushes " difference in height that means between the two in the scope that fabrication error allows).Described first shallow trench isolation comprises a kind of or its combination in any in silicon dioxide, the silicon nitride from 802 material, and its depth bounds is the 1/2-1/3 of described device layer 303 thickness.
The described first type zone 307, the first type injection zone 305 and the second type injection zone 306 are positioned at described device layer 300, and wherein, the described first type zone 307 is positioned at the device layer 303 of described first shallow trench isolation under 802; The described first type injection zone 305 and the second type injection zone 306 lay respectively at described first area 307 and first shallow trench isolation in the device layer 303 of 802 both sides, and the implantation dosage of the described first type injection zone 305 and the second type injection zone 306 is greater than the implantation dosage in the described first type zone 307.Wherein, the doping that described first type and described second type are type opposite, that is, if described first type is the n type, then second type is the p type; If described first type is the p type, then second type is the n type.
Particularly, for the n+-p-p+ diode component, described first type zone 307 is p type zone, and impurity is preferably the boron ion, and the implantation dosage scope is 1e
12/ cm
2-1e
14/ cm
2The described first type injection zone 305 is the p+ injection zone, and impurity is preferably the boron ion, and the implantation dosage scope is 5e
14/ cm
2-3e
15/ cm
2The described second type injection zone 306 is the n+ injection zone, and impurity is preferably arsenic ion, and the implantation dosage scope is 5e
14/ cm
2-3e
15/ cm
2For the p+-n-n+ diode component, described first type zone 307 is n type zone, and impurity is preferably arsenic ion, and the implantation dosage scope is 1e
12/ cm
2-1e
14/ cm
2The described first type injection zone 305 is the n+ injection zone, and impurity is preferably arsenic ion, and the implantation dosage scope is 5e
14/ cm
2-3e
15/ cm
2The described second type injection zone 306 is the p+ injection zone, and impurity is preferably the boron ion, and the implantation dosage scope is 5e
14/ cm
2-3e
15/ cm
2
Silicon-on-insulator diode component provided by the present invention comprises that also second shallow trench isolation around described device layer 303 is from 803, that is, that first area 307, first injection zone 305 and second injection zone 307 of described diode component is isolated with adjacent diode component.Wherein, described second shallow trench isolation is preferably identical from 802 material with described first shallow trench isolation from 803 material, also can be different.
Preferably, also further there is contact layer 1000 at described first type injection zone 305 and the second type injection zone, 306 upper surfaces, as shown in figure 20, this contact layer 1000 can be metal silicide layer, comprise a kind of or its combination in any in cobalt silicon, titanizing silicon, the nickel silicon, in order to reduce the contact resistance of the described first type injection zone 305 and the second type injection zone 306.
With compare in the prior art, silicon-on-insulator diode component provided by the present invention has the following advantages: 1) need not additionally to form gate oxide and polysilicon layer, and therefore, not only simple in structure, can also avoid the appearance of parasitic capacitance, thereby improve the operating efficiency of circuit effectively; 2) there is not side direction pn knot, the diode component that girth is different for area is identical, its I-E characteristic and capacitance-voltage characteristics are identical, thereby make circuit design more flexible; 3) between diode pn knot, introduced first shallow trench isolation from, thereby can prevent effectively that the pn knot is touched layer short circuit and causes short circuit phenomenon.
Though describe in detail about example embodiment and advantage thereof, be to be understood that under the situation of the protection range that does not break away from the qualification of spirit of the present invention and claims, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present, wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.Therefore, claims of the present invention are intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (15)
1. the manufacture method of a silicon-on-insulator diode component, this method may further comprise the steps:
A) provide SOI substrate, this SOI substrate comprises basalis (302), be positioned at the oxygen buried layer (301) on this basalis (302) and be positioned at device layer (303) on this oxygen buried layer (301);
B) the described device layer of etched portions (303) forms groove (304), and forms first shallow trench isolation from (802) in described groove (304);
C) in the device layer (303) of (802) below, form the first type zone (307) at described first shallow trench isolation, in the device layer (303) of both sides, the described first type zone (307), form the first type injection zone (305) and the second type injection zone (306) respectively, wherein, the implantation dosage of the described first type injection zone (305) and the second type injection zone (306) is greater than the implantation dosage in the described first type zone (307).
2. manufacture method according to claim 1, wherein:
Described first type is the n type, and second type is the p type; Perhaps
Described first type is the p type, and second type is the n type.
3. manufacture method according to claim 1 and 2, wherein, described step b) comprises:
Go up formation mask layer, graphically this mask layer at described device layer (303);
With described mask layer is mask, adopts dry etching that described device layer (303) is carried out etching to form groove (304), and wherein, the depth bounds of this groove (304) is the 1/2-1/3 of described device layer (303) thickness;
Deposition of insulative material in described groove (304) forms first shallow trench isolation from (802).
4. manufacture method according to claim 1 and 2, wherein, described step c) comprises:
The device layer (303) of described first shallow trench isolation from (802) below carried out light dope, form the first type zone (307); And
The described first type zone (307) and first shallow trench isolation are carried out the heavy doping of impurity type opposite respectively from the device layer (303) of (802) both sides, form the first type injection zone (305) and the second type injection zone (306).
5. manufacture method according to claim 4, wherein, described lightly doped injection energy range is 50kev-200kev, the implantation dosage scope is 1e
12/ cm
2-1e
14/ cm
2
6. manufacture method according to claim 4, wherein, described heavily doped injection energy range is 10kev-50kev, the implantation dosage scope is 5e
14/ cm
2-3e
15/ cm
2
7. manufacture method according to claim 1 also comprises:
Formation around described device layer (303) second shallow trench isolations from (803).
8. manufacture method according to claim 1 wherein, also comprises after described step c):
D) upper surface at the described first type injection zone (305) and the second type injection zone (306) forms contact layer (1000).
9. silicon-on-insulator diode component, this diode component comprises basalis (302), be positioned at oxygen buried layer (301) on the described basalis (302), be positioned at device layer (303) on the described oxygen buried layer (301) and be positioned at described device layer (303) the first type zone (307), the first type injection zone (305) and the second type injection zone (306), it is characterized in that
Exist first shallow trench isolation from (802), be embedded in the described device layer (300), and described first shallow trench isolation is from the upper surface flush of the upper surface and the described device layer (303) of (802);
The described first type zone (307) is positioned at the device layer (303) of described first shallow trench isolation under (802); And
The described first type injection zone (305) and the second type injection zone (306) are positioned at described first area (307) and first shallow trench isolation device layer (303) from (802) both sides, and the implantation dosage of the described first type injection zone (305) and the second type injection zone (306) is greater than the implantation dosage in the described first type zone (307).
10. diode component according to claim 9 also comprises:
Around second shallow trench isolation of described device layer (303) from (803).
11. diode component according to claim 9 also comprises:
Be positioned at the contact layer (1000) of the described first type injection zone (305) and second type injection zone (306) upper surface.
12. according to each described diode component in the claim 9 to 11, wherein:
Described first type is the n type, and second type is the p type; Perhaps
Described first type is the p type, and second type is the n type.
13. according to each described diode component in the claim 9 to 11, wherein:
The depth bounds of described first shallow trench isolation from (802) is the 1/2-1/3 of described device layer (303) thickness.
14. according to each described diode component in the claim 9 to 11, wherein:
The implantation dosage scope in the described first type zone (307) is 1e
12/ cm
2-1e
14/ cm
2
15. according to each described diode component in the claim 9 to 11, wherein:
The implantation dosage scope of the described first type injection zone (305) and the second type injection zone (306) is 5e
14/ cm
2-3e
15/ cm
2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110183539.1A CN102244030B (en) | 2011-06-30 | 2011-06-30 | Silicon on insulator diode device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110183539.1A CN102244030B (en) | 2011-06-30 | 2011-06-30 | Silicon on insulator diode device and manufacturing method thereof |
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| CN102244030B CN102244030B (en) | 2014-10-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187301A (en) * | 2011-12-16 | 2013-07-03 | 茂达电子股份有限公司 | Trench type power transistor component with super interface and manufacturing method thereof |
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|---|---|---|---|---|
| US4800415A (en) * | 1984-09-21 | 1989-01-24 | American Telephone And Telegraph Company, At&T Bell Laboratories | Bipolar inversion channel device |
| US5717241A (en) * | 1993-12-09 | 1998-02-10 | Northern Telecom Limited | Gate controlled lateral bipolar junction transistor |
| US6465830B2 (en) * | 2000-06-13 | 2002-10-15 | Texas Instruments Incorporated | RF voltage controlled capacitor on thick-film SOI |
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2011
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4800415A (en) * | 1984-09-21 | 1989-01-24 | American Telephone And Telegraph Company, At&T Bell Laboratories | Bipolar inversion channel device |
| US5717241A (en) * | 1993-12-09 | 1998-02-10 | Northern Telecom Limited | Gate controlled lateral bipolar junction transistor |
| US6465830B2 (en) * | 2000-06-13 | 2002-10-15 | Texas Instruments Incorporated | RF voltage controlled capacitor on thick-film SOI |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187301A (en) * | 2011-12-16 | 2013-07-03 | 茂达电子股份有限公司 | Trench type power transistor component with super interface and manufacturing method thereof |
| CN103187301B (en) * | 2011-12-16 | 2016-01-20 | 茂达电子股份有限公司 | Trench type power transistor component with super interface and manufacturing method thereof |
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| CN102244030B (en) | 2014-10-15 |
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