CN102226989A - Method for manufacturing mixed crystal-oriented silicon substrate - Google Patents
Method for manufacturing mixed crystal-oriented silicon substrate Download PDFInfo
- Publication number
- CN102226989A CN102226989A CN2011101618898A CN201110161889A CN102226989A CN 102226989 A CN102226989 A CN 102226989A CN 2011101618898 A CN2011101618898 A CN 2011101618898A CN 201110161889 A CN201110161889 A CN 201110161889A CN 102226989 A CN102226989 A CN 102226989A
- Authority
- CN
- China
- Prior art keywords
- crystal orientation
- silicon chip
- orientation silicon
- thickness
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
The invention relates to a method for manufacturing a mixed crystal-oriented silicon substrate. In the method, conventional silicon wafer bonding, photoetching, corrosion, conventional epitaxy, chemically mechanical polishing and reduction technologies are adopted to manufacture the mixed crystal-oriented silicon substrate. A mask plate is used only, SiO2 is not deposited to be taken as a screening layer and SPACER oxidation and groove isolation are not required. The method is simple in technology, stable and controllable in growth speed of an epitaxial layer, flat in material surface and fewer in defects; the method is high in piezoresistive coefficient character and sensitive to pressure; and the method is applied to the manufacturing field of 15-40V high-voltage analogue integrated circuits and MEMS (micro electro mechanical system) devices.
Description
Technical field
The present invention relates to a kind of manufacture method of crystallographic orientation silicon substrate, it is applicable to the manufacturing field of high speed analog integrated circuit and MEMS device.
Background technology
Conventional CMOS technology all is produced on usually＜100〉crystal face silicon substrate on because＜100〉crystal orientation Si/SiO
2Interface charge density is lower, the mobility of electronics is the highest, but the mobility of hole on this crystal orientation has only 1/2 to 1/3 of electron mobility, better choice is the orientation that changes substrate crystal face itself---adopt＜110〉crystal orientation, therefore be performances such as raising cmos circuit driving force, NMOS pipe and PMOS pipe are integrated on the zone of different crystal orientations of same silicon substrate, have just produced the crystallographic orientation technology.
The silicon substrate technology of crystallographic orientation, be called for short the HOT technology, the existing report from 1998, patent documentation 1 (people such as MasaakiAoki, No. 4768076, United States Patent (USP), Recrystallized CMOS with different crystal planes) in, the CMOS phase inverter of crystallographic orientation has been proposed.It adopts N type＜110〉crystal orientation silicon chips to prepare PMOS pipe, deposit SiO on the PMOS pipe then
2, Si
3N
4, young crystal layer and polysilicon, adopt the polysilicon laser annealing to form＜100〉crystal orientation silicon chip, with NMOS is tubular is formed in＜100〉crystal face on.But this process using laminated construction, manufacture difficulty is very big, crystallization process is restive, and the thermal process in the subsequent technique is bigger than normal to the performance impact of PMOS device.
Patent documentation 2 (people such as Song Junyong, Chinese patent CN 184831A number, semiconductor device and the method for making semiconductor device) in, proposed to have the semi-conducting material in two kinds of crystal orientation, its the first transistor forms in the semi-conducting material with first crystal orientation, and transistor seconds forms in the semiconductor layer with second crystal orientation.But need be in the method at the second crystal orientation silicon face extraneous growth SiO
2Masking layer, the basis of property extension alternatively, and to do the spacer oxidation, adopted twice chemico-mechanical polishing (CMP), its process equipment costliness, cost height, complex technical process, and selective epitaxial institute growth material blemish is many, and growth rate is several nm/min slowly.It is mainly used in the integrated circuit of submicron order, and the operating voltage of its circuit is low, has only several volts.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of crystallographic orientation silicon substrate is used for the purpose that high pressure simulation integrated circuit and MEMS device are made to reach, and technology is simple, low cost of manufacture.
The manufacture method of a kind of crystallographic orientation silicon substrate of the present invention may further comprise the steps:
(1) growth first oxide layer on the first crystal orientation silicon chip;
(2) will have the first crystal orientation silicon chip and the second crystal orientation wafer bonding of described first oxide layer, form the SOI sheet.
(3) described SOI sheet is carried out attenuate, the chemico-mechanical polishing of common process, satisfy device to the thickness of the straight second crystal orientation silicon chip and make requiredly, form described crystallographic orientation silicon substrate.
Described step of growing first oxide layer on the first crystal orientation silicon chip comprises: the conventional cleaning; Conventional oxidation, oxidated layer thickness is 100-500nm.
The first crystal orientation silicon chip and the second crystal orientation wafer bonding that will have described oxide layer, the step that forms the SOI sheet comprises: the conventional cleaning; Conventional silicon-silicon bond closes.
Described SOI sheet is carried out attenuate, the chemico-mechanical polishing of common process, and it is required that extremely the thickness of the straight second crystal orientation silicon chip satisfies the device manufacturing, and the step that forms described crystallographic orientation silicon substrate comprises:
1) adopts conventional attenuate, CMP (Chemical Mechanical Polishing) process, the second crystal orientation silicon chip is carried out attenuate, chemico-mechanical polishing, obtain the SOI sheet that the second crystal orientation silicon wafer thickness is the crystallographic orientation of 3～5 μ m;
2) described SOI sheet is applied photic masking layer, carry out conventional photoetching, exposure, development, produce required graphics field;
3) after wet etching removes the natural oxidizing layer on surface,, adopt dry etching, corrode the silicon layer in second crystal orientation, corrode till centre first oxide layer of SOI sheet in required graphics field;
4) first oxide layer and photic masking layer are removed in the required graphics field of wet etching;
5) adopt conventional epitaxy technique, grown epitaxial layer, its thickness is more than or equal to the thickness and the first thickness of oxide layer sum of the second crystal orientation silicon chip;
6) epitaxial loayer is carried out conventional attenuate, chemico-mechanical polishing after, the second crystal orientation silicon chip and and the second crystal orientation silicon chip on the thickness sum of epitaxial loayer greater than 5 μ m, final, form described crystallographic orientation silicon substrate.
Beneficial effect:
The manufacture method of crystallographic orientation silicon substrate of the present invention only needs to adopt conventional silicon silicon wafer bonding, photoetching, the conventional extension of burn into, chemico-mechanical polishing and reduction process, just can make the silicon substrate of crystallographic orientation.Compare with the silicon substrate manufacture method of routine, it has following characteristics:
1) adopts conventional silicon-silicon wafer bonding technology, just can form the SOI sheet of different crystal orientations; Need not deposit SiO
2As masking layer, need not to do the SPACER oxidation; Only need to use a mask, and do not need to do the groove isolation,, then only need a CMP (Chemical Mechanical Polishing) process, so the operation of the inventive method is simple, low cost of manufacture if select ready-made SOI sheet.
2) by conventional CMP (Chemical Mechanical Polishing) process, the epitaxial loayer in the second unnecessary crystal orientation of skimming, so the silicon substrate of the crystallographic orientation that forms of the inventive method has more smooth plane, and have the different crystal orientations zone on the plane.
3) by conventional epitaxy technique, make epitaxial loayer have consistent crystal orientation with the silicon substrate of depositing region, its thickness can be according to the needs of concrete device, control by the epitaxial growth time, characteristics with fast growth, and compare with the selective epitaxial mode, epi-layer surface defective of the present invention still less.Therefore, the silicon substrate of the crystallographic orientation of the inventive method is applicable to the high pressure simulation integrated circuit of 15～40V.
4) have high piezoresistance coefficient characteristic owing to＜110〉crystal plane material, to presser sensor, so the silicon substrate of the crystallographic orientation of the inventive method is applicable to the manufacturing of MEMS device.
Description of drawings
Fig. 1 is the generalized section of the first crystal orientation silicon chip of band oxide layer of the present invention;
Fig. 2 for Fig. 1 of the present invention＜100〉type first crystal orientation silicon chips and second crystal orientation silicon chip＜110 generalized section of formation behind the described SOI sheet;
Fig. 3 is the SOI sheet attenuate of Fig. 2 of the present invention, the generalized section after the chemico-mechanical polishing;
Fig. 4 is the generalized section after SOI sheet photoetching/exposure/development of Fig. 3 of the present invention;
Fig. 5 is the generalized section behind the SOI sheet dry etching silicon of Fig. 4 of the present invention;
Fig. 6 is the generalized section after the SOI sheet wet etching oxide layer of Fig. 5 of the present invention;
Fig. 7 is the generalized section behind the SOI sheet grown epitaxial layer of Fig. 6 of the present invention;
Fig. 8 is the generalized section after the SOI sheet of Fig. 7 of the present invention forms described crystallographic orientation silicon substrate.
Embodiment
The specific embodiment of the present invention is not limited only to following description.In conjunction with the accompanying drawings the present invention is further specified.
With Semiconducting Silicon Materials sheet crystal orientation, first crystal orientation is＜100〉crystal orientation, and Semiconducting Silicon Materials sheet crystal orientation, second crystal orientation is an example for＜110〉crystal orientation.
On the first crystal orientation silicon chip 2 growth first oxide layer 1:
With the first crystal orientation silicon chip, 2 usefulness 1# liquid (NH
4OH: H
2O
2: H
2O=1: 2: 7) and 2# liquid (HCl: H
2O
2: H
2O=1: 2: 7), each cleans 10min, cleans hereinafter to be referred as RCA; Carry out conventional oxidation on the first crystal orientation silicon chip 2, oxidated layer thickness is 100-500nm, forms the first crystal orientation semi-conducting material silicon chip 2 of band oxide layer 1, as shown in Figure 1;
2. the first crystal orientation silicon chip 2 and the second crystal orientation silicon chip, 3 bondings that will have described first oxide layer 1 form the SOI sheet:
1) the first crystal orientation silicon chip 2 and the second crystal orientation silicon chip 3 are respectively carried out RCA cleaning, time 10min;
2) with the first crystal orientation silicon chip 2 and the inoxidized second crystal orientation silicon chip 3, in the CL200 bonding machine as KARLSUSS company, technology is carried out normal temperature silicon/silicon bonding routinely, forms the SOI sheet, obtains structure as shown in Figure 2;
3. described SOI sheet is carried out attenuate, the chemico-mechanical polishing of common process, it is required to satisfy the device manufacturing to the straight second crystal orientation silicon chip, 3 thickness, forms described crystallographic orientation silicon substrate:
1) adopts the VG200MKH attenuate machine of stripping apparatus such as EVG company,, carry out attenuate the second crystal orientation silicon chip 3 reduction process routinely; Adopt the AVANTI472 chemical-mechanical polishing mathing of the chemical-mechanical polisher such as the U.S., technology is carried out chemico-mechanical polishing routinely, and obtaining the second crystal orientation silicon chip, 3 thickness is the SOI sheet of the crystallographic orientation of 3～5 μ m, as shown in Figure 3.
2) described SOI sheet is applied photic masking layer 7, carry out conventional photoetching, exposure, development, expose the part second crystal orientation silicon chip, promptly produce required graphics field 4, form structure as shown in Figure 4;
3) after wet etching removes the natural oxidizing layer on surface,, adopt dry etching, corrode the silicon layer 3 in second crystal orientation, corrode till centre first oxide layer 1 of SOI sheet, as shown in Figure 5 in required graphics field 4;
4) wet etching in required graphics field 4, removes first oxide layer 1 and photic masking layer 7, as shown in Figure 6;
5) adopt conventional epitaxy technique, grown epitaxial layer 5, its thickness is more than or equal to the thickness of the second crystal orientation silicon chip 3 and the thickness sum of first oxide layer 1, as shown in Figure 7;
6) to after the described silicon chip employing of Fig. 7 attenuate, the CMP (Chemical Mechanical Polishing) process, behind the attenuate, the thickness sum of the epitaxial loayer 6 on the second crystal orientation silicon chip 3 and the second crystal orientation silicon chip is greater than 5 μ m, and is final, forms described crystallographic orientation silicon substrate, as shown in Figure 8.
Used individual event technology in the inventive method, except that done detailed description, other, be this area current techique as individual event technology, equipment and chemical materials, the reagent of the conventional extension of cleaning, oxidation, photoetching, burn into, attenuate, chemico-mechanical polishing etc., no longer describe in detail.
Claims (4)
1. the manufacture method of a crystallographic orientation silicon substrate is characterized in that may further comprise the steps:
(1) growth first oxide layer on the first crystal orientation silicon chip;
(2) will have the first crystal orientation silicon chip and the second crystal orientation wafer bonding of described first oxide layer, form the SOI sheet.
(3) described SOI sheet is carried out attenuate, the chemico-mechanical polishing of common process, satisfy device to the thickness of the straight second crystal orientation silicon chip and make requiredly, form described crystallographic orientation silicon substrate.
2. a kind of silicon hybrid crystal orientation substrate manufacture method according to claim 1 is characterized in that: described step of growing first oxide layer on the first crystal orientation silicon chip comprises: the conventional cleaning; Conventional oxidation, oxidated layer thickness is 100-500nm.
3. a kind of silicon hybrid crystal orientation substrate manufacture method according to claim 1 is characterized in that: will have the first crystal orientation silicon chip and the second crystal orientation wafer bonding of described oxide layer, the step that forms the SOI sheet comprises: the conventional cleaning; Conventional silicon-silicon bond closes.
4. a kind of silicon hybrid crystal orientation substrate manufacture method according to claim 1, it is characterized in that: described SOI sheet is carried out attenuate, the chemico-mechanical polishing of common process, it is required that extremely the thickness of the straight second crystal orientation silicon chip satisfies the device manufacturing, and the step that forms described crystallographic orientation silicon substrate comprises:
1) adopts conventional attenuate, CMP (Chemical Mechanical Polishing) process, the second crystal orientation silicon chip is carried out attenuate, chemico-mechanical polishing, obtain the SOI sheet that the second crystal orientation silicon wafer thickness is the crystallographic orientation of 3～5 μ m;
2) described SOI sheet is applied photic masking layer, carry out conventional photoetching, exposure, development, produce required graphics field;
3) after wet etching removes the natural oxidizing layer on surface,, adopt dry etching, corrode the silicon layer in second crystal orientation, corrode till centre first oxide layer of SOI sheet in required graphics field;
4) wet etching, first oxide layer and photic masking layer are removed in required graphics field;
5) adopt conventional epitaxy technique, grown epitaxial layer, its thickness is more than or equal to the thickness and the first thickness of oxide layer sum of the second crystal orientation silicon chip;
6) epitaxial loayer is carried out conventional attenuate, chemico-mechanical polishing after, the thickness sum of the epitaxial loayer on the second crystal orientation silicon chip and the second crystal orientation silicon chip is greater than 5 μ m, and is final, forms described crystallographic orientation silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101618898A CN102226989A (en) | 2011-06-16 | 2011-06-16 | Method for manufacturing mixed crystal-oriented silicon substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101618898A CN102226989A (en) | 2011-06-16 | 2011-06-16 | Method for manufacturing mixed crystal-oriented silicon substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102226989A true CN102226989A (en) | 2011-10-26 |
Family
ID=44807951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101618898A Pending CN102226989A (en) | 2011-06-16 | 2011-06-16 | Method for manufacturing mixed crystal-oriented silicon substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102226989A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022263A (en) * | 2013-01-06 | 2013-04-03 | 向勇 | Thin silicon technology |
| CN111137846A (en) * | 2019-12-24 | 2020-05-12 | 中国电子科技集团公司第十三研究所 | Preparation method of micron-level step height standard sample block |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1836323A (en) * | 2003-06-17 | 2006-09-20 | 国际商业机器公司 | High-performance CMOS SOI device on hybrid crystal-oriented substrates |
-
2011
- 2011-06-16 CN CN2011101618898A patent/CN102226989A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1836323A (en) * | 2003-06-17 | 2006-09-20 | 国际商业机器公司 | High-performance CMOS SOI device on hybrid crystal-oriented substrates |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022263A (en) * | 2013-01-06 | 2013-04-03 | 向勇 | Thin silicon technology |
| CN111137846A (en) * | 2019-12-24 | 2020-05-12 | 中国电子科技集团公司第十三研究所 | Preparation method of micron-level step height standard sample block |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7015147B2 (en) | Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si1-xGex layer | |
| JP3033412B2 (en) | Method for manufacturing semiconductor device | |
| US20080233708A1 (en) | Method for manufacturing semiconductor device | |
| WO2002103760A2 (en) | Method of selective removal of sige alloys | |
| JP2005531144A5 (en) | ||
| JP2000031440A (en) | Manufacture of soi wafer | |
| US7846811B2 (en) | Process for manufacturing a high-quality SOI wafer | |
| CN101523719B (en) | Resonator and its manufacture method | |
| WO2012155830A1 (en) | Germanium and ⅲ-ⅴ mixed coplanar silicon on insulator (soi) semiconductor structure and manufacturing method thereof | |
| WO2012155831A1 (en) | Heterojunction semiconductor structure with germanium and iii-v integrated coplanar and manufacturing method thereof | |
| US11127625B2 (en) | Semiconductor structure and related method | |
| JP2007142401A (en) | Substrate and method (hybrid crystal substrate with surface orientations having one or a plurality of soi regions or bulk semiconductor regions or having both of them) | |
| CN1819215B (en) | Element formation substrate, method of manufacturing the same, and semiconductor device | |
| CN102226989A (en) | Method for manufacturing mixed crystal-oriented silicon substrate | |
| CN100377352C (en) | Semiconductor device and manufacturing method thereof | |
| US20050112843A1 (en) | Method for anodic bonding of wafers and device | |
| CN110752218A (en) | Multilayer SOI and preparation method thereof | |
| WO2004095522A3 (en) | Deep n wells in triple well structures and method for fabricating same | |
| KR20090105910A (en) | Process for forming and controlling rough interfaces | |
| JPH02237121A (en) | Manufacture of semiconductor device | |
| JPH02219252A (en) | Manufacture of semiconductor device | |
| US9082716B2 (en) | Method of manufacturing semiconductor device | |
| CN103137537A (en) | Si/CoSi2 substrate material on imaging fully-depleted insulation body and preparing method thereof | |
| JP2770808B2 (en) | Semiconductor substrate and method of manufacturing the same | |
| CN103137538A (en) | Si/NiSi2 substrate material on imaging insulation body and preparing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20111026 |