CN102214702B - Semiconductor capacitor structure and forming method thereof - Google Patents
Semiconductor capacitor structure and forming method thereof Download PDFInfo
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Abstract
A kind of semiconductor capacitor structure, comprising: Semiconductor substrate; Be positioned at the first polysilicon layer of institute's semiconductor substrate surface; Also comprise: be positioned at the first polysilicon layer surface, and cover the first medium layer of the sidewall of the first polysilicon layer; Be positioned at described first medium layer surface, and cover the second polysilicon layer of the sidewall of first medium layer; Run through the second polysilicon layer, first medium layer, and expose the through hole of the first polysilicon layer.Correspondingly, the present invention also provides the formation method of described semiconductor capacitor structure.Semiconductor capacitor structure provided by the present invention and forming method thereof avoids formation polysilicon stringers, thus simplifies technological process.
Description
Technical field
The present invention relates to semiconductor applications, particularly semiconductor capacitor structure and forming method thereof.
Background technology
In existing CMOS technology, polycrystalline silicon-on-insulator-polysilicon (PIP, Poly-Insulator-Poly) capacitor and polysilicon-polysilicon silicon-substrate (PPS, Poly-Poly-Substrate) capacitor are widely used as capacitor element use.
Fig. 1 is the structural representation of existing PIP capacitor device, comprises Semiconductor substrate 100, and described Semiconductor substrate 100 surface is formed with fleet plough groove isolation structure 110; Be positioned at the first medium layer 120 on described fleet plough groove isolation structure 110 surface; Be positioned at first polysilicon layer 130 on described first medium layer 120 surface; Be positioned at the second dielectric layer 140 on described first polysilicon layer 130 surface, and second dielectric layer 140 covers the sidewall of the side of the first polysilicon layer 130; Be positioned at second polysilicon layer 150 on described second dielectric layer 140 and first medium layer 120 surface, and described second polysilicon layer 150 covers the sidewall that second dielectric layer 140 is positioned at first medium layer 120 surface, first polysilicon layer 130 part surface of one end relative with capped first polysilicon layer 130 sidewall is exposed, and the surface of described exposure is formed with the first conductive plunger 170 be electrically connected with the first polysilicon layer 130, described second polysilicon layer 150 surface also has the second conductive plunger 180 be electrically connected with the second polysilicon layer 150.
Fig. 2 is the structural representation of existing PPS capacitor, comprises Semiconductor substrate 200, and described Semiconductor substrate 200 surface is formed with dopant well 290, and is positioned at the fleet plough groove isolation structure 210 of described dopant well 290 both sides; Be positioned at the first medium layer 220 on described dopant well 290 surface; Be positioned at first polysilicon layer 230 on described first medium layer 220 surface; Be positioned at the second dielectric layer 240 on described first polysilicon layer 230 surface, described second dielectric layer 240 covers a sidewall of the first polysilicon layer 230; Be positioned at second polysilicon layer 250 on described second dielectric layer 240 and first medium layer 220 surface, and described second polysilicon layer 250 covers the sidewall that second dielectric layer 240 is positioned at first medium layer 220 surface, first polysilicon layer 230 part surface of one end relative with capped first polysilicon layer 230 sidewall is exposed, and the surface of described exposure is formed with the first conductive plunger 270 be electrically connected with the first polysilicon layer 230, described second polysilicon layer 250 surface also has the second conductive plunger 280 be electrically connected with the second polysilicon layer 250.It is the formation method disclosing above-mentioned PPS capacitor in the Chinese patent of CN101937878A at publication number.
In the technique forming existing PIP capacitor device, polysilicon stringers (polystringer) 190 shown in easy formation Fig. 1, in the technique forming existing PPS capacitor, polysilicon stringers (polystringer) 295 shown in easy formation Fig. 2, so need extra light shield and the strict etching technics that controls to remove the polysilicon stringers 190 shown in Fig. 1, the polysilicon stringers 295 shown in Fig. 2.
Summary of the invention
The problem that embodiments of the invention solve is to provide a kind of semiconductor capacitor structure and forming method thereof, to avoid at PIP or/and form polysilicon stringers in PPS capacitor arrangement, thus Simplified flowsheet.For solving the problem, embodiments of the invention provide a kind of semiconductor capacitor structure, comprising:
Semiconductor substrate;
Be positioned at the first polysilicon layer of described semiconductor substrate surface;
Be positioned at described first polysilicon layer surface, and cover the first medium layer of the sidewall of the first polysilicon layer;
Be positioned at described first medium layer surface, and cover the second polysilicon layer of the sidewall of first medium layer;
Run through described second polysilicon layer, first medium layer, and expose the through hole of the first polysilicon layer.
Alternatively, described Semiconductor substrate also comprises dopant well, adjacent dopant well is separated by isolation structure, and be positioned at the second dielectric layer on described dopant well surface, described first polysilicon layer is positioned at described second dielectric layer surface, and described second polysilicon layer, the first polysilicon layer, dopant well form PPS capacitor arrangement.
Alternatively, described Semiconductor substrate also comprises isolation structure, and described first polysilicon layer is positioned at described isolation structure surface, and described first polysilicon layer, first medium layer, the first polysilicon layer form PIP capacitor device structure.
Alternatively, also comprise: the first conductive plunger be electrically connected with the first polysilicon layer, and run through described through hole, and the second conductive plunger be electrically connected with the second polysilicon layer.
Correspondingly, the present invention also provides the formation method of above-mentioned semiconductor capacitor structure, comprising:
Semiconductor substrate is provided;
The first polysilicon layer is formed at described semiconductor substrate surface;
Form first medium layer on described first polysilicon layer surface, described first medium layer covers the sidewall of the first polysilicon layer;
Form polysilicon membrane on described first medium layer surface and semiconductor substrate surface, and etch described polysilicon membrane, form the second polysilicon layer covering first medium layer, described second polysilicon layer has the through hole of exposure first polysilicon layer.
Alternatively, also comprise: in described Semiconductor substrate, form dopant well, adjacent dopant well is separated by isolation structure, second dielectric layer is formed on described dopant well surface, described first polysilicon layer is formed at described second dielectric layer surface, and described first polysilicon layer, the second polysilicon layer, dopant well form PPS capacitor arrangement.
Alternatively, also comprise: in described Semiconductor substrate, form isolation structure, form the first polysilicon layer on described isolation structure surface, described first polysilicon layer, first medium layer, the second polysilicon layer form PIP capacitor device structure.
Alternatively, also comprise: form on the first polysilicon layer surface the first conductive plunger be electrically connected with the first polysilicon layer, formed and run through described through hole, and the second conductive plunger be electrically connected with the second polysilicon layer.
Compared with prior art, embodiments of the invention have the following advantages: in the formation method of the semiconductor capacitor structure provided at embodiments of the invention, form the first polysilicon layer successively at semiconductor substrate surface; Be positioned at the first medium layer on described first polysilicon layer surface; Be positioned at second polysilicon layer on described first medium layer surface; Wherein, first medium layer covers surface and the sidewall of the first polysilicon layer; Second polysilicon layer covers surface and the sidewall of first medium layer, thus in the step of formation second polysilicon layer, the part corresponding with the first polysilicon layer position for the formation of the polysilicon membrane of the second polysilicon layer is remained completely, and the second polysilicon layer completely covers the sorrowful wall of the first polysilicon layer, thus avoid when etching polysilicon membrane and forming the second polysilicon layer, form polysilicon stringers in the first polysilicon layer both sides; Meanwhile, the through hole exposing the first polysilicon layer may be used in subsequent technique, form the conductive plugs be electrically connected with the first polysilicon layer;
Further, in optional embodiment of the present invention, described Semiconductor substrate also comprises dopant well, and the isolation structure between adjacent dopant well, be positioned at the second dielectric layer on dopant well surface, first polysilicon layer is formed at the surface of described second dielectric layer, thus defines the PPS capacitor arrangement be made up of Semiconductor substrate, the first polysilicon layer, the second polysilicon layer;
Further, in optional embodiment of the present invention, described Semiconductor substrate also comprises isolation structure, and described second dielectric layer is positioned at described isolation structure surface, thus defines the PIP capacitor device structure be made up of the first polysilicon layer, first medium layer, the second polysilicon layer.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing PIP capacitor device;
Fig. 2 is the structural representation of existing PPS capacitor;
Fig. 3 is the schematic diagram of the semiconductor capacitor structure that first embodiment of the invention provides;
Fig. 4 is the schematic flow sheet of the formation method of the semiconductor capacitor structure that first embodiment of the invention provides;
Fig. 5 to Fig. 9 is the generalized section of the formation method of the semiconductor capacitor structure that first embodiment of the invention provides;
Figure 10 is the schematic diagram of the semiconductor capacitor structure that this second embodiment provides.
Embodiment
From background technology, existing semiconductor capacitor structure and forming method thereof can form polysilicon stringers in the first polysilicon layer side, in order to remove formed polysilicon stringers, need extra light shield and carry out the etching technics that is tightly controlled, inventor studies for the problems referred to above, find in existing PIP or PPS capacitor, because one end of the second polysilicon layer part corresponding with the first polysilicon layer position needs to be removed, to form the conductive plunger be electrically connected with the first polysilicon layer in subsequent technique, in the technique of part corresponding with the first polysilicon layer position described in removal second polysilicon layer, second polysilicon layer and a first polysilicon layer sidewall neighbour's part can be retained, form described polysilicon stringers.Inventor after further research, proposes a kind of semiconductor capacitor structure and forming method thereof in the present invention.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public embodiment.
First embodiment
The schematic diagram of the semiconductor capacitor structure that Fig. 3 first embodiment of the present invention provides, comprising:
Semiconductor substrate 300;
Be positioned at first polysilicon layer 330 on described Semiconductor substrate 300 surface; Also comprise:
Be positioned at the first polysilicon layer 330 surface, and cover the first medium layer 340 of the sidewall of the first polysilicon layer 330;
Be positioned at described first medium layer 340 surface, and cover the second polysilicon layer 350 of the sidewall of first medium layer 340;
Run through the second polysilicon layer 350, first medium layer 340, and expose the through hole 360 of the first polysilicon layer 330.
In first embodiment of the present invention, described Semiconductor substrate 300 also comprises isolation structure 310, and described first polysilicon layer 330 is positioned at described isolation structure 310 surface.
Please refer to Fig. 3, in the present embodiment, described first polysilicon layer 330, first medium layer 340, second polysilicon layer 350 form PIP capacitor device structure.In other embodiments of the invention, dielectric layer can also be comprised between described first polysilicon layer 330 and isolation structure 310.
Further, in an embodiment of the present invention, the first conductive plunger 380 be electrically connected with the first polysilicon layer 330 is also comprised, the second conductive plunger 370 be electrically connected with the second polysilicon layer 350.Described first conductive plunger 380 is positioned at described through hole 360.
In optional embodiment of the present invention, described second polysilicon layer 350 is N-shaped polysilicon layers, or p-type polycrystalline silicon, and the doping type of described second polysilicon layer 350 and concentration can need to regulate according to technique.
Correspondingly, the formation method of the present invention's semiconductor capacitor structure of also providing the first embodiment to provide.Fig. 4 is the formation method of the semiconductor capacitor structure that first embodiment of the invention provides, and comprising:
Step S101, provides Semiconductor substrate;
Step S102, forms the first polysilicon layer at described semiconductor substrate surface;
Step S103, form first medium layer on described first polysilicon layer surface, described first medium layer covers the sidewall of the first polysilicon layer;
Step S104, polysilicon membrane is formed on described first medium layer surface and semiconductor substrate surface, and described polysilicon membrane is etched, form the second polysilicon layer covering first medium layer, described second polysilicon layer has the through hole of exposure first polysilicon layer.
First, with reference to figure 4 and Fig. 5, perform step S101, Semiconductor substrate 300 is provided.
In the present embodiment, described Semiconductor substrate 300 is existing Semiconductor substrate, such as silicon substrate or silicon-on-insulator substrate.In the present embodiment, formation isolation structure 310 in described Semiconductor substrate 300 is also included in.
With reference to figure 4 and Fig. 6, perform step S102, form the first polysilicon layer 330 on described Semiconductor substrate 300 surface.
In the present embodiment, also comprise and adulterating to the first polysilicon layer 330, the type of doping and concentration can need to set according to technique.
With reference to figure 4 and Fig. 7, perform step S103, form first medium layer 340 on described first polysilicon layer 330 surface, described first medium layer 340 covers the sidewall of the first polysilicon layer 330.
At the present embodiment, the material of described first medium layer 340 is silicon dioxide, because described first medium layer 340 is formed at the surface of the first polysilicon layer 330, and cover the sidewall of the first polysilicon layer 330, so first medium layer 340 can the second polysilicon layer of electric isolution first polysilicon layer 330 and follow-up formation.The thickness of first medium layer 340 can have influence on the capacitance characteristic of the capacitor arrangement of follow-up formation, can need to set according to technique.
With reference to figure 4, Fig. 8 and Fig. 9, perform step S104, polysilicon membrane 50 is formed on described first medium layer 340 surface, and described polysilicon membrane 50 is etched, form the second polysilicon layer 350 covering first medium layer 340, described second polysilicon layer 350 has the through hole 360 of exposure first polysilicon layer 330.
First with reference to figure 8, polysilicon membrane 50 is formed on described first medium layer 340 surface; Then photoresist layer is formed on described polysilicon membrane 50 surface, photoresist layer described in patterning, described photoresist layer has the opening corresponding with the position of the through hole 360 of follow-up formation, with described photoresist layer for mask etching polysilicon membrane 50, until exposing semiconductor substrate 300, form the second polysilicon layer 350, etching completes simultaneously removes first medium layer 340 part corresponding with through hole 360 position, until expose the first polysilicon layer 330, form through hole 360.
In the present embodiment, also comprise and adulterating to the second polysilicon layer 350, the type of doping and concentration can need to set according to technique.
In the present embodiment, also comprise: form on the first polysilicon layer 330 surface the first conductive plunger 380 be electrically connected with the first polysilicon layer 330, described first conductive plunger 380 runs through described through hole 360, forms the second conductive plunger 370 be electrically connected with the second polysilicon layer 350.
Described first polysilicon layer 330, first medium layer 340, second polysilicon layer 350 form PIP capacitor device structure.
In the present embodiment, first medium layer 340 covers the sidewall of the first polysilicon layer 330, second polysilicon layer 350 covers first medium layer 340, so carrying out polysilicon membrane 50 etching in the step of formation second polysilicon layer 350, can not have an impact to the first polysilicon layer 330, thus polysilicon stringers can not be produced in the first polysilicon layer 330 both sides.
Second embodiment
Figure 10 is the schematic diagram of the semiconductor capacitor structure that second embodiment of the present invention provides, and comprising:
Semiconductor substrate 400;
Be positioned at first polysilicon layer 430 on described Semiconductor substrate 400 surface; Also comprise:
Be positioned at the first polysilicon layer 430 surface, and cover the first medium layer 440 of the sidewall of the first polysilicon layer 430;
Be positioned at described first medium layer 440 surface, and cover the second polysilicon layer 450 of the sidewall of first medium layer 440;
Run through the second polysilicon layer 450, first medium layer 440, and expose the through hole 460 of the first polysilicon layer 430.
In a second embodiment of the present invention, described Semiconductor substrate 400 also comprises dopant well 490, and the isolation structure 410 between adjacent dopant well 490, be positioned at the second dielectric layer 420 on described dopant well 490 surface, described first polysilicon layer 430 is positioned at second dielectric layer 420 surface.
First polysilicon layer 430, second polysilicon layer 450, Semiconductor substrate 400 (being positioned at the dopant well 490 on Semiconductor substrate 400 surface) form PPS capacitor arrangement.
Other parts of the semiconductor capacitor structure that second embodiment of the present invention provides are identical with the semiconductor capacitor structure that first embodiment of the present invention provides.
Correspondingly, the formation method of the present invention's semiconductor capacitor structure of also providing the second embodiment to provide.
The difference of the formation method of the semiconductor capacitor structure that the formation method of the semiconductor capacitor structure that the second embodiment provides and the first embodiment provide is, in the formation method of the semiconductor capacitor structure provided in the second embodiment, the Semiconductor substrate 400 provided also comprises described Semiconductor substrate and also comprises dopant well 490, isolation structure 410 between adjacent dopant well 490, and be positioned at the described second dielectric layer 420 on described dopant well 490 surface, and form the first polysilicon layer 430 on described second dielectric layer 420 surface.The formation method of the semiconductor capacitor structure that other steps can provide with reference to the first embodiment.
To sum up, in the formation method of the semiconductor capacitor structure provided at embodiments of the invention, the second polysilicon layer forming the first polysilicon layer at semiconductor substrate surface successively, be positioned at the first medium layer on described first polysilicon layer surface, be positioned at described first medium layer surface; Wherein, first medium layer covers surface and the sidewall of the first polysilicon layer; Second polysilicon layer covers surface and the sidewall of first medium layer, thus in the step of formation second polysilicon layer, the part corresponding with the first polysilicon layer position for the formation of the polysilicon membrane of the second polysilicon layer is remained completely, and the second polysilicon layer completely covers the sidewall of the first polysilicon layer, thus avoid when etching polysilicon membrane and forming the second polysilicon layer, form polysilicon stringers in the first polysilicon layer both sides; Meanwhile, the through hole exposing the first polysilicon layer may be used in subsequent technique, form the conductive plugs be electrically connected with the first polysilicon layer;
Further, in optional embodiment of the present invention, described Semiconductor substrate also comprises dopant well, and the isolation structure between adjacent dopant well, be positioned at the second dielectric layer on dopant well surface, first polysilicon layer is formed at the surface of described second dielectric layer, thus defines the PPS capacitor arrangement be made up of Semiconductor substrate, the first polysilicon layer, the second polysilicon layer;
Further, in optional embodiment of the present invention, described Semiconductor substrate also comprises isolation structure, and described second dielectric layer is positioned at described isolation structure surface, thus defines the PIP capacitor device structure be made up of the first polysilicon layer, first medium layer, the second polysilicon layer.
Although embodiments of the invention with preferred embodiment openly as above, but it is not for limiting embodiments of the invention, any those skilled in the art are not departing from the spirit and scope of embodiments of the invention, the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to embodiments of the invention technical scheme, therefore, every content not departing from embodiments of the invention technical scheme, according to any simple modification that the technical spirit of embodiments of the invention is done above embodiment, equivalent variations and modification, all belong to the protection range of embodiments of the invention technical scheme.
Claims (8)
1. a semiconductor capacitor structure, comprising:
Semiconductor substrate;
Be positioned at the first polysilicon layer of described semiconductor substrate surface;
It is characterized in that, also comprise:
Be positioned at described first polysilicon layer surface, and cover the first medium layer of the first polysilicon layer completely;
Be positioned at described first medium layer surface, and cover the second polysilicon layer of first medium layer completely;
Be formed in described second polysilicon layer and first medium layer, for exposing the through hole of the first polysilicon layer, described through hole is for the formation of the first conductive plunger be electrically connected with the first polysilicon layer.
2. according to semiconductor capacitor structure according to claim 1, it is characterized in that: described Semiconductor substrate also comprises dopant well, adjacent dopant well is separated by isolation structure, and be positioned at the second dielectric layer on described dopant well surface, described first polysilicon layer is positioned at described second dielectric layer surface, and described second polysilicon layer, the first polysilicon layer, dopant well form PPS capacitor arrangement.
3. according to semiconductor capacitor structure according to claim 1, it is characterized in that: described Semiconductor substrate also comprises isolation structure, described first polysilicon layer is positioned at described isolation structure surface, and described first polysilicon layer, first medium layer, the first polysilicon layer form PIP capacitor device structure.
4., according to the semiconductor capacitor structure in claims 1 to 3 described in any one, it is characterized in that, also comprise: the second conductive plunger be electrically connected with the second polysilicon layer.
5. a semiconductor capacitor structure formation method, is characterized in that, comprising:
Semiconductor substrate is provided;
The first polysilicon layer is formed at described semiconductor substrate surface;
Form first medium layer on described first polysilicon layer surface, described first medium layer covers the first polysilicon layer completely;
Polysilicon membrane is formed on described first medium layer surface, described polysilicon membrane covers first medium layer completely, and described polysilicon membrane and first medium layer are etched, form the through hole of exposure first polysilicon layer, described through hole is for the formation of the first conductive plunger be electrically connected with the first polysilicon layer, and described polysilicon membrane is through etching formation second polysilicon layer.
6. according to semiconductor capacitor structure formation method according to claim 5, it is characterized in that, also comprise: in described Semiconductor substrate, form dopant well, adjacent dopant well is separated by isolation structure, second dielectric layer is formed on described dopant well surface, described first polysilicon layer is formed at described second dielectric layer surface, and described first polysilicon layer, the second polysilicon layer, dopant well form PPS capacitor arrangement.
7. according to semiconductor capacitor structure formation method according to claim 5, it is characterized in that, also comprise: in described Semiconductor substrate, form isolation structure, form the first polysilicon layer on described isolation structure surface, described first polysilicon layer, first medium layer, the second polysilicon layer form PIP capacitor device structure.
8. according to the semiconductor capacitor structure formation method in claim 5 to 7 described in any one, it is characterized in that, also comprise: form the second conductive plunger be electrically connected with the second polysilicon layer.
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102723262B (en) * | 2012-06-26 | 2016-09-07 | 上海华虹宏力半导体制造有限公司 | The forming method of semiconductor capacitor |
| CN102751176B (en) * | 2012-07-04 | 2017-05-17 | 上海华虹宏力半导体制造有限公司 | Manufacture method for PIP (poly-insulator-poly) and PPS (polypropylene film) capacitor |
| CN102945849A (en) * | 2012-11-30 | 2013-02-27 | 上海宏力半导体制造有限公司 | Semiconductor capacitor structure and manufacture method thereof |
| CN103426728B (en) * | 2013-08-29 | 2017-06-09 | 上海华虹宏力半导体制造有限公司 | Capacitor arrangement and preparation method thereof |
| CN111525030B (en) * | 2020-04-29 | 2023-02-07 | 上海华虹宏力半导体制造有限公司 | PPS capacitor and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5023694A (en) * | 1988-08-03 | 1991-06-11 | Xicor, Inc. | Side wall contact in a nonvolatile electrically alterable memory cell |
| CN101740639A (en) * | 2008-11-24 | 2010-06-16 | 上海华虹Nec电子有限公司 | Polycrystalline silicon electric resistance and manufacturing method thereof |
| CN101937878A (en) * | 2010-07-30 | 2011-01-05 | 上海宏力半导体制造有限公司 | Memory and method for manufacturing same |
-
2011
- 2011-05-23 CN CN201110134652.0A patent/CN102214702B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5023694A (en) * | 1988-08-03 | 1991-06-11 | Xicor, Inc. | Side wall contact in a nonvolatile electrically alterable memory cell |
| CN101740639A (en) * | 2008-11-24 | 2010-06-16 | 上海华虹Nec电子有限公司 | Polycrystalline silicon electric resistance and manufacturing method thereof |
| CN101937878A (en) * | 2010-07-30 | 2011-01-05 | 上海宏力半导体制造有限公司 | Memory and method for manufacturing same |
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