CN102214599B - Method for forming through holes - Google Patents
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- CN102214599B CN102214599B CN 201010144205 CN201010144205A CN102214599B CN 102214599 B CN102214599 B CN 102214599B CN 201010144205 CN201010144205 CN 201010144205 CN 201010144205 A CN201010144205 A CN 201010144205A CN 102214599 B CN102214599 B CN 102214599B
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Abstract
The invention provides a method for forming through holes. The method comprises the following steps: measuring adsorption electrode voltage required for etching a through hole with first target size in a dielectric layer by using an etching cavity in advance; according to the variable quantity of second target size relative to the first target size, the adsorption electrode voltage required for forming the through hole with the first target size and a functional relationship between the variable quantity of the target size and the variable quantity of the adsorption electrode voltage, obtaining adsorption electrode voltage required for forming a through hole with the second target size; under the adsorption electrode voltage required for forming a through hole with the second target size, etching by using the etching cavity to form a through hole with the second target size in a dielectric layer. By the adoption of the method disclosed by the invention, the characteristic sizes of the through holes are reduced after etching.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of method for forming via.
Background technology
Super large rule are touched integrated circuit (Very Large Scale Integrated Circuit, VLSI) usually need the above metal level of one deck that enough interconnection capabilities are provided, being connected by the through hole of filled conductive material between the interconnection between this multiple layer metal and device active region and the external circuitry realizes, and for guaranteeing the stability of device work, require between through hole without being electrically connected, so that the strict control of via etch process is become extremely important.
In via etch, to measure through hole respectively after the photoetching He after the etching.The size of the through hole that forms in mask layer after the photoetching characterizes by ADI (After Develop inspection) CD (CriticalDimension), and the size of the through hole that forms in dielectric layer after the etching characterizes by AEI (After ETCHinspection) CD.Along with the decline of process node, the size of through hole is also more and more less, in order to realize reducing of AEI CD, utilizes in the prior art the way that reduces ADI CD.For example by adjusting the structure of etching mask pattern before.
For example in the Chinese patent application of title " etching method for forming through hole and through hole mask " application number " 200710040254.6 ", provide a kind of etching method for forming through hole, the method is by increase by an auxiliary mask on intrinsic through hole mask basis, reducing the dimension of picture of inherent condition lower through-hole mask, thereby utilize the size of through hole in the dielectric layer that described mask reduces to form.But the method that reduces clear size of opening in the mask pattern is complicated operation not only, and is subject to easily the restriction of manufacturing process, so that reducing of ADI CD is very limited.
Summary of the invention
The technical problem that the present invention solves is the characteristic size that reduces through hole after the etching.
In order to address the above problem, the invention provides a kind of method for forming via, comprising:
Etching cavity and wafer are provided, in etching cavity, comprise for the electrostatic chuck of placing wafer, has adsorption electrode on the described electrostatic chuck, when applying voltage to described adsorption electrode, then adsorption electrode produces the power of wafer to the absorption of electrostatic chuck direction, and described wafer comprises dielectric layer and the mask pattern that is positioned on the dielectric layer;
Measure in advance and utilize described etching cavity etching, in dielectric layer, form the needed adsorption electrode voltage of first object size through hole;
According to variable quantity, the formation first object size through hole needed adsorption electrode voltage of the second target size with respect to the first object size, and the functional relation between described target size variable quantity and the described adsorption electrode voltage variety, obtain forming the required adsorption electrode voltage of the second target size through hole;
Under the required adsorption electrode voltage of described the second target size through hole, utilize described etching cavity etching, in dielectric layer, form the through hole of the second target size.
Preferably, described etching is plasma etching.
Preferably, described target size variable quantity is less than or equal to 10 nanometers, and the required adsorption electrode voltage of described the second target size through hole is 5V to 20V.
Preferably, when etching formed the second target size and first object size through hole, etching parameters and mask pattern except the voltage of adsorption electrode were identical.
Preferably, the functional relation between described target size variable quantity and the described adsorption electrode voltage variety is:
The variable quantity of described target size=-m * described adsorption electrode voltage variety, m is positive number.Preferably, described m equals 0.2 to 0.6, and described target size variable quantity unit is nanometer, and described adsorption electrode voltage variety unit is volt.
Preferably, described electrostatic chuck is circular, and described adsorption electrode comprises at least three strip electrodes that distribute along the diametric(al) of electrostatic chuck, and is successively equal angle.
Preferably, described electrostatic chuck is circular, and described adsorption electrode comprises at least three through the curve-like electrode in the center of circle.
Compared with prior art, the present invention mainly has the following advantages:
Usually all be by adjusting the structure of the mask pattern that forms before the etching in the prior art, adjust the characteristic size of the through hole that forms after the etching, but this adjustment is very limited, just can't reduce continuing after for example the characteristic size of through hole is adjusted to certain size after with etching, and the present invention adjusts the characteristic size of the through hole of etching formation by adjusting adsorption electrode voltage, thereby by being increased, the voltage of adsorption electrode can be further the characteristic size of through hole be reduced like this, thereby so that the characteristic size of through hole can further reduce, and simple process operates easily.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
Fig. 1 is method for forming via flow chart of the present invention;
Fig. 2 is the schematic diagram of the employed etching cavity of method for forming via of the present invention;
Fig. 3 is the chip architecture schematic diagram to be etched among the present invention;
Fig. 4 is that the characteristic size of etching through hole is with adsorption electrode change in voltage schematic diagram;
Fig. 5 is method for forming via principle schematic of the present invention.
Embodiment
By background technology as can be known, along with the decline of process node, the size of through hole is also more and more less, in order to realize reducing of AEI CD, utilizes in the prior art the way that reduces ADI CD.For example existing by adjusting the structure of the mask pattern that forms before the etching, adjust the characteristic size of the through hole that forms after the etching, but this adjustment is very limited, just can't reduce continuing after for example the characteristic size of through hole is adjusted to certain size after with etching.
The present inventor has obtained a kind of method for forming via through a large amount of experimental studies, comprising: measure in advance and utilize described etching cavity etching, form the needed adsorption electrode voltage of first object size through hole in dielectric layer; According to variable quantity, the formation first object size through hole needed adsorption electrode voltage of the second target size with respect to the first object size, and the functional relation between described target size variable quantity and the described adsorption electrode voltage variety, obtain forming the required adsorption electrode voltage of the second target size through hole; Under the required adsorption electrode voltage of described the second target size through hole, utilize described etching cavity etching, in dielectric layer, form the through hole of the second target size.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing specific implementation of the present invention is described in detail.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization in the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public implementation.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 1 is method for forming via flow chart of the present invention.Fig. 2 is the schematic diagram of the employed etching cavity of method for forming via of the present invention.Below in conjunction with Fig. 1 and Fig. 2 method for forming via of the present invention is described.
Method for forming via comprises in the present embodiment:
Step S10, etching cavity and wafer are provided, in etching cavity, comprise for the electrostatic chuck of placing wafer, has adsorption electrode on the described electrostatic chuck, when applying voltage to described adsorption electrode, then adsorption electrode produces the power of wafer to the absorption of electrostatic chuck direction, and described wafer comprises dielectric layer and the mask pattern that is positioned on the dielectric layer.
Please refer to Fig. 2, Fig. 2 provides a kind of etching cavity schematic diagram of etching apparatus.Described etching cavity is used for carrying out plasma etching, and it is hermetically-sealed construction, by plasma generator (not shown) plasma etching gas, the pattern etching of the surperficial selection area of wafer (not shown) is removed.
Wherein in etching cavity 100, comprise electrostatic chuck (Electro Static Chuck, E-chuck) 110, described electrostatic chuck is positioned at the etching cavity bottom, described electrostatic chuck is circular, have at least three banded electrode wires 115 that distribute along the electrostatic chuck diametric(al) at electrostatic chuck, be successively equal angle between the described electrode wires 115, for example three are 60 ° of angles, described electrode wires 115 consists of adsorption electrode, apply voltage to adsorption electrode, namely give between the two ends of every strip electrode line 115 to connect alternating current, then described adsorption electrode can produce the effect of power, wafer is adsorbed to the electrostatic chuck direction, thereby wafer is fixed on the electrostatic chuck.Apart from the above, adsorption electrode can also be for being attached to chip sucking other structure on the electrostatic chuck, and for example described adsorption electrode comprises at least three through the curve-like electrode in the center of circle.
In the present embodiment, can also comprise the cover ring (Cover Ring) (not shown) that is positioned at etching cavity 100 and is positioned at electrostatic chuck 110 surfaces in the etching cavity, be used for the isolation plasma, avoid plasma directly to contact with electrostatic chuck 110, cause current lead-through, so that electrostatic chuck 110 is broken by plasma.
Fig. 3 is the chip architecture schematic diagram to be etched among the present invention.Can have dielectric layer 210 and the mask pattern 220 that is positioned on the dielectric layer on the wafer 200, the material of described dielectric layer 210 is selected from the SiO2 of SiO2 or doping usually, USG (Undoped silicon glass for example, the silex glass that does not have doping), BPSG (Borophosphosilicate glass, the silex glass of boron phosphorus doped), BSG (borosilicate glass, the silex glass of doped with boron), PSG (Phosphosilitcate Glass, the silex glass of Doping Phosphorus) etc.
Step S20 measures in advance and utilizes described etching cavity etching, forms the needed adsorption electrode voltage of first object size through hole in dielectric layer.Wherein the first object size is AEI, i.e. size after the etching.
Concrete, can carry out etching to a wafer in advance, in dielectric layer 210, form the through hole of first object size, just can know afterwards the needed adsorption electrode voltage of through hole of first object size.
Usually, the voltage that adds on the described adsorption electrode is by device fabrication manufacturer regulation, and it can produce the power of absorption wafer, and for example voltage is the alternating current of 5V.Utilize this etching cavity to carry out plasma etching, can specifically comprise: the etching apparatus chamber pressure is 10 millitorr to 50 millitorrs, and the top radio-frequency power is 200W to 500W, and the bottom radio-frequency power is 150W to 300W, C
4F
8Flow is per minute 10SCCM to 50SCCM, and the CO flow is 100SCCM to 200SCCM, and the Ar flow is 300SCCM to 600SCCM, O
2Flow is 10SCCM to 50SCCM, and etching dielectric layer 210 is until form through hole.
Wherein, for example adsorption electrode voltage is the alternating current of 2V, and first object is of a size of 61 nanometers.
Above-mentioned measurement first object size and the required adsorption electrode voltage purpose of first object size that forms are to provide reference quantity for through hole that the back etching forms the second target size.
Step S30, according to variable quantity, the formation first object size through hole needed adsorption electrode voltage of the second target size with respect to the first object size, and the functional relation between described target size variable quantity and the described adsorption electrode voltage variety, obtain forming the required adsorption electrode voltage of the second target size through hole.Wherein, the second target size is AEI, i.e. size after the etching.
Concrete, before etching, usually can set the clear size of opening of formation to be etched.The present inventor draws under study for action, as shown in Figure 4, under same etching condition during etching, increase along with adsorption electrode voltage, the size of the through hole that etching forms can diminish, and for example is increased to 20V at adsorption electrode voltage by 5V, and then clear size of opening (relatively under the adsorption electrode voltage in the situation of 5V) reduces value and increases to 7nm from 1nm, be in the 5V to 20V at voltage namely, through hole can change in 10 nanometer range along with voltage.The inventor thinks that this is because adsorption electrode can produce one to the power of electrostatic chuck direction absorption, increase along with voltage on the adsorption electrode, this absorption affinity also can increase, plasma also can be subject to this absorption affinity effect in etching, this absorption affinity is larger, then the collision effect of plasma is larger, be that the etching effect is stronger, as shown in Figure 5, thereby so that mask pattern is depleted is more, the effect that mask pattern is subject to etching can form polymer deposition on the sidewall of the open bottom of mask pattern, namely the sidewall slope of mask pattern, so that the dielectric layer area that mask pattern exposes reduces, thus the size reduction of the through hole that in dielectric layer, forms.
Therefore the test of inventor by repeatedly for example in the constant situation of other etching condition, carried out etching from increasing gradually adsorption electrode voltage below the 5V, and measured the clear size of opening after the etching, obtains test data as shown in Figure 4.According to test data shown in Figure 4, shift the variable quantity that obtained target size and the functional relation between the described adsorption electrode voltage variety onto, it is concrete that the process of shifting onto can two some abscissas on the figure subtract each other among Fig. 4 in order to get, ordinate subtracts each other, thereby just can obtain, between functional relation.The variable quantity of described target size=-m * described adsorption electrode voltage, m is positive number.The concrete etching parameters of utilizing in the present embodiment, described m equals 0.2 to 0.6, and namely as adsorption electrode voltage increase 5V, then target size reduces about 1nm to 3nm, the variable quantity unit of described target size is nanometer, and described adsorption electrode voltage unit is volt.Certainly; except this functional relation; those skilled in the art also can be according to its etching parameters and etching technics; obtain in this different functional relation according to test; but the adjustment that utilizes this functional relation to carry out etching CD is key point of the present invention, therefore in this relevant scheme all in protection scope of the present invention.
The inventor thinks through after the lot of experiments, referring to the test data shown in table one and the table two, can pass through to adjust the size of adsorption electrode voltage, and this size to the through hole that etching forms is finely tuned, and concrete effect in 10 nanometer range is better.
Table one adopts 2V adsorption electrode voltage to carry out the clear size of opening test data on the wafer after the etching one time.Table two is for adopting 17V adsorption electrode voltage to carry out clear size of opening test data on wafer after the etching.
Table one
| Wafer 1 | Wafer 2 | |
| Through hole 1CD (nanometer) | 64.1 | 65.6 |
| Through hole 2CD (nanometer) | 61.7 | 67.1 |
| Through hole 3CD (nanometer) | 61.3 | 64.5 |
| Through hole 4CD (nanometer) | 65.8 | 66.6 |
| Through hole 5CD (nanometer) | 62.9 | 66.6 |
| Through hole 6CD (nanometer) | 62.1 | 66.4 |
| Through hole 7CD (nanometer) | 62.2 | 66.2 |
| Through hole 8CD (nanometer) | 61.4 | 64.5 |
| Through hole 9CD (nanometer) | 61.7 | 66.2 |
Table two
| Wafer 1 | Wafer 2 | |
| Through hole 1CD (nanometer) | 55.0 | 55.5 |
| Through hole 2CD (nanometer) | 57.0 | 56.5 |
| Through hole 3CD (nanometer) | 55.8 | 56.1 |
| Through hole 4CD (nanometer) | 54.3 | 56.6 |
| Through hole 5CD (nanometer) | 55.9 | 57.9 |
| Through hole 6CD (nanometer) | 56.3 | 57.3 |
| Through hole 7CD (nanometer) | 56.0 | 57.1 |
| Through hole 8CD (nanometer) | 56.0 | 56.5 |
| Through hole 9CD (nanometer) | 55.9 | 56.1 |
In the present embodiment, need etching to form the through hole of the second target size, therefore in this step at first according to the variable quantity of described target size and the variable quantity of the functional relation target size between the described adsorption electrode voltage variety=-m * described adsorption electrode voltage, just can obtain forming the required adsorption electrode voltage of the second target size through hole.
Concrete, the magnitude relationship of the through hole of comparison the second target size and the through hole of first object size.For example the second target size is 55 nanometers, and first object is of a size of 61 nanometers, and the variable quantity of target size is-6 nanometers, then utilizes described functional relation, can obtain the adsorption electrode voltage variety and can be 10V to 30V.In the present embodiment, adsorption electrode voltage has increased 15V, is 17V.Need to prove that if etching parameters changes then described adsorption electrode voltage also can change, occurrence those skilled in the art can obtain in conjunction with the experiment of the functional relation between etching parameters and the described adsorption electrode voltage by limited number of time.
The method of concrete adjustment adsorption electrode voltage can be utilized the power supply that is adjusted into the adsorption electrode power supply, perhaps obtains by increase bleeder circuit between power supply and adsorption electrode.
Step S30 under the required adsorption electrode voltage of described the second target size through hole, utilizes described etching cavity etching, forms the through hole of the second target size in dielectric layer.
Concrete, when etching formed the second target size and first object size through hole, etching parameters and mask pattern except the voltage of adsorption electrode were identical.For example this step etching specifically comprises: utilize this etching cavity to carry out plasma etching, can specifically comprise: the etching apparatus chamber pressure is 10 millitorr to 50 millitorrs, the top radio-frequency power is 200W to 500W, the bottom radio-frequency power is 150W to 300W, the C4F8 flow is per minute 10SCCM to 50SCCM, the CO flow is 100SCCM to 200SCCM, and the Ar flow is 300SCCM to 600SCCM, O
2Flow is 10SCCM to 50SCCM, and etching dielectric layer 210 is until form through hole.In this step etching, adsorption electrode voltage is 17V.
In order to reach better etching effect, when carrying out the etching of the second target size through hole, can also adjust other etching parameters when regulating adsorption electrode voltage.
The present invention has reduced the size of through hole by adjusting adsorption electrode voltage, thereby so that etching technics further improves, the size of device is further dwindled, and has promoted greatly the development of semiconductor fabrication.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (6)
1. method for forming via comprises:
Etching cavity and wafer are provided, in etching cavity, comprise for the electrostatic chuck of placing wafer, has adsorption electrode on the described electrostatic chuck, when applying voltage to described adsorption electrode, then adsorption electrode produces the power of wafer to the absorption of electrostatic chuck direction, and described wafer comprises dielectric layer and the mask pattern that is positioned on the dielectric layer;
Measure in advance and utilize described etching cavity etching, in dielectric layer, form the needed adsorption electrode voltage of first object size through hole;
It is characterized in that, also comprise step:
According to variable quantity, the formation first object size through hole needed adsorption electrode voltage of the second target size with respect to the first object size, and the functional relation between described target size variable quantity and the described adsorption electrode voltage variety: the variable quantity of described target size=-m * described adsorption electrode voltage variety, m equals 0.2 to 0.6, described target size variable quantity unit is nanometer, described adsorption electrode voltage variety unit is volt, obtains forming the required adsorption electrode voltage of the second target size through hole; Wherein, described target size variable quantity be the second target size with respect to the variable quantity of first object size, its scope is less than or equal to 10 nanometers; Described adsorption electrode voltage variety is for forming the needed adsorption electrode voltage of the second target size through hole with respect to the variable quantity that forms the needed adsorption electrode voltage of first object size through hole;
Under the required adsorption electrode voltage of described the second target size through hole, utilize described etching cavity etching, in dielectric layer, form the through hole of the second target size.
2. method for forming via according to claim 1 is characterized in that, described etching is plasma etching.
3. method for forming via according to claim 2 is characterized in that, the required adsorption electrode voltage of described the second target size through hole is 5V to 20V.
4. method for forming via according to claim 2 is characterized in that, when etching formed the second target size and first object size through hole, etching parameters and mask pattern except the voltage of adsorption electrode were identical.
5. method for forming via according to claim 1 is characterized in that, described electrostatic chuck is circular, and described adsorption electrode comprises at least three strip electrodes that distribute along the diametric(al) of electrostatic chuck, and is successively equal angle.
6. method for forming via according to claim 1 is characterized in that, described electrostatic chuck is circular, and described adsorption electrode comprises at least three through the curve-like electrode in the center of circle.
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| US9754822B1 (en) | 2016-03-02 | 2017-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method |
| US10199500B2 (en) | 2016-08-02 | 2019-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer film device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101207069A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming of via hole |
| CN101295643A (en) * | 2007-04-24 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Through hole etching method and through hole mask |
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| JP2002244296A (en) * | 2001-02-19 | 2002-08-30 | Matsushita Electric Ind Co Ltd | Hole pattern forming method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101207069A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming of via hole |
| CN101295643A (en) * | 2007-04-24 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Through hole etching method and through hole mask |
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