CN102214105A - Parallel speedy starting method and electronic device having multiple processing units - Google Patents
Parallel speedy starting method and electronic device having multiple processing units Download PDFInfo
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- CN102214105A CN102214105A CN2010101412956A CN201010141295A CN102214105A CN 102214105 A CN102214105 A CN 102214105A CN 2010101412956 A CN2010101412956 A CN 2010101412956A CN 201010141295 A CN201010141295 A CN 201010141295A CN 102214105 A CN102214105 A CN 102214105A
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Abstract
The invention discloses a parallel speedy starting method and an electronic device having multiple processing units. The parallel speedy starting method is suitable for the electronic device having multiple processing units and comprises the following steps of: (a) enabling a first processing unit of the electronic device to execute a program which can initialize hardware equipment; (b) after the process of initializing the hardware equipment is finished, enabling the first processing unit to load at least one link library, which is called exclusively by a second processing unit of the electronic device, from a storage medium to a random access memory; and (c) enabling the second processing unit to execute a kernel start of an operating system, and then, to load the rest link library, which is called exclusively by the storage medium, from the storage medium. With the first processing unit assisting in preloading the link libraries for the second processing unit, the time for starting can be shortened.
Description
Technical field
The present invention relates to a kind of startup method, particularly relate to the parallelization quick start method that a kind of quickening has the electronic installation toggle speed of multiplied unit with electronic installation of multiplied unit.
Background technology
Portable electric devices such as intelligent mobile phone have functions such as communication, data transmission and multimedia concurrently, along with technical development is ripe and universal day by day.The processor of this type electronic installation (CPU) needs to handle extensive application program and multimedia file, and the CPU framework of double-core (DualCore) is done one's utmost to develop to improve operation efficiency for this reason by well-known in recent years chip factory.
For instance, QualCom (Qualcomm) wherein a pair of core processor framework promptly adopts a slower processing core, for example carry out the ARM9 that clock is 256MHz, carry out the communication special purpose operating system and handle the 3G communications protocol, adopt one to handle core faster in addition, for example carry out the ARM11 that clock is 768～1000MHz, carry out the operating system (for example Windows Mobile or Linux) of application layer.
Consult Fig. 1, when start, ARM9 carries out Boot Loader in the phase one.The main operation task of Boot Loader comprises the initialization computer hardware, takes hardware environment to a proper state.After the phase one finishes, ARM9 handles the loading action of the operating system that the 3G communications protocol uses (being called for short the communication operation system) on the one hand, notifies ARM11 to carry out the operating system (illustrating with Linux) of the work-load application layer of subordinate phase on the other hand.The subordinate phase contents processing comprises Linux core (kernel) start, loads the initialization of chained library (library) and all hardware periphery, approximately needs 20 seconds time to finish.Next ARM11 continues to carry out the phase III, starts graphical user's interface (being called for short UI).Yet graceful UI design makes ARM11 more and more huger at the chained library of required loading of phase III, drags the slow on time.
Under present start mechanism, because being longer than ARM9, the ARM11 processing time adds the time of carrier communication with operating system, even and if communication loads already with operating system and finishes, do not load under the situation about finishing at (SuSE) Linux OS and user's interface, ARM9 also can't enable the relevant running of communication and the sky etc. that can only leave unused.Because the user of portable electric device always wishes can use immediately after this portable electric device powers on, tens of seconds on time always allows the user feel quite very long.
In order to improve long problem of aforementioned on time, normally change more dynamical processing core and carry out in-cycle work, but cost certainly will increase.
Summary of the invention
Therefore, purpose of the present invention promptly in that a kind of parallelization quick start method is provided, is applicable to the electronic installation with multiplied unit, but and by the rewriting of the program of initialization computer hardware and realize.
Another object of the present invention is to provide a kind of electronic installation, but accelerates starting up speed by the rewriting of the program of initialization computer hardware.
For achieving the above object, but comprising one, electronic installation of the present invention stores the program of an initialization computer hardware and Storage Media, a random access memory of most chained libraries, and one first processing unit and one second processing unit.The parallelization quick start method that this electronic installation is carried out comprises following steps:
(a) but make this first processing unit carry out the program of an initialization computer hardware; When the initialization computer hardware is finished, execution in step (b) and (c).
(b) this first processing unit is loaded into random access memory from a Storage Media with at least one chained library that is used by the exclusive calling of this second processing unit.
(c) make this second processing unit carry out the core start of an operating system, then load all the other chained libraries by itself exclusive calling from this Storage Media.
Preferably, the chained library of the described loading of this step (b) comprise an application layer operating system to the small part chained library, even also comprise at least partly chained library that graphical user's interface is contained.
Preferably, this electronic installation is an embedded system such as intelligent mobile phone for example, but and the program of initialization computer hardware be meant Boot Loader.Yet the present invention is not exceeded with embedded system, can also be general computer system, by bios program initialization computer hardware.
Preferably, this first processing unit is to tabulate according to a default chained library that writes on Boot Loader to carry out the work of preload chained library.
Preferably, this first processing unit and second processing unit are that two in the middle of a pair of core processor or the multi-core processor handle core, or two processors.
Effect of the present invention is to make first processing unit share the loading work of part second processing unit with the rewriting of program, need not change hardware and can shorten the overall startup time, shortens user's stand-by period.
Description of drawings
Fig. 1 is an existing start schematic flow sheet with electronic installation of double-core processor, and the wherein workflow of two processing cores is described;
Fig. 2 is a device calcspar, illustrates that the present invention has the preferred embodiment of the electronic installation of multiplied unit;
Fig. 3 is a start schematic flow sheet, and the workflow of first processing unit and second processing unit of present embodiment is described; And
Fig. 4 is that a chained library loads synoptic diagram, illustrates that chained library loads the corresponding relation of a random access memory from a Storage Media.
The reference numeral explanation
1 ... first processing unit
2 ... second processing unit
3 ... Storage Media
4……………RAM
10 ... virtual memory
20 ... virtual memory
100 ... electronic installation
S1～S6 ... step
Embodiment
About aforementioned and other technology contents, characteristics and effect of the present invention, in detailed description, can clearly present below in conjunction with reference to the accompanying drawings a preferred embodiment.
Consult Fig. 2, the preferred embodiment of electronic installation 100 of the present invention is one to have the embedded system (Embedded system) of a plurality of processing units, by the Boot loader utility or have integrated circuit (IC) the initialization computer hardware of identical function.Aforementioned a plurality of processing unit is meant that electronic installation 100 adopts double-core (Dual Core) or multi-core processor (CPU), or has an above CPU.Below illustrate with double-core CPU.
This electronic installation 100 comprises one first processing unit 1, one second processing unit 2, for example is the nonvolatile storage medium 3 of flash memory (flash), and a random-access memory (ram) 4.First, second processing unit 1,2 of present embodiment is two arithmetic cores in the middle of the double-core processor, first processing unit, 1 arithmetic capability is lower, function with data and communication, second processing unit, 2 arithmetic capabilities are higher, in order to handle various application programs.But the present invention can adopt the arithmetic core of same performance not as limit.
Store a Boot loader utility, in the Storage Media 3 and be mainly used in the operating system of handling the 3G communications protocol, below with the OS_1 designate, and one for example be the operating system of application layers such as Linux or Windows Mobile, below with the OS_2 designate.
In conjunction with consulting Fig. 3 and Fig. 4, when electronic installation 100 powered on, first processing unit 1 was sent instruction, the Boot loader utility in the Storage Media 3 is read and begin by this first processing unit, 1 exclusive virtual memory (virtual memory) 10 and carry out.In Boot Loader implementation, can finish computer hardware initialization (step S1).
For avoiding first processing unit 1 after executing the computer hardware initialization, directly to begin to load OS_1, second processing units 2 such as sky cause leaving unused at last, the Boot Loader of present embodiment makes first processing unit 1 after carrying out the computer hardware initialization, not only send signalisation second processing unit 2 and carry out OS_2 core (kernel) start (step S4), and first processing unit 1 itself is gone back with reference to default chained library (library) tabulation the carrying out work (step S2) of preload OS_2 part chained library.Aforementioned " part chained library " is meant the central part of a plurality of chained libraries of operating system, certainly, also can be designed to the all-links storehouse of preload operating system on real the work.
Present embodiment writes on default chained library tabulation in the middle of the Boot loader utility, when the instruction that first processing unit 1 reads the preload chained library, then from Storage Media 3 specified chained library in this chained library tabulation is read.The chained library of reading is stored in first logical address in the exclusive virtual memory 10 of one first processing unit 1, be actually the physical address that loads this first logical address of to video among the RAM 4, this physical address second logical address in the exclusive virtual memory 20 of second processing unit 2 of can videoing again, second logical address can be called out for second processing unit 2 in the future and be used.The method that first processing unit 1 loads RAM 4 with chained library comprises the reset mode of position (function or symbolrelocation) of fetch program (readahead), parsing program file header (parse header), letter formula/symbol in advance.
Finish when the work of first processing unit, 1 preload chained library, then carry out OS_1 and load action (step S3).
On real the work, this default chained library tabulation comprises the whole or central part chained library of OS_2, is determined according to physical condition by system developer.The parameter that decision chained library tabulation must be considered comprises the usefulness, resource distribution, chained library size, loading required time of first processing unit 1 and second processing unit 2 etc.; Certainly, also need consider the load time of OS_1, to do the estimation of whole on time.What deserves to be mentioned is that except the preload of the chained library of OS_2, the present invention also can design the dynamic link library that makes the graphical required use of user's interface of first processing unit, 1 preload part.
In sum, by the technical scheme that present embodiment proposes, the time that second processing unit 2 loads the OS_2 chained library shortens, and then loads ahead of time the time of user's interface, shortens the whole on time, so can reach purpose of the present invention really.
The above, it only is preferred embodiment of the present invention, and can not limit scope of the invention process with this, promptly all simple equivalent of being done according to claim of the present invention and invention description content change and modify, and all still belong in the scope that patent of the present invention contains.
Claims (11)
1. a parallelization quick start method is applicable to the electronic installation with multiplied unit, comprises following steps:
(a) but make one first processing unit of this electronic installation carry out the program of an initialization computer hardware; When the initialization computer hardware is finished, execution in step (b) and (c);
(b) this first processing unit is loaded into a random access memory from the chained library that a Storage Media uses the exclusive calling of at least one one second processing unit by this electronic installation; And
(c) make this second processing unit carry out the core start of an operating system, then load all the other chained libraries by itself exclusive calling from this Storage Media.
2. parallelization quick start method as claimed in claim 1, wherein, the chained library of the described loading of this step (b) comprise an application layer operating system to the small part chained library.
3. parallelization quick start method as claimed in claim 2, wherein, the chained library of the described loading of this step (b) also comprises at least partly chained library of the required use of graphical user's interface.
4. parallelization quick start method as claimed in claim 2, wherein, but the program of this initialization computer hardware is meant Boot Loader.
5. parallelization quick start method as claimed in claim 4, wherein, this first processing unit is to tabulate according to a default chained library that writes on Boot Loader to carry out the work of preload chained library.
6. electronic installation with multiplied unit comprises:
One Storage Media, but program and most chained library of storage one initialization computer hardware;
One random access memory; And
One first processing unit and one second processing unit, when this electronic installation powers on, but this first processing unit is carried out the program of this initialization computer hardware, and when the initialization computer hardware is finished, this first processing unit is loaded on this random access memory from this Storage Media with wherein at least one chained library that is used by the exclusive calling of this second processing unit, and this second processing unit is carried out the core start of an operating system, then from this Storage Media loading all the other chained libraries by the exclusive calling of this second processing unit.
7. the electronic installation with multiplied unit as claimed in claim 6, wherein, this first processing unit and second processing unit are that two in the middle of a pair of core processor or the multi-core processor handle core, or two processors.
8. the electronic installation with multiplied unit as claimed in claim 6, wherein, the chained library that uses by the exclusive calling of this second processing unit that this first processing unit loads comprise an application layer operating system to the small part chained library.
9. the electronic installation with multiplied unit as claimed in claim 8, wherein, the chained library by the exclusive calling use of this second processing unit that this first processing unit loads also comprises at least partly chained library of the required use of graphical user's interface.
10. the electronic installation with multiplied unit as claimed in claim 8 is an embedded system, but and program that should initialization computer hardware be meant Boot Loader.
11. the electronic installation with multiplied unit as claimed in claim 10, this first processing unit are to tabulate according to a default chained library that writes on Boot Loader to carry out the work of preload chained library.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102929713A (en) * | 2012-10-08 | 2013-02-13 | 清华大学 | Loosely coupled heterogeneous multi-core processing system supporting parallelism of multiple operating systems |
| CN103955376A (en) * | 2014-02-19 | 2014-07-30 | 熊猫电子集团有限公司 | Method for DSP (Digital Signal Processor) self-start secondary demand loading |
| WO2015058478A1 (en) * | 2013-10-24 | 2015-04-30 | 深圳中微电科技有限公司 | Rapid start ui system and rapid start method for electrical appliance |
| CN107256143A (en) * | 2017-04-21 | 2017-10-17 | 青岛海信电器股份有限公司 | A kind of method and Android device of the starting up speed for improving Android device |
| US11144326B2 (en) | 2019-02-19 | 2021-10-12 | Cisco Technology, Inc. | System and method of initiating multiple adaptors in parallel |
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| CN101123686A (en) * | 2006-08-10 | 2008-02-13 | 索尼株式会社 | Electronic appliance and startup method |
| CN101604252A (en) * | 2009-07-10 | 2009-12-16 | 深圳华为通信技术有限公司 | Multicomputer system and multicomputer system startup method |
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| CN1567187A (en) * | 2003-06-11 | 2005-01-19 | 华为技术有限公司 | Data processing system and method |
| US20050289286A1 (en) * | 2004-06-15 | 2005-12-29 | Akihiko Ohwada | Multi-core processor control method |
| CN101123686A (en) * | 2006-08-10 | 2008-02-13 | 索尼株式会社 | Electronic appliance and startup method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102929713A (en) * | 2012-10-08 | 2013-02-13 | 清华大学 | Loosely coupled heterogeneous multi-core processing system supporting parallelism of multiple operating systems |
| WO2015058478A1 (en) * | 2013-10-24 | 2015-04-30 | 深圳中微电科技有限公司 | Rapid start ui system and rapid start method for electrical appliance |
| CN103955376A (en) * | 2014-02-19 | 2014-07-30 | 熊猫电子集团有限公司 | Method for DSP (Digital Signal Processor) self-start secondary demand loading |
| CN107256143A (en) * | 2017-04-21 | 2017-10-17 | 青岛海信电器股份有限公司 | A kind of method and Android device of the starting up speed for improving Android device |
| CN107256143B (en) * | 2017-04-21 | 2023-09-12 | 海信视像科技股份有限公司 | Method for improving starting-up speed of android device and android device |
| US11144326B2 (en) | 2019-02-19 | 2021-10-12 | Cisco Technology, Inc. | System and method of initiating multiple adaptors in parallel |
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| CN102214105B (en) | 2017-05-31 |
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