CN102210100A - Circuit arrangement for amplifying a digital signal, and transceiver circuit for a bus system - Google Patents
Circuit arrangement for amplifying a digital signal, and transceiver circuit for a bus system Download PDFInfo
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- CN102210100A CN102210100A CN2009801444204A CN200980144420A CN102210100A CN 102210100 A CN102210100 A CN 102210100A CN 2009801444204 A CN2009801444204 A CN 2009801444204A CN 200980144420 A CN200980144420 A CN 200980144420A CN 102210100 A CN102210100 A CN 102210100A
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- 230000005669 field effect Effects 0.000 claims abstract description 10
- 230000000295 complement effect Effects 0.000 claims abstract description 5
- 230000000630 rising effect Effects 0.000 abstract description 13
- 230000006854 communication Effects 0.000 description 13
- 230000005540 biological transmission Effects 0.000 description 11
- 238000004891 communication Methods 0.000 description 11
- 238000012546 transfer Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 241001530812 Goupia glabra Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- 230000001105 regulatory effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000013024 troubleshooting Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
- H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
- H03F3/3069—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor the emitters of complementary power transistors being connected to the output
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
- H04L25/085—Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/297—Indexing scheme relating to amplifiers the loading circuit of an amplifying stage comprising a capacitor
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
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- Logic Circuits (AREA)
Abstract
The invention relates to an output circuit (61) for a transceiver circuit (21) for a bus system (11), for amplifying a digital input signal (IN) present at an input connection (78) of the output circuit. The circuit (61) has a transistor stage (63) which is complementary switched and which has two branches (65, 75) which are designed as complementary to each other and switched in series. Each branch (65, 75) has a field effect transistor (M1, M2). In order to provide an output circuit (61) wherein a duration (t1) of a rising edge of an output signal and a duration (t2) of a falling edge of an output signal (OUT) are as uniform as possible, it is suggested that each branch (65, 75) has a current source (71, 77) which is switched in series with a drain to source path of the field effect transistor (M1, M2) of the branch (65, 75), and each current source (71, 77) is designed to produce a current which flows through the branch (65, 75) when the drain to source path of the field effect transistor (M1, M2) of the same branch (65, 75) is at least partially conducting, and the current (11, 12) which can be produced by the current source (71, 77) of the first branch (65, 75) at least substantially corresponds to the current (12, 11) which can be produced by the current source (71, 77) of the first branch (75, 65).
Description
Technical field
The present invention relates to the transceiver circuit that is used for bus system of the feature of a kind of output circuit of feature of the preamble with claim 1 and a kind of preamble with claim 6.
Background technology
Especially the control appliance of automobile or cargo vehicle, sensor technology and actuator usually are connected to each other by communication system (as with the known bus system of title " FlexRay ").The traffic on bus system, visit and reception mechanism and troubleshooting are regulated by agreement.FlexRay be a kind of fast, deterministic (deterministisch) and fault-tolerant bus system, especially in automobile, adopt.The FlexRay agreement is according to time division multiple access (TDMA, Time Division Multiple Access) principle is come work, the fixing time slot of distribution of messages that maybe will transmit wherein for the participant, the message that the participant maybe will be transmitted is accessing communication connection exclusively in these fixing time slots.Time slot repeats with fixing circulation at this, makes message can accurately be forecast by the moment of bus transfer and certainty ground carries out bus access.
For optimal is used for the bandwidth of message transfer on bus system, FlexRay is divided into static part and dynamic part with circulation.Fixing time slot is located in the static part that bus cycle begins at this.In dynamic part, time slot is dynamically by predetermined.Therein, exclusive bus access now respectively only at short notice (in the duration of at least one so-called mini-slot) can realize.Have only when carrying out bus access in mini-slot, this time slot just is extended the required time.Thus, that is have only and when reality also needs bandwidth, just consume this bandwidth.At this, FlexRay communicates with the data transfer rate that is 10Mbit/sec respectively to the maximum by one or two circuits that separate physically.FlexRay also can come work with lower data transfer rate.The passage of realizing by these circuits at this corresponding to bit transmission, especially so-called OSI(open system framework (Open System Architecture)) bit transmission of layer model.The use of two passages is mainly used in redundancy and thus fault-tolerant ground message transfer, yet also can transmit different message, then makes data transfer rate double thus.Usually, message is transmitted by differential signal, that is to say that the signal by connection line transmission is obtained by the difference of the individual signals by two circuits transmission.Layer in layer model on bit transmission is constructed to make this signal or these signals to carry out electrical transmission or optical delivery or otherwise transmit by (a plurality of) circuit.
When data or message were transmitted by this bus system, pulse distortion was because trailing edge on the transmission path (high to low) or rising edge (low to height) are delayed to different intensities.Rising edge and the delay between the trailing edge at this signal also are known as pulse distortion or asymmetric delay.Asymmetric delay can not only have system's reason but also have random cause.Especially under the higher situation of the ratio that in the FlexRay system, is provided with, such the quality of transfer of data is produced the interference influence about rising edge and the asymmetric transmission characteristic of trailing edge for the bit rate of 10MHz.Therefore, the asymmetric transmission characteristic on the physical layer must be avoided as far as possible widely.
Fig. 5 shows the generally well-known circuit arrangement of driver form, and this driver is constructed to have the inverter of the insulating barrier field-effect transistor (MOSFET) of arranging complimentary to one anotherly and constructing.When making this driver, PMOS and the nmos pass transistor having attempted constructing match complimentary to one anotherly as far as possible well.But, because PMOS and nmos pass transistor produced in same manufacturing step, so this pairing is inadequate.This causes by the duration t1 of the rising edge of the output signal of driver generation different with the duration t2 of trailing edge.Fig. 6 shows by the output signal of known driver according to the rectangle input signal generation of driver.
At the switching threshold of following receiver ideally, error running time that is obtained by different duration t1 and t2 is,
│ t1-t2 │=VDD*0.5* │ dV/dt
Rise-dV/dt
Descend│
The transceiver circuit of using for Flexray require for rising edge be identical running time for trailing edge.For example the difference of the edge steepness of 5V port (for example pin RXD) has remarkable contribution for error running time in the system.
Summary of the invention
Task of the present invention is to provide a kind of output circuit, wherein, when the employed field-effect transistor in output circuit of the complementary branch road of output circuit was not configured aspect its electrical characteristics accurately complimentary to one anotherly, the duration of the duration of the rising edge of output signal and the trailing edge of output signal then differed also small as far as possible.
This task solves by a kind of output circuit of the feature with claim 1 and by a kind of transceiver circuit with feature of claim 6.
Recognize that according to the present invention the electrical characteristics of field-effect transistor can be eliminated by using current source at least to a great extent to the influence of the duration at edge.The edge steepness of the output signal that produces by output circuit according to the present invention is irrelevant with the NMOS and the transistorized inadequate pairing of PMOS that especially cause for technical reason by inserting current source.The present invention based on circuit design be suitable for all following application: these are used for the rising edge of signal and require identical delay with trailing edge for signal.Especially, can be configured to terminal RxD and/or be used for the bus terminal BP of Flexray transceiver circuit and the driver of BM according to output circuit of the present invention.
Description of drawings
Other features and advantages of the present invention are obtained by following description, have wherein further set forth exemplary form of implementation with reference to accompanying drawing.At this,
Fig. 1 shows the bus system that has the node that has transceiver circuit respectively;
Fig. 2 shows the schematic diagram according to the output circuit of first preferred implementing form;
Fig. 3 shows the detailed icon of the output circuit among Fig. 2;
Fig. 4 shows the diagram according to the output circuit of second preferred implementing form, and this output circuit has low-resistance output follower (Ausgangsfolger);
Fig. 5 shows the diagram of known circuit arrangement; And
Fig. 6 show under the situation of the known circuit arrangement in Fig. 5 with the edge steepness difference shown in the curve chart and to the signal effect of running time.
Embodiment
Fig. 1 shows bus system 11, and a plurality of nodes 13 are connected on this bus system 11.Bus system 11 can be the FlexRay communication system, and therefore this bus system 11 can be constructed according to the standard of FlexRay association.
Each node 13 directly or indirectly is connected to each other via star-type coupler 17 by bus line 15.Each bus line 15 all is constructed to have the right cable of at least one heart yearn, and described at least one heart yearn is to comprising two heart yearns 19 that form electric conductor respectively.Therefore bus system 11 has the passage that is used to transmit data, and the described passage that is used to transmit data forms by the right heart yearn 19 of heart yearn.In unshowned form of implementation, bus system 11 can have a plurality of passages, two passages preferably, described passage by two heart yearns separated from one another to implementing (not shown).By using two passages can improve the useful data rate of the transfer of data between the node 13 by the different data of transmission on these two passages.Since bus system two heart yearns to one of can work on when fault is arranged, so obtained the higher fail safe of bus system 11.
Each node 13 all has transceiver circuit 21, and this transceiver circuit 21 preferably is constructed to integrated circuit.The first bus terminal BP of transceiver circuit 21 and the second bus terminal BM are connected with one of heart yearn 19 of one of bus line 15 respectively.
Transceiver circuit 21 has and is used for receiving the acceptor circuit 23 of data and that bus line 15 of being used for being connected to by node 13 sends the transmitter circuit 25 of data by bus line 15.Not only acceptor circuit 23 but also transmitter circuit 25 all are connected with BM with two bus terminal BP within transceiver circuit 21.Not only acceptor circuit 23 but also transmitter circuit 25 are all set up the heart yearn that is used for by being connected to the bus line 15 on the corresponding transceiver circuit 21 to transmitting differential digital signal.
Transceiver circuit 21 has logical block 27 in addition, and this logical block 27 is coupled with acceptor circuit 23 and with transmitter circuit 25.Logical block 27 has and is used for transceiver circuit 21 for example is connected to terminal on the control circuit that is formed by microcontroller 31 or microcomputer.These terminals or the circuit that is connected thereto have formed the interface 29 between transceiver circuit 21 and control circuit or microcontroller 31.
Microcontroller 31 has the communication controler 33 that is used to be controlled at the communication process that is undertaken by bus line 15 between the node 13.Communication controler 33 is set up the agreement control communication process that is used for according to bus system 11, in particular for implementing the media access method of bus system 11.Communication controler 33 in addition can by set up for example be used for according to the CRC method calculate Frame that will be by bus line 15 transmission verification and, and/or set up the verification that is used to check the Frame that receives with.
Especially be provided with as interface circuit: circuit RxD is used for transceiver circuit 21 is transferred to communication controler 33 by the data that bus line 15 has received from transceiver circuit 21; And circuit TxD, be used for transceiver circuit 21 should be transferred to transceiver circuit 21 from communication controler 33 by the data that bus line 15 sends.Interface 29 also comprises following other circuit 34 except comprising two circuit RxD and TxD: these other circuits 34 for example are used for exchange of control information between communication controler 33 and transceiver circuit 21.
Microcontroller 31 has the nuclear of calculating 35, memory 37(working storage and/or read-only memory) and input and output device 39.Microcontroller 31 can be set up to be used to implement the other protocol software and/or application program.
Shown in form of implementation in, communication controler 33 is integrated in the microcontroller 31.Therewith differently, in unshowned form of implementation, communication controler 33 is constructed to the circuit that separates with microcontroller 31, preferably is constructed to integrated circuit.
Fig. 2 shows the output circuit 61 of the transceiver circuit 21 that is used to export digital signal OUT.Digital signal OUT can be the bus signals BP and the BM of the digital signal RxD that produced by logical block 27 or two complementations being produced by transmitter circuit 25.In shown form of implementation, logical block 27 and transmitter circuit 25 have one or more output circuit 61.In addition, logical block 27 also can have another output circuit 61 that is used to produce output signal OUT, and this output signal OUT is transferred to microcontroller 31 by in the other circuit 34 at least one by logical block 27.In addition, what also it is contemplated that is that output circuit 61 is integrated in the circuit or member that is different from the transceiver circuit 21.For example, output circuit can be integrated in the microcontroller 31 or be integrated into arbitrarily in other the integrated circuit.
Between the output 69 of output circuit and ground path 73, be furnished with load capacitance 79.The gate terminal of two transistor M1 and M2 is connected to each other and forms the input 78 of output circuit 61.
In the form of implementation shown in Figure 3, two current sources 71,77 are constructed to current mirror.Current mirror has transistor M7.Can be provided with the reference current source 81 that is used for predetermined reference current IREF, described reference current source 81 can link to each other with the drain terminal of transistor M7.Current mirror is also formed by other transistor M3, M4 and M6 except transistor M7, and described other transistor M3, M4 are relevant with first branch road 65 with M6.The transistor M5 of current mirror is relevant with second branch road 75 with transistor M7.In another form of implementation of the present invention, reference current source 81 is not set.
In addition, be connected with the lower leg 89 of current amplifier 83 on the input 87 of current amplifier 83, this lower leg 89 is disposed between output 69 and the ground path 73.Lower leg 89 has the emitter follower that is connected on the input 87, and this emitter follower forms by NPN transistor Q3 and resistance Q2, and lower leg 89 have be connected the downstream be constructed to the transistorized output transistor Q4 of PNP.The emitter terminal of two output transistor Q2 and Q4 is connected to each other and is connected on the output 69 of output circuit 61.Between output 69 and ground path 73, be furnished with load capacitance 79.Between output 91 that links to each other with input 87 current amplifier 83 transistor level 63 and ground path 73, be furnished with the capacitor C 1 of substantial constant at least.Constant capacitor C 1 can be disposed in the semiconductor chip of the integrated circuit that is integrated with output circuit 16.The value of constant capacitor C 1 is by its structure or come predetermined by the structure of semiconductor chip.
When 61 work of the output circuit shown in Fig. 3, digital input signals IN is applied on the input of output circuit.According to the logic state of input signal IN, one of two transistor M1 or M2 connect.The rising edge of the great-jump-forward of input signal IN or trailing edge are converted into continuous rising edge or the trailing edge of the output signal OUT that is produced by output circuit 61 based on load capacitance 79 by output circuit. Current source 71,77 or corresponding current mirror inject following branch road 65 or 75 with predetermined electric current I 1 or I2: described branch road 65 or 75 transistor M1 or M2 connect.If predetermined electric current is selected in the same manner, i.e. I1=I2 then obtains the identical gradient aspect numerical value of the rising edge of digital output signal OUT and trailing edge.
Therefore output circuit 61 makes it possible to implement to have port, for example 5V digital output end at symmetrical edge, that is to say the port that makes it possible to implement to have for rising edge and trailing edge identical edge steepness.
In output circuit 61, not only obtain identical running time by output circuit 61 for the rising edge of the digital signal IN on input 78 but also for the trailing edge of this digital signal IN.Set out thus in this case: receiver subsequently (being generally the input of microcontroller) has its switching threshold under the situation of 0.5*VDD.
dV/dt?=?I/C
When selecting I=I1=I2, form the edge of symmetry.
The Current Control port that output circuit 61 is constructed to have transistor M3 and M4 is with as current source.Electric current by transistor M3 is the duplicate (Kopie) by the electric current of transistor M5.This duplicate produces by M6 and current mirror M4, M3.
In the output circuit shown in Fig. 3 61, edge steepness is relevant with load capacitance 79.For fear of correlation, output 91 that can (as shown in FIG. 4) transistor level 63 is provided with constant and predetermined capacitor C 1.And then unknown relevant with connection line or bus line 15 usually load capacitance 79 is essentially 1 low impedance amplifier 83 at least by gain (Verstaerkung) and drives.Thus, edge steepness and load capacitance 79 are irrelevant.
In the technology that bipolar transistor is not provided, transistor Q1 to Q4 can replace (output impedance │ Z │=1/ (2*gm)) by the MOS transistor that has very large ratio W/L between channel width and channel length.
Claims (6)
1. output circuit (61) that is used for the transceiver circuit (21) of bus system (11), be used to be amplified in the digital input signals (IN) on the input terminal (78) of output circuit, wherein output circuit (61) has the complementary transistor level (63) that switches, described transistor level (63) comprises two branch roads that are connected in series (65 of constructing complimentary to one anotherly, 75), each branch road (65 wherein, 75) all has field-effect transistor (M1, M2), it is characterized in that, each branch road (65,75) all has current source (71 respectively, 77), described current source (71,77) with the field-effect transistor of this branch road (65,75) (M1, drain electrode-source path M2) is connected in series, each current source (71 wherein, 77) all be configured in same branch road (65,75) field-effect transistor (M1, drain electrode-source path M2) produces this branch road (65 of flowing through during to the small part conducting, 75) electric current, electric current (the I1 that can produce by the current source (71,77) of a branch road (65,75) wherein, I2) corresponding essentially at least can be by another branch road (75, the electric current that current source 65) (77,71) produces (I2, I1).
2. circuit according to claim 1 (61) is characterized in that, at least one in the current source (71,77) is constructed to current mirror.
3. circuit according to claim 2 (61), it is characterized in that, current mirror is coupled with the reference current source (81) that is used for predetermined reference current (IREF), make it possible to the corresponding branch road (65 of flowing through by the current mirror generation, electric current 75) (I1, I2) relevant with reference current (IREF).
4. one of require described circuit (61) according to aforesaid right, it is characterized in that, the downstream of the transistor level (63) that switches in complementation is connected with output stage (83).
5. circuit according to claim 4 is characterized in that, output stage is constructed to current amplifier (83), preferably be constructed to have bipolar transistor (Q1, Q2, Q3, current amplifier Q4) (83).
6. transceiver circuit (21) that is used for bus system (11), it has output circuit (61), be used to be amplified in the digital input signals (IN) on the input terminal (78) of output circuit (61), wherein output circuit (61) has the complementary transistor level (63) that switches, described transistor level (63) comprises two branch roads that are connected in series (65 of constructing complimentary to one anotherly, 75), each branch road (65 wherein, 75) all has field-effect transistor (M1, M2), it is characterized in that output circuit (61) is constructed according to one of aforesaid right requirement.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102008057619.0A DE102008057619B4 (en) | 2008-11-10 | 2008-11-10 | Circuit arrangement for amplifying a digital signal and transceiver circuit for a bus system |
| DE102008057619.0 | 2008-11-10 | ||
| PCT/EP2009/062429 WO2010052066A1 (en) | 2008-11-10 | 2009-09-25 | Circuit arrangement for amplifying a digital signal, and transceiver circuit for a bus system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102210100A true CN102210100A (en) | 2011-10-05 |
| CN102210100B CN102210100B (en) | 2015-01-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200980144420.4A Active CN102210100B (en) | 2008-11-10 | 2009-09-25 | Circuit arrangement for amplifying a digital signal, and transceiver circuit for a bus system |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2012508492A (en) |
| CN (1) | CN102210100B (en) |
| DE (1) | DE102008057619B4 (en) |
| WO (1) | WO2010052066A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105684370A (en) * | 2013-11-08 | 2016-06-15 | 罗伯特·博世有限公司 | Subscriber station for a bus system, and method for reducing line-related emissions in a bus system |
| CN111819820A (en) * | 2018-03-12 | 2020-10-23 | 罗伯特·博世有限公司 | Transmitting/receiving device for bus system and method for operating the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102017115511A1 (en) * | 2017-07-11 | 2019-01-17 | Knorr-Bremse Systeme für Nutzfahrzeuge GmbH | Level converter and a method for converting level values in vehicle control devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60150811U (en) * | 1984-03-19 | 1985-10-07 | 三洋電機株式会社 | buffer circuit |
| DE3676297D1 (en) | 1986-03-12 | 1991-01-31 | Itt Ind Gmbh Deutsche | INTEGRATED INSULATION LAYER FIELD EFFECT TRANSISTOR DELAY LINE FOR DIGITAL SIGNALS. |
| JPH01161913A (en) * | 1987-12-18 | 1989-06-26 | Toshiba Corp | Clock driver circuit |
| JP2583294B2 (en) * | 1988-10-28 | 1997-02-19 | 日産自動車株式会社 | Output buffer circuit for pulse transmission |
| JPH03228425A (en) * | 1990-02-01 | 1991-10-09 | Fujitsu Ltd | Semiconductor integrated circuit device |
| JP2800380B2 (en) * | 1990-07-13 | 1998-09-21 | 日産自動車株式会社 | Output buffer circuit |
| JPH07235868A (en) | 1994-02-23 | 1995-09-05 | Nec Corp | Current buffer circuit |
| US5581197A (en) * | 1995-05-31 | 1996-12-03 | Hewlett-Packard Co. | Method of programming a desired source resistance for a driver stage |
| JP3050289B2 (en) * | 1997-02-26 | 2000-06-12 | 日本電気株式会社 | Output impedance adjustment circuit of output buffer circuit |
| JP3334548B2 (en) * | 1997-03-21 | 2002-10-15 | ヤマハ株式会社 | Constant current drive circuit |
| DE102006011059A1 (en) | 2006-03-08 | 2007-09-13 | Robert Bosch Gmbh | Method and system for transmitting data encoded in a signal |
-
2008
- 2008-11-10 DE DE102008057619.0A patent/DE102008057619B4/en active Active
-
2009
- 2009-09-25 WO PCT/EP2009/062429 patent/WO2010052066A1/en active Application Filing
- 2009-09-25 JP JP2011535060A patent/JP2012508492A/en active Pending
- 2009-09-25 CN CN200980144420.4A patent/CN102210100B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105684370A (en) * | 2013-11-08 | 2016-06-15 | 罗伯特·博世有限公司 | Subscriber station for a bus system, and method for reducing line-related emissions in a bus system |
| US10530612B2 (en) | 2013-11-08 | 2020-01-07 | Robert Bosch Gmbh | Subscriber station for a bus system and method for reducing line-related emissions in a bus system |
| CN105684370B (en) * | 2013-11-08 | 2020-04-14 | 罗伯特·博世有限公司 | Subscriber station of a bus system and method for reducing wire-bound emissions in a bus system |
| CN111819820A (en) * | 2018-03-12 | 2020-10-23 | 罗伯特·博世有限公司 | Transmitting/receiving device for bus system and method for operating the same |
| US11502876B2 (en) | 2018-03-12 | 2022-11-15 | Robert Bosch Gmbh | Transceiver device for a bus system and operating method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102210100B (en) | 2015-01-14 |
| DE102008057619A1 (en) | 2010-05-12 |
| DE102008057619B4 (en) | 2021-08-26 |
| WO2010052066A1 (en) | 2010-05-14 |
| JP2012508492A (en) | 2012-04-05 |
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