CN102202118A - Power sequence control circuit on camera and mobile phone - Google Patents
Power sequence control circuit on camera and mobile phone Download PDFInfo
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- CN102202118A CN102202118A CN2011101086453A CN201110108645A CN102202118A CN 102202118 A CN102202118 A CN 102202118A CN 2011101086453 A CN2011101086453 A CN 2011101086453A CN 201110108645 A CN201110108645 A CN 201110108645A CN 102202118 A CN102202118 A CN 102202118A
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Abstract
The invention discloses a power sequence control circuit on a camera and a mobile phone. The power sequence control circuit comprises a plurality of power supply modules and a plurality of branch circuits. The output of each power supply module is a power supply output, and a previous power supply output can act as an enable signal of a next power supply module through the voltage division of a branch circuit. When the voltage of the previous power supply rises to a certain value, the next power supply module enable signal outputs voltage wherein the enable signal of the first power supply module is controlled through GPIO. According to the invention, the traditional method of using software time-delay to realize the time interval of power supply is avoided. The power sequence control circuit in the invention has simple operation and stable and reliable operation process, and only needs a GPIO to control the whole circuit. And the used material is common material, so the power sequence control circuit has a low cost and is very practical.
Description
Technical field
The present invention relates to field of mobile phones, in particular a kind of camera electrifying timing sequence control circuit and a kind of mobile phone.
Background technology
Camera needs the stable electrifying timing sequence of determining, if electrifying timing sequence does not meet the demands, will cause the camera job insecurity or can't work.Camera generally has three-way power, is respectively: DOVDD is as the supply power voltage of IO mouth; DVDD is as the working power of the DSP of camera; AVDD is an analog power, is used to supply with the artificial circuit part of camera.Wherein the power-on time space requirement of the power-on time of DOVDD and AVDD is more than or equal to 0ms, the power-on time of AVDD to the power-on time space requirement of DVDD more than or equal to 0ms.Traditional method is to use three LDO(low pressure difference linear voltage regulators) export three-way power, and each LDO uses a GPIO to control, utilize time that software delay realizes DOVDD to the power-on time of AVDD at interval and the power-on time of AVDD to the power-on time interval of DVDD.So not only take the resource of GPIO, also needed software to do the time that time-delay comes precise control, complicated and inconvenient.
Therefore, prior art has yet to be improved and developed.
Summary of the invention
The object of the present invention is to provide a kind of camera electrifying timing sequence control circuit and a kind of mobile phone, being intended to solve prior camera utilizes software delay to realize the resource that has not only taken GPIO that the control of electrifying timing sequence causes, also need software to do the time that time-delay comes precise control, complicated and inconvenient problem.
Technical scheme of the present invention is as follows:
A kind of camera electrifying timing sequence control circuit, wherein, comprise a plurality of power modules and a plurality of bleeder circuit, each power module is output as the output of one road power supply, and power supply output in last road is by the enable signal of bleeder circuit dividing potential drop as back one road power module, when last road supply voltage rises to certain value, back one road power module enables, output voltage, wherein, the enable signal of first via power module is controlled by GPIO.
Described camera electrifying timing sequence control circuit, wherein, described power module is three, bleeder circuit is two.
Described camera electrifying timing sequence control circuit, wherein, described power module is a low pressure difference linear voltage regulator.
Described camera electrifying timing sequence control circuit, wherein, described bleeder circuit comprises divider resistance.
Described camera electrifying timing sequence control circuit, wherein, described control circuit comprises: first low pressure difference linear voltage regulator, second low pressure difference linear voltage regulator, the 3rd low pressure difference linear voltage regulator, and described first low pressure difference linear voltage regulator is used to produce first via power supply; Described second low pressure difference linear voltage regulator is used to produce the second road power supply; Described the 3rd low pressure difference linear voltage regulator is used to produce the Third Road power supply, and described first via power supply is early than the second road power supply, and described the second road power supply is early than the Third Road power supply; Described circuit also comprises first divider resistance, second divider resistance, the 3rd divider resistance and the 4th divider resistance, wherein, described first divider resistance and second divider resistance are formed the bleeder circuit of first via power supply, will import the enable signal of second low pressure difference linear voltage regulator as the output of the second road power supply after the first via power supply dividing potential drop; Described the 3rd divider resistance and the 4th divider resistance are formed the bleeder circuit of the second road power supply, with input the 3rd low pressure difference linear voltage regulator after the output voltage dividing potential drop of the second road power supply, as the enable signal of Third Road power supply output.
Described camera electrifying timing sequence control circuit, wherein, the voltage input end of described first low pressure difference linear voltage regulator, second low pressure difference linear voltage regulator and the 3rd low pressure difference linear voltage regulator is connected to the output of battery respectively, wherein, the Enable Pin of described first low pressure difference linear voltage regulator connects a pin that is used to produce the GPIO controller of enable signal, when described pin was drawn high, first low pressure difference linear voltage regulator enabled; On the output of described first low pressure difference linear voltage regulator, also connect one first divider resistance, the other end of described first divider resistance connects the Enable Pin of second divider resistance and second low pressure difference linear voltage regulator, the other end ground connection of described second divider resistance; The output of described second low pressure difference linear voltage regulator connects the second road power supply and the 3rd divider resistance, the other end of described the 3rd divider resistance connects the Enable Pin and the 4th divider resistance of the 3rd low pressure difference linear voltage regulator, the other end ground connection of described the 4th divider resistance; The output of described the 3rd low pressure difference linear voltage regulator connects the Third Road power supply.
Described camera electrifying timing sequence control circuit, wherein, on the voltage input end of described first low pressure difference linear voltage regulator, second low pressure difference linear voltage regulator and the 3rd low pressure difference linear voltage regulator, also be connected with first direct-to-ground capacitance, the 3rd direct-to-ground capacitance and the 5th direct-to-ground capacitance respectively; On the voltage output end of described first low pressure difference linear voltage regulator, second low pressure difference linear voltage regulator and the 3rd low pressure difference linear voltage regulator, also be connected with second direct-to-ground capacitance, the 4th direct-to-ground capacitance and the 6th direct-to-ground capacitance respectively.
A kind of mobile phone wherein, is provided with above-mentioned camera electrifying timing sequence control circuit in described mobile phone.
Beneficial effect of the present invention: the present invention produces the needed three-way power of camera by utilization LDO, and produces the output enable signal of next LDO by electric resistance partial pressure.Avoided traditional usefulness to utilize software delay to realize the time interval between power supply.It is very convenient to operate, and running is reliable and stable.Only need to use a GPIO to control entire circuit.And the material that adopts also is material commonly used, so cost is low, and also very practical.
Description of drawings
Fig. 1 is circuit theory diagrams provided by the invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, clear and definite, below develop simultaneously with reference to accompanying drawing that the present invention is described in more detail for embodiment.
The present invention realizes the control of the electrifying timing sequence when load provides multiple power supplies simultaneously of a plurality of power modules.Wherein, be provided with a plurality of power modules and a plurality of bleeder circuit, each power module is output as the output of one road power supply, and power supply output in last road is by the enable signal of bleeder circuit dividing potential drop as back one road power module, when last road supply voltage rises to certain value, back one road power module enables output voltage.Wherein, the enable signal of first via power module is controlled by GPIO.
Referring to Fig. 1, a concrete embodiment circuit provided by the invention, it comprises the first low pressure difference linear voltage regulator U1, the second low pressure difference linear voltage regulator U2, the 3rd low pressure difference linear voltage regulator U3, and the described first low pressure difference linear voltage regulator U1 is used to produce first via power supply DOVDD; The described second low pressure difference linear voltage regulator U2 is used to produce the second road power supply AVDD; Described the 3rd low pressure difference linear voltage regulator U3 is used to produce Third Road power supply DVDD, and described circuit also comprises the first divider resistance R1, the second divider resistance R2, the 3rd divider resistance R3 and the 4th divider resistance R4.Wherein, the described first divider resistance R1 and the second divider resistance R2 form the bleeder circuit of first via power supply DOVDD, will import the enable signal of the second low pressure difference linear voltage regulator U2 as the second road power supply AVDD output after the first via power supply dividing potential drop; Described the 3rd divider resistance R3 and the 4th divider resistance R4 form the bleeder circuit of the second road power supply AVDD, with input the 3rd low pressure difference linear voltage regulator U3 after the output voltage dividing potential drop of the second road power supply, as the enable signal of Third Road power supply DVDD output.
Please continue referring to Fig. 1, the annexation of circuit provided by the invention is: the output VBAT of battery connects the first low pressure difference linear voltage regulator U1 respectively, the voltage input end VI1 of the second low pressure difference linear voltage regulator U2 and the 3rd low pressure difference linear voltage regulator U3, VI2 and VI3, wherein, the Enable Pin EN1 of the described first low pressure difference linear voltage regulator U1 connects a pin that is used to produce the GPIO controller of LDO enable signal, the output VO1 of the described first low pressure difference linear voltage regulator U1 connects first via power supply DOVDD, on the output VO1 of the described first low pressure difference linear voltage regulator U1, also connect one first divider resistance R1, the other end of the described first divider resistance R1 connects the Enable Pin EN2 of the second divider resistance R2 and the second low pressure difference linear voltage regulator U2, the other end ground connection of the described second divider resistance R2; The output VO2 of the described second low pressure difference linear voltage regulator U2 connects the second road power supply AVDD and the 3rd divider resistance R3, the other end of described the 3rd divider resistance R3 connects Enable Pin EN3 and the 4th divider resistance R4 of the 3rd low pressure difference linear voltage regulator U3, the other end ground connection of described the 4th divider resistance R4; The output of described the 3rd low pressure difference linear voltage regulator U3 connects Third Road power supply DVDD.
On voltage input end VI1, the VI2 of the described first low pressure difference linear voltage regulator U1, the second low pressure difference linear voltage regulator U2 and the 3rd low pressure difference linear voltage regulator U3 and VI3, also be connected with the first direct-to-ground capacitance C1, the 3rd direct-to-ground capacitance C3 and the 5th direct-to-ground capacitance C5 respectively.In addition, on voltage output end VO1, the VO2 of the described first low pressure difference linear voltage regulator U1, the second low pressure difference linear voltage regulator U2 and the 3rd low pressure difference linear voltage regulator U3 and VO3, yet be connected with the second direct-to-ground capacitance C2, the 4th direct-to-ground capacitance C4 and the 6th direct-to-ground capacitance C6 respectively.
Described divider resistance is respectively applied for the output enable signal that produces next low pressure difference linear voltage regulator.For the power module that logic control is arranged, only add an effective level at its logic control end, this power module just can be started working.Utilize the dividing potential drop of resistance, can start next power module, also can guarantee that AVDD must be just output after the voltage of DOVDD rises to certain voltage simultaneously, the output of DVDD also is just output after AVDD rises to certain voltage.So just guaranteed the desired electrifying timing sequence of CAMERA.
The first low pressure difference linear voltage regulator U1 output voltage is DOVDD, it is the power supply that is used for to the IO mouth of camera, the first low pressure difference linear voltage regulator U1 what enable termination is the LDO_EN signal, this signal is controlled by GPIO, draw high to enabling DOVDD output, drag down the output of then closing DOVDD.
The second low pressure difference linear voltage regulator U2 output voltage is AVDD, is used for the artificial circuit part power supply of camera inside.The 3rd low pressure difference linear voltage regulator U3 output voltage is DVDD, and it is the DSP power supply of camera inside.
The first low pressure difference linear voltage regulator U1 draw high by LDO_EN enable after, the meeting of its output voltage DOVDD along with output rising and rise.This moment is because the enable signal AVDD_EN of the second low pressure difference linear voltage regulator U2 is the signal that obtains by the first divider resistance R1 and the second divider resistance R2 dividing potential drop, therefore AVDD_EN also can rise along with the rising of DOVDD, when the voltage of AVDD_EN rises to can enable the second low pressure difference linear voltage regulator U2 time, the second road power supply AVDD promptly exports.In like manner, the enable signal DVDD_EN of the 3rd low pressure difference linear voltage regulator U3 also can rise along with the rising of the second road power supply AVDD voltage, when the enable signal DVDD_EN of the 3rd low pressure difference linear voltage regulator U3 rises to can enable the 3rd low pressure difference linear voltage regulator U3 the time, Third Road power supply DVDD promptly exports.
By such design, just can guarantee that the second road power supply AVDD must be just output after the voltage of first via power supply DOVDD rises to certain voltage, the output of Third Road power supply DVDD also is just output after the second road power supply AVDD rises to certain voltage.So just guaranteed the desired electrifying timing sequence of camera.
It is example explanation embodiments of the present invention that the three-way power that present embodiment is formed with three power modules provides power supply to load simultaneously, but is not limited in three-way power, can be for more than three the tunnel, and its control principle is identical with present embodiment.
The present invention also provides a kind of mobile phone, is provided with above-mentioned electrifying timing sequence control circuit in described mobile phone.LDO produces the needed three-way power of camera by utilization, and produces the output enable signal of next LDO by electric resistance partial pressure.Avoided traditional usefulness to utilize software delay to realize the time interval between power supply.It is very convenient to operate, and running is reliable and stable.Only need to use a GPIO to control entire circuit.And the material that adopts also is material commonly used, so cost is low, and also very practical.
Should be understood that application of the present invention is not limited to above-mentioned giving an example, for those of ordinary skills, can be improved according to the above description or conversion that all these improvement and conversion all should belong to the protection range of claims of the present invention.
Claims (8)
1. camera electrifying timing sequence control circuit, it is characterized in that, comprise a plurality of power modules and a plurality of bleeder circuit, each power module is output as the output of one road power supply, and power supply output in last road is by the enable signal of bleeder circuit dividing potential drop as back one road power module, when last road supply voltage rises to certain value, back one road power module enables, output voltage, wherein, the enable signal of first via power module is controlled by GPIO.
2. camera electrifying timing sequence control circuit according to claim 1 is characterized in that described power module is three, and bleeder circuit is two.
3. camera electrifying timing sequence control circuit according to claim 1 is characterized in that described power module is a low pressure difference linear voltage regulator.
4. camera electrifying timing sequence control circuit according to claim 1 is characterized in that described bleeder circuit comprises divider resistance.
5. camera electrifying timing sequence control circuit according to claim 2, it is characterized in that, described control circuit comprises: first low pressure difference linear voltage regulator, second low pressure difference linear voltage regulator, the 3rd low pressure difference linear voltage regulator, and described first low pressure difference linear voltage regulator is used to produce first via power supply; Described second low pressure difference linear voltage regulator is used to produce the second road power supply; Described the 3rd low pressure difference linear voltage regulator is used to produce the Third Road power supply, and described first via power supply is early than the second road power supply, and described the second road power supply is early than the Third Road power supply; Described circuit also comprises first divider resistance, second divider resistance, the 3rd divider resistance and the 4th divider resistance, wherein, described first divider resistance and second divider resistance are formed the bleeder circuit of first via power supply, will import the enable signal of second low pressure difference linear voltage regulator as the output of the second road power supply after the first via power supply dividing potential drop; Described the 3rd divider resistance and the 4th divider resistance are formed the bleeder circuit of the second road power supply, with input the 3rd low pressure difference linear voltage regulator after the output voltage dividing potential drop of the second road power supply, as the enable signal of Third Road power supply output.
6. camera electrifying timing sequence control circuit according to claim 5, it is characterized in that, the voltage input end of described first low pressure difference linear voltage regulator, second low pressure difference linear voltage regulator and the 3rd low pressure difference linear voltage regulator is connected to the output of battery respectively, wherein, the Enable Pin of described first low pressure difference linear voltage regulator connects a pin that is used to produce the GPIO controller of enable signal, when described pin was drawn high, first low pressure difference linear voltage regulator enabled; On the output of described first low pressure difference linear voltage regulator, also connect one first divider resistance, the other end of described first divider resistance connects the Enable Pin of second divider resistance and second low pressure difference linear voltage regulator, the other end ground connection of described second divider resistance; The output of described second low pressure difference linear voltage regulator connects the second road power supply and the 3rd divider resistance, the other end of described the 3rd divider resistance connects the Enable Pin and the 4th divider resistance of the 3rd low pressure difference linear voltage regulator, the other end ground connection of described the 4th divider resistance; The output of described the 3rd low pressure difference linear voltage regulator connects the Third Road power supply.
7. camera electrifying timing sequence control circuit according to claim 6, it is characterized in that, on the voltage input end of described first low pressure difference linear voltage regulator, second low pressure difference linear voltage regulator and the 3rd low pressure difference linear voltage regulator, also be connected with first direct-to-ground capacitance, the 3rd direct-to-ground capacitance and the 5th direct-to-ground capacitance respectively; On the voltage output end of described first low pressure difference linear voltage regulator, second low pressure difference linear voltage regulator and the 3rd low pressure difference linear voltage regulator, also be connected with second direct-to-ground capacitance, the 4th direct-to-ground capacitance and the 6th direct-to-ground capacitance respectively.
8. a mobile phone is characterized in that, is provided with the camera electrifying timing sequence control circuit described in any one of the claim 1 to 7 in described mobile phone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 201110108645 CN102202118B (en) | 2011-04-28 | 2011-04-28 | Power sequence control circuit on camera and mobile phone |
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| CN 201110108645 CN102202118B (en) | 2011-04-28 | 2011-04-28 | Power sequence control circuit on camera and mobile phone |
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| CN102202118A true CN102202118A (en) | 2011-09-28 |
| CN102202118B CN102202118B (en) | 2013-10-02 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102684615A (en) * | 2012-04-23 | 2012-09-19 | 烽火通信科技股份有限公司 | Driving device achieving ideal power up and power down timing sequence of power amplifier |
| CN103869856A (en) * | 2012-12-11 | 2014-06-18 | 中兴通讯股份有限公司 | Multi-voltage time sequence control circuit |
| CN106371334A (en) * | 2015-07-21 | 2017-02-01 | 深圳市奇辉电气有限公司 | Circuit for controlling power-on and power-off time sequences and power supply system |
| CN108205277A (en) * | 2016-12-20 | 2018-06-26 | 北京小米移动软件有限公司 | For electric installation |
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| CN101534330A (en) * | 2008-10-15 | 2009-09-16 | 闻泰集团有限公司 | Electrifying circuit on mobile terminal camera |
| CN201766650U (en) * | 2010-08-26 | 2011-03-16 | 北京思比科微电子技术股份有限公司 | Image sensor and system comprising same |
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| JP2008177755A (en) * | 2007-01-17 | 2008-07-31 | Rohm Co Ltd | Level shift circuit and semiconductor device using the same |
| KR20090048876A (en) * | 2007-11-12 | 2009-05-15 | 삼성디지털이미징 주식회사 | Apparatus of processing digital image |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102684615A (en) * | 2012-04-23 | 2012-09-19 | 烽火通信科技股份有限公司 | Driving device achieving ideal power up and power down timing sequence of power amplifier |
| CN102684615B (en) * | 2012-04-23 | 2015-04-08 | 烽火通信科技股份有限公司 | Driving device achieving ideal power up and power down timing sequence of power amplifier |
| CN103869856A (en) * | 2012-12-11 | 2014-06-18 | 中兴通讯股份有限公司 | Multi-voltage time sequence control circuit |
| CN103869856B (en) * | 2012-12-11 | 2015-12-23 | 中兴通讯股份有限公司 | A kind of multivoltage sequential control circuit |
| CN106371334A (en) * | 2015-07-21 | 2017-02-01 | 深圳市奇辉电气有限公司 | Circuit for controlling power-on and power-off time sequences and power supply system |
| CN106371334B (en) * | 2015-07-21 | 2019-03-01 | 深圳市奇辉电气有限公司 | A kind of Power-up/down time sequence control circuit and power-supply system |
| CN108205277A (en) * | 2016-12-20 | 2018-06-26 | 北京小米移动软件有限公司 | For electric installation |
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| Publication number | Publication date |
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| CN102202118B (en) | 2013-10-02 |
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Effective date of registration: 20201231 Address after: 221000 Daxin village, Mapo Town, Tongshan District, Xuzhou City, Jiangsu Province Patentee after: Jiangsu Guanyang flour Co.,Ltd. Address before: 510000 No. 106 Fengze East Road, Nansha District, Guangzhou City, Guangdong Province Patentee before: Guangzhou shengxia Intellectual Property Operation Co.,Ltd. Effective date of registration: 20201231 Address after: 510000 No. 106 Fengze East Road, Nansha District, Guangzhou City, Guangdong Province Patentee after: Guangzhou shengxia Intellectual Property Operation Co.,Ltd. Address before: 516006 Guangdong province Huizhou Zhongkai hi tech Development Zone No. 23 District Patentee before: HUIZHOU TCL MOBILE COMMUNICATION Co.,Ltd. |
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