CN102201378A - Insulation membrane structure of single grain sized semiconductor element - Google Patents
Insulation membrane structure of single grain sized semiconductor element Download PDFInfo
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- CN102201378A CN102201378A CN2011101200251A CN201110120025A CN102201378A CN 102201378 A CN102201378 A CN 102201378A CN 2011101200251 A CN2011101200251 A CN 2011101200251A CN 201110120025 A CN201110120025 A CN 201110120025A CN 102201378 A CN102201378 A CN 102201378A
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- semiconductor element
- crystal grain
- grain size
- size semiconductor
- insulation
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000009413 insulation Methods 0.000 title claims abstract description 24
- 239000012528 membrane Substances 0.000 title abstract 3
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000013078 crystal Substances 0.000 claims description 69
- 238000000576 coating method Methods 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 20
- 239000002861 polymer material Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 23
- 239000011247 coating layer Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 19
- 239000000758 substrate Substances 0.000 description 7
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 5
- 238000012536 packaging technology Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Abstract
An insulation membrane structure of a single grain sized semiconductor element is disclosed. The insulation membrane structure of a single grain sized semiconductor element comprises: a single grain sized semiconductor element, possessing a front side surface, a rear side surface, a left side surface, a right side surface, a bottom and an upper surface which consists of two metal pads; an insulating coating layer which covers on the front side surface, the rear side surface, the left side surface, the right side surface and the bottom. In the invention, a same reliability can be obtained, especially for small single grain sized semiconductor elements. The element can be protected from environment. Costs are saved and difficulty of the technology is reduced.
Description
The present invention is one and divides an application that the applying date of original application is: on 08 18th, 2008; Original applying number is: 200810144966.7; Former invention and created name is: single-crystal grain size semiconductor element insulating covered structure and technology thereof.
Technical field
The present invention relates to a kind of semiconductor element insulating covered structure and technology thereof, relate in particular to a kind of single-crystal grain size semiconductor element insulating covered structure and technology thereof.
Background technology
Semiconductor packages provides protection using integrated circuit, heat radiation, and function such as circuit turn-on; known technology removes the high-order encapsulation technology; as BGA Package (Ball Grid Array; BGA), Flip-Chip Using (Flip-Chip; FC), reach polycrystalline sheet module (Multi Chip Module; MCM), the most frequently used still leaded package mode, it is mainly sticking brilliant (Die Bond), bonding wire (Wired Bond), encapsulation (Molding), reaches lettering encapsulation processs such as (Marking).
As, TaiWan, China letters patent I 249208 " wafer-level packaging technology and wafer level dice size encapsulating structure " provides wafer, this wafer have first surface with respect to one of this first surface second surface and at least one Cutting Road; Form a plurality of blind holes on this first surface of this wafer, wherein this wafer has a plurality of first connection pads, and the position of each those blind hole corresponds respectively to one of them position of those first connection pads; In those blind holes, form a plurality of conductive poles, wherein an end of each described a plurality of conductive pole respectively with described one of them electric connection of a plurality of connection pads; The a plurality of glue frames of configuration on this first surface of this wafer; Substrate arrangement on described a plurality of glue frames, is wherein kept the gap by described a plurality of glue frames between this substrate and this wafer; And grind this wafer, to expose the other end of each described a plurality of conductive pole.Wherein, form a plurality of soldered balls on described a plurality of second connection pad; Form the reprovision line layer on this second surface of this wafer; Form a plurality of soldered balls on this reprovision line layer, and described a plurality of soldered ball is electrically connected to described a plurality of second connection pad via this reprovision line layer.
Yet above-mentioned known employing leaded package is utilized sticking crystalline substance, bonding wire, and encapsulation etc., makes packaging technology very complicated and expending time in to cause the cost raising.
Therefore, improving of the above-mentioned shortcoming of inventor's thoughts, and according to the correlation experience of being engaged in for many years in this respect, the concentrated observation and research, and cooperate the utilization of scientific principle and passive device technology, and propose a kind of reasonable in design and effectively improve the present invention of above-mentioned shortcoming.
Summary of the invention
Therefore the object of the present invention is to provide a kind of single-crystal grain size semiconductor element insulating covered structure and technology thereof, reach the purpose of simplifying technology and reducing cost.
According to above-mentioned purpose of the present invention, the present invention proposes a kind of single-crystal grain size semiconductor element insulating covered structure, comprise: single-crystal grain size semiconductor element, this single-crystal grain size semiconductor element has leading flank, trailing flank, left surface, right flank, bottom surface, reaches upper surface, and this upper surface of this single-crystal grain size semiconductor element has two metal gaskets; And insulation-coated layer, this insulation-coated layer is covered in this leading flank, this trailing flank, this left surface, this right flank, and this bottom surface of this single-crystal grain size semiconductor element.
In described single-crystal grain size semiconductor element insulating covered structure, this insulation-coated layer is the pbz polymer material at least.
In described single-crystal grain size semiconductor element insulating covered structure, the two ends of this single-crystal grain size semiconductor element also have termination electrode respectively, and this termination electrode is covered in this insulation-coated layer, reaches this metal gasket.
In described single-crystal grain size semiconductor element insulating covered structure, this termination electrode is argentiferous at least.
In described single-crystal grain size semiconductor element insulating covered structure, this termination electrode is cupric at least.
In described single-crystal grain size semiconductor element insulating covered structure, this termination electrode has electrodeposited coating, and this electrodeposited coating is coated on this termination electrode.
In described single-crystal grain size semiconductor element insulating covered structure, this electrodeposited coating is nickeliferous at least.
In described single-crystal grain size semiconductor element insulating covered structure, this electrodeposited coating is stanniferous at least.
The present invention also proposes a kind of single-crystal grain size semiconductor element insulating process for coating, comprises the following steps: at first to provide single-crystal grain size semiconductor element and tool; The upper surface of this single-crystal grain size semiconductor element is attached at this tool; Carry out insulation-coated technology then, together with this tool, and this single-crystal grain size semiconductor element be positioned over filming equipment, form insulation-coated layer on this single-crystal grain size semiconductor element, cover the upper surface of this single-crystal grain size semiconductor element by this tool, the upper surface definition metal lead wire zone (Metal Wire Area) of this single-crystal grain size semiconductor element, this metal lead wire zone forms two metal gaskets (Metal Pad); Then together with this tool, and this single-crystal grain size semiconductor element take out from this filming equipment, separate this tool and this single-crystal grain size semiconductor element subsequently; Two ends with this single-crystal grain size semiconductor element form conductive layer subsequently, and this conductive layer is covered in this insulation-coated layer, reaches these two metal gaskets; And at last with the two ends formation electrodeposited coating of this single-crystal grain size semiconductor element, this electrodeposited coating is coated on this conductive layer.
In described single-crystal grain size semiconductor element insulating process for coating, the high size of the length and width of this crystal grain size semiconductor element is about 0.6mm * 0.3mm * 0.5mm, 1.0mm * 0.5mm * 0.5mm or 1.6mm * 0.8mm * 0.5mm.
In described single-crystal grain size semiconductor element insulating process for coating, these two metal gaskets are in order to electrically connect with other substrates.
The present invention has following beneficial effect:
(1) utilizes the technology of passive device; can obtain identical reliability; but the semiconductor element that size is less; illustrate; the size of single crystal grain can be fabricated into 1.0mm * 0.5mm * 0.5mm easily; even 0.5mm * 0.25mm * 0.25mm, protect this single-crystal grain size semiconductor element not affected by environment, as other foreign matter influences such as aqueous vapor or dust.
(2) utilize passive device technology tool, and the design, not only oversimplify the semiconductor element packaging technology, and on this single-crystal grain size semiconductor element, form passive device termination electrode that adopts and the electrodeposited coating that possesses weld interface simultaneously, in order to electrically connect with other substrates, save the expense of accurate sealed in unit, and reduced the difficulty of technology.
In order to make narration of the present invention more detailed and complete, in the following summary of the invention, provide many different embodiment or example, can and cooperate graphicly with reference to following description, be used for understanding the application of the different characteristic in different embodiment.
Description of drawings
Fig. 1 is the method flow diagram of the embodiment of the invention.
Fig. 2 is the schematic perspective view of the single-crystal grain size semiconductor element of the embodiment of the invention.
Fig. 3 is the schematic perspective view that the single-crystal grain size semiconductor element of the embodiment of the invention is placed tool.
Fig. 4 is the technology generalized section () of the embodiment of the invention.
Fig. 5 is the technology generalized section (two) of the embodiment of the invention.
Fig. 6 is the technology generalized section (three) of the embodiment of the invention.
Fig. 7 is the technology generalized section (four) of the embodiment of the invention.
Wherein, description of reference numerals is as follows:
The S100-S112 process step
100 single-crystal grain size semiconductor elements
100a single-crystal grain size semiconductor element insulating covered structure
101 leading flanks
102 trailing flanks
103 left surfaces
104 right flanks
105 bottom surfaces
106 upper surfaces
106a metal lead wire zone
110 insulation-coated layers
120 metal gaskets
130 termination electrodes
140 electrodeposited coatings
200 tools
Embodiment
Please refer to shown in Figure 1, the invention provides a kind of single-crystal grain size semiconductor element packaging technology S100, comprise the following steps: process step S102, process step S104, process step S106, process step S108, process step S110 and process step 112.
Process step S102
Please refer to Fig. 2, single-crystal grain size semiconductor element 100 at first is provided, this single-crystal grain size semiconductor element 100 is a cube, this cube have six by leading flank 101, trailing flank 102, left surface 103, right flank 104, bottom surface 105, and upper surface 106 formed, the high size of these cubical length and width is about 0.6mm * 0.3mm * 0.5mm, 1.0mm * 0.5mm * 0.5mm or 1.6mm * 0.8mm * 0.5mm.
Please refer to Fig. 3, tool 200 is provided then, this tool 200 is designed voluntarily by the user.
Process step S104
This single-crystal grain size semiconductor element 100 is placed on this tool 200, made the upper surface 106 of this single-crystal grain size semiconductor element 100 be attached at this tool 200 upper surfaces.
Process step S106
Carry out insulation-coated technology then; together with this tool 200; and this single-crystal grain size semiconductor element 100 is positioned over the filming equipment (not shown); please refer to Fig. 4; form insulation-coated layer 110 on this single-crystal grain size semiconductor element 100; this insulation-coated layer 110 can be an organic polymer coating; silica; or polysilicon; this insulation-coated layer 110 is covered in the leading flank 101 of this single-crystal grain size semiconductor element 100; trailing flank 102; left surface 103; right flank 104; and bottom surface 105; the thickness of this insulation-coated layer 110 can be enough to protect this single-crystal grain size semiconductor element 100 between about 1 to 50 μ m.
Cover this upper surface 106 of this single-crystal grain size semiconductor element 100 by this tool 200, upper surface 106 definition of this single-crystal grain size semiconductor element 100 form metal lead wire zone (Metal Wire Area) 106a, please refer to Fig. 5, this metal lead wire zone 106a is before carrying out insulation-coated technology, this metal lead wire zone 106a has had two metal gaskets (Metal Pad) 120, these two metal gaskets 120 are in order to electrically connect with other substrates, the method that forms described a plurality of metal gasket 120 is a semiconductor technology technology commonly used, as semiconductor exposure development (Lithography), and metal etch (Metal Etching), not emphasis of the present invention, so not at this detailed description.
Process step S108
Then with this tool 200, and this single-crystal grain size semiconductor element 100 take out from this insulation-coated equipment together, separate this tool 200 and this single-crystal grain size semiconductor element 100 subsequently.
Process step S110
Please refer to Fig. 6, subsequently the two ends of this single-crystal grain size semiconductor element 100 are attached and carry out drying (drying) behind the elargol or solidify (curing) or burn attached (Firing) and handle, in order to form conductive layer, in the present embodiment, this conductive layer claims termination electrode 130 again, and this termination electrode 130 covers this insulation-coated layer 110 and described a plurality of metal gasket 120.
Process step S112
Please refer to Fig. 7, at last the two ends of this single-crystal grain size semiconductor element 100 are electroplated to form electrodeposited coating 140, this electrodeposited coating 140 comprises nickel, reaches tin, and this electrodeposited coating 140 is coated on this termination electrode 130, finishes single-crystal grain size semiconductor element insulating covered structure 100a.
Can reach following effect under the present invention and the known comparison:
(1) owing to do not use the leaded package (utilize sticking crystalline substance, bonding wire, encapsulate then) of general semiconductor element, and utilize the technology of passive device, can obtain identical reliability, but the less semiconductor element of size.The size of for example general passive device can be fabricated into 1.0mm * 0.5mm * 0.5mm easily, even 0.5mm * 0.25mm * 0.25mm, this be the known semiconductor packages pin can't reach easily.Utilize this insulation-coated layer 110, this termination electrode 130 and this electrodeposited coating 140, in order to protect the article coated 100a of this single-crystal grain size semiconductor element packaging insulating not affected by environment, as other foreign matter influences such as aqueous vapor or dust.
(2) utilize this tool 200 and design thereof; not only oversimplify semiconductor element packaging protection technology; and on this single-crystal grain size semiconductor element, form common termination electrode of passive device 130 and the electrodeposited coating 140 that possesses weld interface simultaneously, in order to electrically connect with other substrates.And needn't use the known leaded package of semiconductor industry (utilizing sticking crystalline substance, bonding wire, encapsulation then) to reach and other substrate electrically connects.Save the expense of accurate sealed in unit, and reduced the difficulty of technology.
Though the present invention discloses as above with preferred embodiment, right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention, can think easily and variation or modification, all can be encompassed in following claims scope of the present invention.
Claims (7)
1. a single-crystal grain size semiconductor element insulating covered structure is characterized in that, comprising:
Single-crystal grain size semiconductor element, this single-crystal grain size semiconductor element have leading flank, trailing flank, left surface, right flank, bottom surface, reach upper surface, and the upper surface of this single-crystal grain size semiconductor element has two metal gaskets; And
Insulation-coated layer, this insulation-coated layer is covered in leading flank, trailing flank, left surface, right flank, and the bottom surface of this single-crystal grain size semiconductor element, the two ends of this single-crystal grain size semiconductor element also have termination electrode respectively, this termination electrode is covered in this insulation-coated layer, and this metal gasket, makes this termination electrode be covered in leading flank, trailing flank, left surface, right flank, bottom surface, and the upper surface of this single-crystal grain size semiconductor element.
2. single-crystal grain size semiconductor element insulating covered structure as claimed in claim 1 is characterized in that, this insulation-coated layer is the pbz polymer material at least.
3. single-crystal grain size semiconductor element insulating covered structure as claimed in claim 1 is characterized in that this termination electrode is argentiferous at least.
4. single-crystal grain size semiconductor element insulating covered structure as claimed in claim 1 is characterized in that this termination electrode is cupric at least.
5. single-crystal grain size semiconductor element insulating covered structure as claimed in claim 1 is characterized in that this termination electrode has electrodeposited coating, and this electrodeposited coating is coated on this termination electrode.
6. single-crystal grain size semiconductor element insulating covered structure as claimed in claim 5 is characterized in that this electrodeposited coating is nickeliferous at least.
7. single-crystal grain size semiconductor element insulating covered structure as claimed in claim 5 is characterized in that this electrodeposited coating is stanniferous at least.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101200251A CN102201378A (en) | 2008-08-18 | 2008-08-18 | Insulation membrane structure of single grain sized semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101200251A CN102201378A (en) | 2008-08-18 | 2008-08-18 | Insulation membrane structure of single grain sized semiconductor element |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101449667A Division CN101656240B (en) | 2008-08-18 | 2008-08-18 | Single-crystal grain size semiconductor element insulating covering process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102201378A true CN102201378A (en) | 2011-09-28 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101200251A Pending CN102201378A (en) | 2008-08-18 | 2008-08-18 | Insulation membrane structure of single grain sized semiconductor element |
Country Status (1)
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|---|---|
| CN (1) | CN102201378A (en) |
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- 2008-08-18 CN CN2011101200251A patent/CN102201378A/en active Pending
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Application publication date: 20110928 |