CN102201373B - Manufacture method of SOI (silicon on insulator)-based electronic fuse line - Google Patents
Manufacture method of SOI (silicon on insulator)-based electronic fuse line Download PDFInfo
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- CN102201373B CN102201373B CN201110103147.XA CN201110103147A CN102201373B CN 102201373 B CN102201373 B CN 102201373B CN 201110103147 A CN201110103147 A CN 201110103147A CN 102201373 B CN102201373 B CN 102201373B
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Abstract
The invention provides a manufacture method of an SOI (silicon on insulator)-based electronic fuse line. The method comprises the following steps of: forming an active area and a monocrystalline silicon layer of an electronic fuse line are in one process; then forming an oxidation layer and an silicon nitride layer; and then removing the silicon nitride layer and the oxidation layer at the top of the electronic fuse line area and further removing the partial monocrystalline silicon layer of the electronic fuse line area so that the thickness of the monocrystalline silicon layer in the electronic fusing line area can be thinned selectively, thereby reducing the power consumed for fusing an electronic fuse line and improving the yield.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of manufacture method of the new fuse structure based on silicon-on-insulator.
Background technology
Utilize fuse to be common approach with the semiconductor device of stylize application-specific or client's needs, new fuse structure has the one compared with high usage in fuse.New fuse structure is formed by one deck monocrystalline silicon, and this monocrystalline silicon deposition is on a silicon substrate and through metal silication processing procedure.
Silicon-on-insulator substrate has been widely used in manufacture of semiconductor, introduces the method existing a kind of silicon base on insulator being formed new fuse structure below.
Please refer to shown in Fig. 1, silicon-on-insulator (SOI) wafer 100 generally includes active layer 110, insulating barrier 112 and substrate 114.Active layer 110 is the epitaxial layer that forms of one deck silicon, silicon germanium oxide, germanium or strained silicon normally.Insulating barrier 112 is also called buried oxide layer (buried oxide layer) usually, and its material can be silicon dioxide, is formed on the substrate 114 of silicon or glass material, and effect makes active layer 110 and substrate 114 electrical isolation.
Please refer to shown in Fig. 2, patterning active layer 110, SOI wafer is formed new fuse structure layer 210 and active area 212.
Please refer to shown in Fig. 3, form grid 310, described grid 310 comprises gate oxide 314 and single crystalline silicon gate electrode 316.
Please refer to shown in Fig. 4, form clearance wall (Spacer) 318, and form light dope regions and source/drain 320 in active area 212, the material of clearance wall 318 is silicon nitride.
Please refer to shown in Fig. 5, light dope source/drain region 320 and new fuse structure layer 210 carry out silicide process, namely first deposit one deck silicide and anneal again, form metal silicide layer 610.
The manufacture method of the new fuse structure of existing silicon-on-insulator, the electronic type fuse of formation comprises new fuse structure layer 210 and metal silicide layer 610, and the thickness of described new fuse structure equals the thickness of active area 212.
Summary of the invention
The present invention solves in prior art, and the new fuse structure thickness based on silicon-on-insulator is thicker, the technical problem that energy consumption is higher.
For reaching above-mentioned purpose of the present invention, the invention provides the manufacture method of the new fuse structure based on silicon-on-insulator, comprising step:
On insulator silicon base forms monocrystalline silicon layer, and monocrystalline silicon layer described in patterning, to be formed with source region and new fuse structure district;
Described active area and described new fuse structure district form oxide layer;
Form silicon nitride layer, described silicon nitride layer covers described active area and described new fuse structure district;
Remove silicon nitride layer and the oxide layer at top, described new fuse structure district;
Remove the portion of monocrystalline silicon layer in described new fuse structure district;
Remove remaining described silicon nitride layer and oxide layer, retain the monocrystalline silicon layer in described active area and described new fuse structure district;
Form grid in described active area, and with described grid for mask, carry out the low-doped ion implantation of source/drain region;
The monocrystalline silicon layer sidewall in the monocrystalline silicon layer sidewall in described gate lateral wall, described active area and described new fuse structure district forms clearance wall.
In the manufacture method of the described new fuse structure based on silicon-on-insulator, described oxide layer is silicon dioxide layer.
In the manufacture method of the described new fuse structure based on silicon-on-insulator, remove the silicon nitride layer at top, described new fuse structure district and the method for oxide layer is dry etching.
In the manufacture method of the described new fuse structure based on silicon-on-insulator, the method removing the monocrystalline silicon layer in the described new fuse structure district of part is plasma dry etch.
In the manufacture method of the described new fuse structure based on silicon-on-insulator, removing remaining described silicon nitride layer and oxide layer, retaining the monocrystalline silicon layer in described active area and described new fuse structure district for removing the remaining silicon nitride of silicon chip surface and silica respectively by optionally etching or corroding.
In the manufacture method of the described new fuse structure based on silicon-on-insulator, after removing the monocrystalline silicon layer (monocrystalline silicon) in the described new fuse structure district of part, the remaining monocrystalline silicon layer thickness range in described new fuse structure district is 100 dust-1500 dusts.
In the manufacture method of the described new fuse structure based on silicon-on-insulator, after forming clearance wall, also comprise and carry out metal silicide processing procedure, make the monocrystalline silicon layer in described new fuse structure district all form metal silicide layer.
The monocrystalline silicon layer in active area and new fuse structure district is formed in a procedure, then oxide layer and silicon nitride layer is formed, by removing silicon nitride layer and the oxide layer at top, electronics fuse district, and remove the portion of monocrystalline silicon layer in new fuse structure district further, to reach thinning new fuse structure thickness, can obtain the new fuse structure of the lower thickness be made up of simple material, the thickness of described new fuse structure can control as required; In addition, because fuse is monocrystal material, the distribution of resistance before and after its fusing also can be relatively good, thus effectively can improve Programming Window sequencing window.
Accompanying drawing explanation
Fig. 1-Fig. 5 is the structural representation of prior art based on each step of manufacture method of the new fuse structure of silicon-on-insulator.
Fig. 6-Figure 12 is the structural representation of the embodiment of the present invention based on each step of manufacture method of the new fuse structure of silicon-on-insulator.
Embodiment
Below with reference to accompanying drawing, the manufacture method of the new fuse structure of silicon-on-insulator of the present invention is described in further detail.
Core concept of the present invention is, based on silicon-on-insulator substrate, the monocrystalline silicon layer in active area and new fuse structure district is formed in a procedure, then oxide layer and silicon nitride layer is formed, by removing silicon nitride layer and the oxide layer at top, electronics fuse district, and remove the portion of monocrystalline silicon layer in new fuse structure district further, to reach thinning new fuse structure thickness, thus reduce the object of the power consumption of fusing new fuse structure.
The invention provides the manufacture method of the new fuse structure based on silicon-on-insulator, comprise step:
Please refer to shown in Fig. 6, on insulator silicon base 10 forms monocrystalline silicon layer, and monocrystalline silicon layer described in patterning, to be formed with source region 12A and new fuse structure district 12B; Forming the method for described monocrystalline silicon layer, can be the method for any one formation monocrystalline silicon layer of the prior art, as epitaxy.
Please refer to shown in Fig. 7, described active area 12A and described new fuse structure district 12B form oxide layer 14; In the present embodiment, described oxide layer 14 is silicon dioxide layer, and its formation method is the formation method of prior art, as chemical vapour deposition technique.The existence of oxide layer is to prevent the stress of silicon nitride too large and as the etch stop layer of silicon nitride etch.
Shown in Fig. 7, form silicon nitride layer 16, described silicon nitride layer 16 covers described active area 12A and described new fuse structure district 12B;
Please refer to shown in Fig. 8, remove silicon nitride layer 16 and the oxide layer 14 at 12B top, described new fuse structure district; Dry etching is in the present embodiment that existing dry etch process no longer describes at this.
Please refer to shown in Fig. 9, remove the portion of monocrystalline silicon layer of described new fuse structure district 12B; In the present embodiment, the method removing the portion of monocrystalline silicon layer of described new fuse structure district 12B is plasma dry etch; The remaining monocrystalline silicon layer thickness range in described new fuse structure district is 100 dust-1500 dusts.
Please refer to shown in Figure 10, remove remaining described silicon nitride layer 16 and oxide layer 14, retain the monocrystalline silicon layer of described active area 12A and described new fuse structure district 12B; The monocrystalline silicon layer and new fuse structure that described in the remaining silicon nitride of silicon chip surface and silica, new fuse structure district 12B retains is removed respectively by optionally etching or corroding.
Please refer to shown in Figure 11, form grid 20 at described active area 12A, and with described grid 20 for mask, carry out the low-doped ion implantation of source/drain region, as utilized nitrogen, arsenic, antimony, boron, aluminium or gallium etc. to adulterate, this step can be any one of existing low-doped ion implantation technology.
The monocrystalline silicon layer sidewall in the monocrystalline silicon layer sidewall in described gate lateral wall, described active area and described new fuse structure district forms clearance wall 30.The material of clearance wall 30 can be silicon nitride (conventional is silica or ONO structure now), and utilize methane and ammonia as reacting gas, at the temperature of about 300 degree to 800 degree, reaction generates, and thickness is approximately 300 dust-1000 dusts.
The advantage of above-described embodiment is: the new fuse structure that can obtain the lower thickness be made up of pure crystalline silicon, and the thickness of described new fuse structure can control as required; In addition, in addition, because fuse is monocrystal material, the distribution of resistance before and after its fusing also can be relatively good, thus effectively can improve ProgrammingWindow sequencing window, is more conducive to improve yield.
Optionally, in another embodiment of the invention, after formation clearance wall 30, also comprise and carry out metal silicide processing procedure, make the monocrystalline silicon layer in described new fuse structure district all form metal silicide layer.Metal silicide make can be existing formation metal silicide processing procedure in any one.Metal in metal silicide can be cobalt, copper, molybdenum, titanium or tantalum etc., in the present embodiment, described new fuse structure is made up of metal silicide completely, and compared with new fuse structure in prior art is made up of bi-material, the stylizing of new fuse structure of pure material layer more easily controls.Control easily owing to stylizing, so, there is higher reliability.Certainly in other examples of the present invention, new fuse structure also can be double-decker (when fuse layer thickness is not very thin), or also directly can form the silicide layer of complete silication when the monocrystalline silicon layer of fuse is very thin.
Claims (7)
1. based on the manufacture method of the new fuse structure of silicon-on-insulator, it is characterized in that, comprise step:
On insulator silicon base forms monocrystalline silicon layer, and monocrystalline silicon layer described in patterning, to be formed with source region and new fuse structure district;
Described active area and described new fuse structure district form oxide layer;
Form silicon nitride layer, described silicon nitride layer covers described active area and described new fuse structure district;
Remove silicon nitride layer and the oxide layer at top, described new fuse structure district;
Remove the portion of monocrystalline silicon layer in described new fuse structure district;
Remove remaining described silicon nitride layer and oxide layer, retain the monocrystalline silicon layer in described active area and described new fuse structure district;
Form grid in described active area, and with described grid for mask, carry out the low-doped ion implantation of source/drain region;
The monocrystalline silicon layer sidewall in the monocrystalline silicon layer sidewall in described gate lateral wall, described active area and described new fuse structure district forms clearance wall.
2., as claimed in claim 1 based on the manufacture method of the new fuse structure of silicon-on-insulator, it is characterized in that, described oxide layer is silicon dioxide layer.
3. as claimed in claim 1 based on the manufacture method of the new fuse structure of silicon-on-insulator, it is characterized in that, remove the silicon nitride layer at top, described new fuse structure district and the method for oxide layer is dry etching.
4. as claimed in claim 1 based on the manufacture method of the new fuse structure of silicon-on-insulator, it is characterized in that, the method removing the monocrystalline silicon layer in the described new fuse structure district of part is plasma dry etch.
5. as claimed in claim 1 based on the manufacture method of the new fuse structure of silicon-on-insulator, it is characterized in that, removing remaining described silicon nitride layer and oxide layer, retaining the monocrystalline silicon layer in described active area and described new fuse structure district for removing the remaining silicon nitride of silicon chip surface and silica respectively by optionally etching.
6. as claimed in claim 1 based on the manufacture method of the new fuse structure of silicon-on-insulator, it is characterized in that, after removing the monocrystalline silicon layer in the described new fuse structure district of part, the remaining monocrystalline silicon layer thickness range in described new fuse structure district is 100 dust-1500 dusts.
7. as claimed in claim 1 based on the manufacture method of the new fuse structure of silicon-on-insulator, it is characterized in that, after forming clearance wall, also comprise and carry out metal silicide processing procedure, make the monocrystalline silicon layer in described new fuse structure district all form metal silicide layer.
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| CN201110103147.XA CN102201373B (en) | 2011-04-25 | 2011-04-25 | Manufacture method of SOI (silicon on insulator)-based electronic fuse line |
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| CN201110103147.XA CN102201373B (en) | 2011-04-25 | 2011-04-25 | Manufacture method of SOI (silicon on insulator)-based electronic fuse line |
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| CN102201373A CN102201373A (en) | 2011-09-28 |
| CN102201373B true CN102201373B (en) | 2015-04-01 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130092A (en) * | 2010-01-20 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Fuse device and preparation method thereof |
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| JPH0738413B2 (en) * | 1984-10-31 | 1995-04-26 | 富士通株式会社 | Semiconductor device |
| US6597013B2 (en) * | 2001-08-06 | 2003-07-22 | Texas Instruments Incorporated | Low current blow trim fuse |
| US7067359B2 (en) * | 2004-03-26 | 2006-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating an electrical fuse for silicon-on-insulator devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102130092A (en) * | 2010-01-20 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Fuse device and preparation method thereof |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140428 |
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