CN102201373A - Manufacture method of SOI (silicon on insulator)-based electronic fuse line - Google Patents
Manufacture method of SOI (silicon on insulator)-based electronic fuse line Download PDFInfo
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- CN102201373A CN102201373A CN201110103147XA CN201110103147A CN102201373A CN 102201373 A CN102201373 A CN 102201373A CN 201110103147X A CN201110103147X A CN 201110103147XA CN 201110103147 A CN201110103147 A CN 201110103147A CN 102201373 A CN102201373 A CN 102201373A
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Abstract
The invention provides a manufacture method of an SOI (silicon on insulator)-based electronic fuse line. The method comprises the following steps of: forming an active area and a monocrystalline silicon layer of an electronic fuse line are in one process; then forming an oxidation layer and an silicon nitride layer; and then removing the silicon nitride layer and the oxidation layer at the top of the electronic fuse line area and further removing the partial monocrystalline silicon layer of the electronic fuse line area so that the thickness of the monocrystalline silicon layer in the electronic fusing line area can be thinned selectively, thereby reducing the power consumed for fusing an electronic fuse line and improving the yield.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of manufacture method of the new fuse structure based on silicon-on-insulator.
Background technology
Utilizing fuse has been common means with the semiconductor device that stylize application-specific or client need, and new fuse structure is that a kind of than high usage arranged in the fuse.New fuse structure is formed by one deck monocrystalline silicon, and this monocrystalline silicon is deposited on the silicon base and process metal silication processing procedure.
The silicon-on-insulator substrate has been widely used in the manufacture of semiconductor, introduces existing a kind of method that forms new fuse structure in the silicon-on-insulator substrate below.
Please refer to shown in Figure 1ly, silicon-on-insulator (SOI) wafer 100 generally includes active layer 110, insulating barrier 112 and substrate 114.Active layer 110 is one deck silicon, silicon germanium oxide, germanium or epitaxial layer that strained silicon constituted normally.Insulating barrier 112 is called again usually imbeds oxide layer (buried oxide layer), and its material can be a silicon dioxide, is formed on the substrate 114 of silicon or glass material, and effect is to make active layer 110 and substrate 114 electrical isolation.
Please refer to shown in Figure 2ly, patterning active layer 110 forms new fuse structure layer 210 and active area 212 on the SOI wafer.
Please refer to shown in Figure 3ly, form grid 310, described grid 310 comprises gate oxide 314 and single crystalline silicon gate electrode 316.
Please refer to shown in Figure 4ly, form clearance wall (Spacer) 318, and form light dope source electrode/drain regions 320 at active area 212, the material of clearance wall 318 is a silicon nitride.
Please refer to shown in Figure 5ly, carry out the silicide processing procedure on lightly-doped source/drain region 320 and new fuse structure layer 210, promptly deposition one deck silicide is annealed again earlier, forms metal silicide layer 610.
The manufacture method of the new fuse structure of existing silicon-on-insulator, the electronic type fuse of formation comprises new fuse structure layer 210 and metal silicide layer 610, the thickness of described new fuse structure equals the thickness of active area 212.
Summary of the invention
The present invention solves in the prior art, and is thicker based on the new fuse structure thickness of silicon-on-insulator, the energy consumption technical problems of high.
For reaching above-mentioned purpose of the present invention, the invention provides manufacture method based on the new fuse structure of silicon-on-insulator, comprise step:
In the silicon-on-insulator substrate, form monocrystalline silicon layer, and the described monocrystalline silicon layer of patterning, to be formed with source region and new fuse structure district;
In described active area and described new fuse structure district, form oxide layer;
Form silicon nitride layer, described silicon nitride layer covers described active area and described new fuse structure district;
Remove the silicon nitride layer and the oxide layer at top, described new fuse structure district;
Remove the part monocrystalline silicon layer in described new fuse structure district;
Remove remaining described silicon nitride layer and oxide layer, keep the monocrystalline silicon layer in described active area and described new fuse structure district;
Form grid at described active area, and be mask with described grid, the low-doped ion that carries out source/drain region injects;
Form clearance wall at the monocrystalline silicon layer sidewall of described gate lateral wall, described active area and the monocrystalline silicon layer sidewall in described new fuse structure district.
In the manufacture method of described new fuse structure based on silicon-on-insulator, described oxide layer is a silicon dioxide layer.
In the manufacture method of described new fuse structure based on silicon-on-insulator, removing the silicon nitride layer at top, described new fuse structure district and the method for oxide layer is dry etching.
In the manufacture method of described new fuse structure based on silicon-on-insulator, the method for removing the monocrystalline silicon layer in the described new fuse structure of part district is the plasma dry etching.
In the manufacture method of described new fuse structure based on silicon-on-insulator, remove remaining described silicon nitride layer and oxide layer, the monocrystalline silicon layer that keeps described active area and described new fuse structure district is by optionally silicon chip surface residual silicon nitride and silica are removed in etching or corrosion respectively.
In the manufacture method of described new fuse structure based on silicon-on-insulator, remove the monocrystalline silicon layer (monocrystalline silicon) in the described new fuse structure of part district after, the remaining monocrystalline silicon layer thickness range in described new fuse structure district is 100 dusts-1500 dusts.
In the manufacture method of described new fuse structure based on silicon-on-insulator, form after the clearance wall, also comprise and carry out the metal silicide processing procedure, make the monocrystalline silicon layer in described new fuse structure district all form metal silicide layer.
The monocrystalline silicon layer in active area and new fuse structure district is formed in one procedure, form oxide layer and silicon nitride layer then, by removing the silicon nitride layer and the oxide layer at top, electronics fuse district, and further remove the part monocrystalline silicon layer in new fuse structure district, to reach attenuate new fuse structure thickness, can access the new fuse structure of being made up of simple material than minimal thickness, the thickness of described new fuse structure can be controlled as required; In addition, because fuse is a monocrystal material, the distribution of resistance before and after its fusing also can be relatively good, thereby can improve Programming Window sequencing window effectively.
Description of drawings
Fig. 1-Fig. 5 is the structural representation of prior art based on each step of manufacture method of the new fuse structure of silicon-on-insulator.
Fig. 6-Figure 12 is the structural representation of the embodiment of the invention based on each step of manufacture method of the new fuse structure of silicon-on-insulator.
Embodiment
Below with reference to accompanying drawing, the manufacture method of the new fuse structure of silicon-on-insulator of the present invention is described in further detail.
Core concept of the present invention is, based on the silicon-on-insulator substrate, the monocrystalline silicon layer in active area and new fuse structure district is formed in one procedure, form oxide layer and silicon nitride layer then, by removing the silicon nitride layer and the oxide layer at top, electronics fuse district, and further remove the part monocrystalline silicon layer in new fuse structure district, and to reach attenuate new fuse structure thickness, the purpose of the power consumption of new fuse structure thereby reduction fuses.
The invention provides manufacture method, comprise step based on the new fuse structure of silicon-on-insulator:
Please refer to shown in Figure 6ly, in silicon-on-insulator substrate 10, form monocrystalline silicon layer, and the described monocrystalline silicon layer of patterning, to be formed with source region 12A and new fuse structure district 12B; Forming the method for described monocrystalline silicon layer, can be that of the prior art any one forms the method for monocrystalline silicon layer, as epitaxy.
Please refer to shown in Figure 7ly, on described active area 12A and described new fuse structure district 12B, form oxide layer 14; In the present embodiment, described oxide layer 14 is a silicon dioxide layer, and the formation method that its formation method is a prior art is as chemical vapour deposition technique.The existence of oxide layer is to lose layer too greatly and as ending of silicon nitride etch for the stress that prevents silicon nitride.
Please continue to form silicon nitride layer 16 with reference to shown in Figure 7, described silicon nitride layer 16 covers described active area 12A and described new fuse structure district 12B;
Please refer to shown in Figure 8ly, remove the silicon nitride layer 16 and the oxide layer 14 at 12B top, described new fuse structure district; Dry etching is that existing dry etch process is no longer described at this in the present embodiment.
Please refer to shown in Figure 9ly, remove the part monocrystalline silicon layer of described new fuse structure district 12B; In the present embodiment, the method for removing the part monocrystalline silicon layer of described new fuse structure district 12B is the plasma dry etching; The remaining monocrystalline silicon layer thickness range in described new fuse structure district is 100 dusts-1500 dusts.
Please refer to shown in Figure 10ly, remove remaining described silicon nitride layer 16 and oxide layer 14, keep the monocrystalline silicon layer of described active area 12A and described new fuse structure district 12B; Removing the monocrystalline silicon layer that silicon chip surface residual silicon nitride and the described new fuse structure of silica district 12B keep respectively by etching optionally or corrosion is new fuse structure.
Please refer to shown in Figure 11, form grid 20 at described active area 12A, and be mask with described grid 20, the low-doped ion that carries out source/drain region injects, as utilize nitrogen, arsenic, antimony, boron, aluminium or gallium etc. to mix, this step can be any one of existing low-doped ion implantation technology.
Form clearance wall 30 at the monocrystalline silicon layer sidewall of described gate lateral wall, described active area and the monocrystalline silicon layer sidewall in described new fuse structure district.The material of clearance wall 30 can be silicon nitride (now commonly used be silica or ONO structure), utilizes methane and ammonia as reacting gas, generates in the reaction to the temperature of 800 degree of about 300 degree, and thickness is approximately 300 dusts-1000 dust.
The advantage of the foregoing description is: can access the new fuse structure of being made up of pure crystalline silicon than minimal thickness, the thickness of described new fuse structure can be controlled as required; In addition, in addition, because fuse is a monocrystal material, the distribution of resistance before and after its fusing also can be relatively good, thereby can improve ProgrammingWindow sequencing window effectively, is more conducive to improve yield.
Optionally, in another embodiment of the present invention, after forming clearance wall 30, also comprise and carry out the metal silicide processing procedure, make the monocrystalline silicon layer in described new fuse structure district all form metal silicide layer.It can be in the processing procedure of existing formation metal silicide any one that metal silicide is made.Metal in the metal silicide can be cobalt, copper, molybdenum, titanium or tantalum etc., in the present embodiment, described new fuse structure is made up of metal silicide fully, is made up of two kinds of materials with new fuse structure in the prior art and compares the easier control that stylizes of the new fuse structure of pure material layer.Control is easy owing to stylize, so, higher reliability is arranged.Certainly new fuse structure also can be double-decker (when fuse layer thickness when not being very thin) in other examples of the present invention, directly forms the silicide layer of complete silication when perhaps also can be at the monocrystalline silicon layer of fuse very thin.
Claims (7)
1. based on the manufacture method of the new fuse structure of silicon-on-insulator, it is characterized in that, comprise step:
In the silicon-on-insulator substrate, form monocrystalline silicon layer, and the described monocrystalline silicon layer of patterning, to be formed with source region and new fuse structure district;
In described active area and described new fuse structure district, form oxide layer;
Form silicon nitride layer, described silicon nitride layer covers described active area and described new fuse structure district;
Remove the silicon nitride layer and the oxide layer at top, described new fuse structure district;
Remove the part monocrystalline silicon layer in described new fuse structure district;
Remove remaining described silicon nitride layer and oxide layer, keep the monocrystalline silicon layer in described active area and described new fuse structure district;
Form grid at described active area, and be mask with described grid, the low-doped ion that carries out source/drain region injects;
Form clearance wall at the monocrystalline silicon layer sidewall of described gate lateral wall, described active area and the monocrystalline silicon layer sidewall in described new fuse structure district.
2. the manufacture method of the new fuse structure based on silicon-on-insulator as claimed in claim 1 is characterized in that described oxide layer is a silicon dioxide layer.
3. the manufacture method of the new fuse structure based on silicon-on-insulator as claimed in claim 1 is characterized in that removing the silicon nitride layer at top, described new fuse structure district and the method for oxide layer is dry etching.
4. the manufacture method of the new fuse structure based on silicon-on-insulator as claimed in claim 1 is characterized in that, the method for removing the monocrystalline silicon layer in the described new fuse structure of part district is the plasma dry etching.
5. the manufacture method of the new fuse structure based on silicon-on-insulator as claimed in claim 1, it is characterized in that, remove remaining described silicon nitride layer and oxide layer, the monocrystalline silicon layer that keeps described active area and described new fuse structure district is by optionally silicon chip surface residual silicon nitride and silica are removed in etching or corrosion respectively.
6. the manufacture method of the new fuse structure based on silicon-on-insulator as claimed in claim 1 is characterized in that, remove the monocrystalline silicon layer in the described new fuse structure of part district after, the remaining monocrystalline silicon layer thickness range in described new fuse structure district is 100 dusts-1500 dusts.
7. the manufacture method of the new fuse structure based on silicon-on-insulator as claimed in claim 1 is characterized in that, forms after the clearance wall, also comprises and carries out the metal silicide processing procedure, makes the monocrystalline silicon layer in described new fuse structure district all form metal silicide layer.
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| CN201110103147.XA CN102201373B (en) | 2011-04-25 | 2011-04-25 | Manufacture method of SOI (silicon on insulator)-based electronic fuse line |
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| CN201110103147.XA CN102201373B (en) | 2011-04-25 | 2011-04-25 | Manufacture method of SOI (silicon on insulator)-based electronic fuse line |
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| CN102201373B CN102201373B (en) | 2015-04-01 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61107742A (en) * | 1984-10-31 | 1986-05-26 | Fujitsu Ltd | Semiconductor device |
| US20040017674A1 (en) * | 2001-08-06 | 2004-01-29 | Romas Gregory G. | Low current blow trim fuse |
| US20050214982A1 (en) * | 2004-03-26 | 2005-09-29 | Chi-Hsi Wu | Electrical fuse for silicon-on-insulator devices |
| CN102130092A (en) * | 2010-01-20 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Fuse device and preparation method thereof |
-
2011
- 2011-04-25 CN CN201110103147.XA patent/CN102201373B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61107742A (en) * | 1984-10-31 | 1986-05-26 | Fujitsu Ltd | Semiconductor device |
| US20040017674A1 (en) * | 2001-08-06 | 2004-01-29 | Romas Gregory G. | Low current blow trim fuse |
| US20050214982A1 (en) * | 2004-03-26 | 2005-09-29 | Chi-Hsi Wu | Electrical fuse for silicon-on-insulator devices |
| CN102130092A (en) * | 2010-01-20 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Fuse device and preparation method thereof |
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