CN102195469B - Line voltage compensation circuit based on peak detection current mode switch circuit - Google Patents

Abstract

The invention relates to a line voltage compensation circuit based on peak detection current mode switch circuit. The line voltage compensation circuit provided by the invention comprises a sample circuit and a compensation circuit, wherein, the sample circuit is used for sampling voltages related with the line voltage, thus obtaining sampling voltages which are in linear relation with the line voltage and scaling down in proportion. The compensation circuit is connected with the sample circuit and is used for compensating the non-inverting input end or inverted input end of a comparator in the peak detection circuit by utilizing the sampling voltage of the output by the sample circuit in an electrical signal mode, so that the inductance peak point current is equal to the inductance peak point current under the ideal situation. The line voltage compensation circuit provided by the invention not only has the advantages of steady loop and quick reaction speed and the like in the traditional peak detection current mode switch control circuit, but also can be used for overcoming the problem of unstable inductance peak point current caused by system delay, so that the inductance peak point current is invariant. The line voltage compensation circuit provided by the invention can be widely applied to analogue integrated circuits.

Description

Line voltage compensation circuit based on Peak-detecting current type switching circuit

Technical field

The present invention relates to analog integrated circuit, relate in particular to Peak-detecting current type switching circuit.

Background technology

Peak-detecting current type switch control mode is a kind of method that current peak is controlled commonly used in power-supply system, and basic principle is that to detect in real time the inductive current value and then control inductive current peak by the comparator in Peak-detecting current type switching circuit be a steady state value.

Fig. 1 is that conventional peak detects current mode switch control circuit structure chart.The loop structure of this Peak-detecting current type ON-OFF control circuit is simple, need not to carry out loop compensation, and whole loop is more stable, and response speed is also very fast.

In Fig. 1, some light-emitting diode magnitudes of voltage are VC, when power tube MP conducting, power supply VIN is through these some light-emitting diodes, inductance L, power tube MP and detect resistance R set to this inductance L charging, until resistance R set both end voltage (being VCS voltage) greater than comparator C MP in-phase end input voltage VREF after, comparator C MP output low level signal, this low level signal is by control logic and drive circuit switch-off power pipe MP, after this inductance L begins the discharge by diode Diode, and the electric current of the resistance R of then flowing through est reduces to zero.After this, power tube MP reopens under control signal Vctl controls again, and inductance L begins charging, so repeatedly, thereby produces the switching signal Ton with supply voltage VIN variable duty ratio at comparator C MP output.

Ideally, the current peak Ipk0 of the inductance L of flowing through is only decided by reference voltage VREF0 and resistance R set, and its value is

$\mathrm{<figure-callout\; id="0"\; label="Ipk"\; filenames="HSA00000059490700021.png,HSA00000059490700022.png"\; state="\{\{state\}\}">Ipk</figure-callout>}0=\frac{\mathrm{VIN}-\mathrm{VC}}{L}\mathrm{Ton}=\frac{\mathrm{<figure-callout\; id="0"\; label="VREF"\; filenames="HSA00000059490700021.png,HSA00000059490700022.png"\; state="\{\{state\}\}">VREF</figure-callout>}0}{\mathrm{Rset}}---\left(1\right)$

In side circuit, close set time Td of total existence from comparator C MP output Ton signal to power tube MP and postpone, directly cause the actual inductance peak current Ipk that obtains to surpass ideally peak current Ipk0.

The actual peak current that obtains is

$\mathrm{Ipk}=\frac{\mathrm{VIN}-\mathrm{VC}}{L}(\mathrm{Ton}+\mathrm{Td})=\mathrm{<figure-callout\; id="0"\; label="Ipk"\; filenames="HSA00000059490700021.png,HSA00000059490700022.png"\; state="\{\{state\}\}">Ipk</figure-callout>}0+\frac{\mathrm{VIN}-\mathrm{VC}}{L}\mathrm{Td}=\frac{\mathrm{<figure-callout\; id="0"\; label="VREF"\; filenames="HSA00000059490700021.png,HSA00000059490700022.png"\; state="\{\{state\}\}">VREF</figure-callout>}0}{\mathrm{Rset}}+\frac{\mathrm{VIN}-\mathrm{VC}}{L}\mathrm{Td}---\left(2\right)$

By formula (2) as can be known, the actual inductance peak current Ipk that obtains is with the input voltage VIN linear change, therefore, although conventional peak detects the current mode switch circuit and has certain advantage, but detect the inherent delay of current mode switch Circuits System due to conventional peak, the inductance peak current can't become steady state value truly, and the inductance peak current is higher than ideally

And can change along with supply voltage VIN.

Summary of the invention

The invention provides a kind of line voltage compensation circuit based on Peak-detecting current type switching circuit that can overcome the above problems.

In first aspect, the invention provides a kind of line voltage compensation circuit based on peak detection circuit.This peak detection circuit comprises switching circuit, the 7th resistance, inductance, and this peak detection circuit charges to this inductance by line voltage and through this switching circuit, the 7th resistance, and by comparator this resistance both end voltage relatively, control end to this induction charging by the unlatching of controlling this switching circuit, in order to control the peak current of this inductance.And should comprise sample circuit and compensating circuit based on the line voltage compensation circuit of peak detection circuit.

This sample circuit is used for the sampling voltage relevant to this line voltage, thereby obtains and proportional sampling voltage of dwindling linear with this line voltage.This compensating circuit is connected with this sample circuit, be used for and compensated to this peak detection circuit comparator in-phase input end or inverting input by the sampling voltage of this sample circuit output mode with the signal of telecommunication, so that this inductance peak current is close to ideally inductance peak current.

In one embodiment of the invention, sample circuit comprises the first resistance, the second resistance, and this first resistance, the second resistance connects mutually, and with this tie point as this sample circuit output, in order to be connected with this compensating circuit by this output.

In another embodiment of the present invention, compensating circuit comprises the first amplifier, the 3rd resistance, the first current mirror, the second current mirror, the second amplifier, the 5th transistor, the 4th resistance, the 5th resistance, the 6th resistance.This first current mirror comprises the first branch road and the second branch road, and the second current mirror comprises the 3rd branch road and the 4th branch road, and the 3rd resistance is on this first branch road.

This first amplifier in-phase input end is connected with the 3rd resistance, and this first amplifier out is connected to this first branch road, and this second branch road is connected with the 3rd branch road.This second amplifier inverting input is reference voltage, and in-phase input end is connected to the 4th resistance, and output is connected with the 5th transistor gate.The 5th transistor, the 4th resistance, the 5th resistance, the 6th resistance series connection, and export the 4th branch road to the 4th resistance, the 5th resistance tie point, and with the 5th resistance, the 6th resistance tie point as comparator in-phase input end in this peak detection circuit.

In yet another embodiment of the present invention, this compensating circuit comprises the first amplifier, the 3rd resistance, the first current mirror, the second amplifier, the 5th transistor, the 4th resistance, the 6th resistance.And this first current mirror comprises the first branch road and the second branch road, and the 3rd resistance is on this first branch road.

This first amplifier in-phase input end is connected with the 3rd resistance, and this first amplifier out is connected to this first branch road, and this second branch road is connected to the 7th resistance in this peak detection circuit.This second amplifier inverting input is reference voltage, and in-phase input end is connected to the 4th resistance, and output is connected with the 5th transistor gate.The 5th transistor, the 4th resistance, the 6th resistance series connection, and with the 4th resistance, the 6th resistance tie point as comparator in-phase input end in this peak detection circuit.

The present invention has solved by sample circuit, compensating circuit the unsettled problem of inductance peak current that in the conventional method, Time Delay of Systems brings.The present invention has not only inherited conventional peak and has detected the advantages such as current mode switch control circuit loop stability, response speed be fast, and has overcome the inductance peak current instability problem that is brought by time-delay that himself exists, and makes the inductance peak current invariable.

Description of drawings

Below with reference to accompanying drawings specific embodiments of the present invention is described in detail, in the accompanying drawings:

Fig. 1 is that conventional peak detects current mode switch control circuit structural representation;

Fig. 2 is line voltage compensation circuit structure block diagram;

Fig. 3 is the line voltage compensation circuit diagram of one embodiment of the invention;

Fig. 4 is comparator C MP both end voltage contrast figure;

Fig. 5 is the line voltage compensation circuit diagram of another embodiment of the present invention;

Fig. 6 is the line voltage compensation circuit diagram of another embodiment of the present invention;

Fig. 7 is the also line voltage compensation circuit diagram of an embodiment of the present invention.

Embodiment

Fig. 2 is line voltage compensation circuit structure block diagram.This line voltage compensation circuit 200 comprises sample circuit 210, compensating circuit 220.

Sample circuit 210 is used for sampling and the proportional voltage of line voltage VIN, thereby obtains and proportional sampling voltage of dwindling linear with this line voltage VIN.

Compensating circuit 220 is connected with sample circuit 210, is used for being compensated to peak detection circuit 230 by the sampling voltage of the sample circuit 210 outputs mode with the signal of telecommunication, so that the inductance peak current equals ideally inductance peak current IPK0.In one embodiment of the invention, compensating circuit 220 is used for and will converts sampling current to by the sampling voltage of sample circuit 210 outputs, and the mode of this sampling current with voltage compensated to peak detection circuit 230.In another embodiment of the present invention, compensating circuit 220 is used for and will be directly compensated to peak detection circuit 230 in the mode of voltage by the sampling voltage of sample circuit 210 outputs.

Fig. 3 is the line voltage compensation circuit diagram of one embodiment of the invention.In Fig. 3, sample circuit 210 comprises resistance R 1, R2, resistance R 1, R2 series connection, and resistance R 1 one ends are connected in peak detection circuit 230 some light-emitting diodes and its magnitude of voltage is VC, the other end is connected to the amplifier EA1 end of oppisite phase (a point) in compensating circuit 220, and a point voltage is

$\mathrm{Va}=(\mathrm{VIN}-\mathrm{VC})\&times;\frac{R2}{R1+R2}---\left(3\right)$

Compensating circuit 220 comprises amplifier EA1, resistance R 3, transistor M1, M2, M3, M4, amplifier EA2, transistor M5, resistance R 4, R5, R6.

Amplifier EA1 in-phase input end is connected with resistance R 3, and output is connected with transistor M1.Transistor M1, M2 consist of current mirror, and the transistor M2 electric current I of flowing through 2 proportional replication streams are through transistor M1 electric current I 1, and the transistor M1 electric current of flowing through is

$I1=\frac{V_a}{R3}=(\mathrm{VIN}-\mathrm{VC})\&CenterDot;\frac{R2}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HSA00000059490700032.png"\; state="\{\{state\}\}">R</figure-callout>}1+\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HSA00000059490700021.png"\; state="\{\{state\}\}">R</figure-callout>}2}\&CenterDot;\frac{1}{R3}---\left(4\right)$

Suppose that transistor M1, M2 breadth length ratio equate, the transistor M2 electric current I 2 of flowing through equals I1, namely

$I2=I1=(\mathrm{VIN}-\mathrm{VC})\&CenterDot;\frac{R2}{R1+R2}\&CenterDot;\frac{1}{R3}---\left(5\right)$

Transistor M3, M2 series connection, and transistor M3, M4 formation current mirror, the proportional replication stream of transistor M4 electric current I CC of flowing through is through transistor M3 electric current I 3, and the proportional replication stream of transistor M4 electric current I CC of flowing through is through transistor M2 electric current I 2.Suppose that transistor M3, M4 breadth length ratio are identical, the transistor M4 electric current I of flowing through CC is

$\mathrm{ICC}=\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HSA00000059490700021.png"\; state="\{\{state\}\}">I</figure-callout>}2=I1=(\mathrm{VIN}-\mathrm{VC})\&CenterDot;\frac{R2}{R1+\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HSA00000059490700021.png"\; state="\{\{state\}\}">R</figure-callout>}2}\&CenterDot;\frac{1}{R3}---\left(6\right)$

Amplifier EA2 inverting input is reference voltage V BG, and in-phase input end is connected to resistance R 4 and transistor M5 drain electrode, and output is connected with transistor M5 grid.Transistor M5, resistance R 4, R5, R6 connect mutually, and with resistance R 5 and resistance R 6 tie points (d point) tie point of circuit 220 and peak detection circuit 230 by way of compensation, compensating circuit 220 exports the voltage Vd of peak detection circuit to and is

$\mathrm{Vd}=(\mathrm{VBG}-\mathrm{ICC}*R4)*\frac{R6}{R4+R5+R6}---\left(7\right)$

In compensating circuit 220, the d point is connected with comparator C MP in-phase input end VREFC,

$\mathrm{VREFC}=\mathrm{Vd}=(\mathrm{VBG}-\mathrm{ICC}*R4)*\frac{R6}{R4+R5+R6}---\left(8\right)$

Formula (6) substitution formula (8) can be got

$\mathrm{VREFC}=\mathrm{VBG}\frac{R6}{R4+R5+R6}-(\mathrm{VIN}-\mathrm{VC})\frac{R6}{R4+R5+R6}\frac{R4}{R3}\frac{R2}{R1+R2}---\left(9\right)$

Wherein, VREFC carries out the input voltage of comparator C MP in-phase end after current compensation to peak detection circuit; VC is some light-emitting diodes tube voltages in peak detection circuit; VBG is reference voltage, and magnitude of voltage is stable, is generally 1.2 volts; VIN line voltage, magnitude of voltage is unstable.

If when peak detection circuit 230 not being carried out current compensation, comparator C MP in-phase end input voltage is that VREF is

$\mathrm{VREF}=\mathrm{VBG}\frac{R6}{R4+R5+R6}---\left(10\right)$

Formula (10) substitution formula (9) can be got

$\mathrm{VREFC}=\mathrm{VREF}-(\mathrm{VIN}-\mathrm{VC})\frac{R6}{R4+R5+R6}\frac{R4}{R3}\frac{R2}{R1+R2}---\left(11\right)$

Can be found out by formula (11), for not adding line voltage compensation circuit 200, comparator C MP in-phase input end voltage has reduced

Fig. 4 is comparator C MP both end voltage contrast figure.In Fig. 4, left graph is ideally, comparator C MP end of oppisite phase input voltage VCS and in-phase end input voltage VREF relation curve, and the crest voltage on resistance R set is IPK0*Rset; Middle graphs is when peak detection circuit not being compensated, comparator C MP end of oppisite phase input voltage VCS and in-phase end input voltage VREF relation curve, this end of oppisite phase input voltage is IPK0*Rset after inductance reaches desirable peak current IPK0, continue to increase to IPK*Rset because system delay Td directly causes its crest voltage; Right side graph figure is after peak detection circuit is carried out line voltage compensation, comparator C MP end of oppisite phase input voltage VCS and in-phase end input voltage VREF relation curve, can be found out by this figure, due to voltage VREFC lower than reference voltage VREF0 ideally, therefore system can send cut-off signals in advance, the designer can make through after system delay Td by adjusting parameter (as resistance R 1, R2, R3), comparator end of oppisite phase crest voltage equals Rset and the product of inductance peak current ideally, is Rset*IPK0.

According to formula (2) as can be known, the voltage added value that is caused by system delay Td is

According to formula (11) as can be known, after the compensation, voltage VREFC is lower than ideal situation voltage VREF0 If therefore satisfy

$\frac{\mathrm{VIN}-\mathrm{VC}}{L}\mathrm{Td}*\mathrm{Rset}=(\mathrm{VIN}-\mathrm{VC})\frac{R6}{R4+R5+R6}\frac{R4}{R3}\frac{R2}{R1+R2}---\left(12\right)$

(have system delay Td) under actual conditions, the inductance peak current of peak detection circuit 230 is peak current IPK0 ideally.Equation (12) can be set up by adjusting parameter (as resistance R 1, R2, R3).

Fig. 5 is the line voltage compensation circuit diagram of another embodiment of the present invention.In Fig. 5, compensating circuit 220 comprises amplifier EA1, resistance R 3, transistor M1, M2, amplifier EA2, transistor M5, resistance R 4, R5, R6.

Transistor M1, M2 consist of current mirror.Transistor M2 in this compensating circuit 220 is connected with the resistance R set in peak detection circuit (tie point is m), and m point voltage Vm is

Vm=(I2+I _L) * Rset comparator C MP anti-phase input terminal voltage VCS is

VCS＝Vm＝(I2+I _L)×Rset

Wherein, I _LElectric current for the inductance L of flowing through in peak detection circuit.Comparator C MP in-phase input end voltage VREFC is

VREFC＝VCS＝(I2+I _L)×Rset (13)

Can get according to formula (13),

VREFC-I2×Rset＝I _L×Rset (14)

Formula (5) substitution formula (14) is got,

$\mathrm{VREFC}-(\mathrm{VIN}-\mathrm{VC})\&CenterDot;\frac{R2}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HSA00000059490700032.png"\; state="\{\{state\}\}">R</figure-callout>}1+\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HSA00000059490700021.png"\; state="\{\{state\}\}">R</figure-callout>}2}\&CenterDot;\frac{1}{R3}\&CenterDot;\mathrm{Rset}=I_L\&times;\mathrm{Rset}---\left(15\right)$

Adjustment R1, R2, R3 size make I _LEqual ideal inductance peak current IPK0, even formula

Set up, thereby realize that the inductance peak current is fixed constant.

Need to prove, sample circuit also can directly be connected with line voltage VIN, rather than is connected to peak detection circuit 230 light-emitting diode VC ends.That is to say, sample circuit also can direct sample VIN.

Fig. 6 is the line voltage compensation circuit diagram of another embodiment of the present invention.As seen from Figure 6, the resistance R 1 in sample circuit 210 is connected directly to line voltage VIN, and namely sample circuit 210 directly is connected with line voltage VIN.

Fig. 7 is the also line voltage compensation circuit diagram of an embodiment of the present invention.As seen from Figure 7, the resistance R 1 in sample circuit 210 is connected directly to line voltage VIN, and namely sample circuit 210 directly is connected with line voltage.

Obviously, under the prerequisite that does not depart from true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that is within all should being included in the scope that these claims contain.The present invention's scope required for protection is only limited by described claims.

Claims (9)

1. line voltage compensation circuit based on peak detection circuit, wherein, this peak detection circuit comprises switching circuit (MP), the 7th resistance (Rest), inductance (L), and this peak detection circuit is by line voltage (VIN) and through switching circuit (MP), the 7th resistance (Rest) charges to inductance (L), and by comparator (CMP) this resistance (Rest) both end voltage relatively, control the end that inductance (L) is charged by the unlatching of controlling this switching circuit (MP), in order to control the peak current of this inductance (L), it is characterized in that, comprise sample circuit (210) and compensating circuit (220),

Described sample circuit (210) is used for the sampling voltage relevant to line voltage (VIN), thereby obtains and proportional sampling voltage of dwindling linear with this line voltage (VIN);

Described compensating circuit (220) is connected with this sample circuit (210), be used for and compensated to this peak detection circuit comparator (CMP) in-phase input end (VREFC) or inverting input (VCS) by the sampling voltage of this sample circuit (210) output mode with the signal of telecommunication, so that this inductance (L) peak current is close to inductance peak current (1PK0) ideally;

Described sample circuit (210) comprises the first resistance (R1), the second resistance (R2), the common port of the first resistance (R1) and the second resistance (R2) is connected with the inverting input (VCS) of comparator (CMP), by way of compensation the input of circuit (220); Compensating circuit (220) comprises the first amplifier (EA1), the 3rd resistance (R3), the first current mirror, the second current mirror, the second amplifier (EA2), the 5th transistor (M5), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), wherein, this first current mirror comprises the first branch road and the second branch road, the second current mirror comprises the 3rd branch road and the 4th branch road, and the 3rd resistance (R3) is on this first branch road;

This first amplifier (EA1) in-phase input end is connected with the 3rd resistance (R3), and this first amplifier (EA1) output is connected to described the first branch road, and this second branch road is connected with the 3rd branch road;

This second amplifier (EA2) inverting input is reference voltage (VBG), and in-phase input end is connected to the 4th resistance (R4), and output is connected with the 5th transistor (M5) grid;

The 5th transistor (M5), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6) series connection, and export described the 4th branch road to the 4th resistance (R4), the 5th resistance (R5) tie point, and with the 5th resistance (R5), the 6th resistance (R6) tie point as comparator (CMP) in-phase input end (VREFC) in this peak detection circuit;

Described the first current mirror comprises the first transistor (M1) and transistor seconds (M2), and this first branch road comprises this first transistor (M1), and this second branch road comprises this transistor seconds (M2).

2. a kind of line voltage compensation circuit based on peak detection circuit as claimed in claim 1, is characterized in that, described switching circuit (MP) is transistor.

3. a kind of line voltage compensation circuit based on peak detection circuit as claimed in claim 1, it is characterized in that, described sample circuit (210) comprises the first resistance (R1), the second resistance (R2), and this first resistance (R1), the second resistance (R2) series connection mutually, and with this tie point as this sample circuit (210) output, in order to be connected with described compensating circuit (220) by this output.

4. a kind of line voltage compensation circuit based on peak detection circuit as claimed in claim 3 wherein, this peak detection circuit comprises some series connection light-emitting diodes, and these some light-emitting diode one ends are connected to line voltage (VIN) other end and are connected with this inductance (L), it is characterized in that, described the first resistance (R1) is connected to this some series connection light-emitting diodes.

5. a kind of line voltage compensation circuit based on peak detection circuit as claimed in claim 4, is characterized in that, described sampling voltage is

Wherein, VIN is line voltage, and VC is the magnitude of voltage of some light-emitting diodes, and R1 is the first resistance, and R2 is the second resistance.

6. a kind of line voltage compensation circuit based on peak detection circuit as claimed in claim 3, is characterized in that, described the first resistance (R1) is connected to line voltage (VIN).

7. a kind of line voltage compensation circuit based on peak detection circuit as claimed in claim 6, is characterized in that, described sampling voltage is

Wherein, VIN is line voltage, and R1 is the first resistance, and R2 is the second resistance.

8. a kind of line voltage compensation circuit based on peak detection circuit as claimed in claim 1, it is characterized in that, described the first current mirror comprises the first transistor (M1) and transistor seconds (M2), and this first branch road comprises the first transistor (M1), and this second branch road comprises transistor seconds (M2); Described the second current mirror comprises the 3rd transistor (M3) and the 4th transistor (M4), and this first branch road comprises the 3rd transistor (M3), and this second branch road comprises the 4th transistor (M4).

9. a kind of line voltage compensation circuit based on peak detection circuit as claimed in claim 1, is characterized in that, described sample circuit (210) comprises the first resistance (R1), the second resistance (R2); Described compensating circuit (220) comprises the first amplifier (EA1), the 3rd resistance (R3), the first current mirror, the second amplifier (EA2), the 5th transistor (M5), the 4th resistance (R4), the 6th resistance (R6), wherein, this first current mirror comprises the first branch road and the second branch road, and the 3rd resistance (R3) is on this first branch road;

This first amplifier (EA1) in-phase input end is connected with the 3rd resistance (R3), this the first amplifier (EA1) output is connected to described the first branch road, and this second branch road is connected to the 7th resistance (Rest) in this peak detection circuit;

This second amplifier (EA2) inverting input is reference voltage (VBG), and in-phase input end is connected to the 4th resistance (R4), and output is connected with the 5th transistor (M5) grid;

The 5th transistor (M5), the 4th resistance (R4), the 6th resistance (R6) series connection, and with the 4th resistance (R4), the 6th resistance (R6) tie point as comparator (CMP) in-phase input end (VREFC) in this peak detection circuit.

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