CN102194815A - 金属氧化物半导体组件及其制作方法 - Google Patents

金属氧化物半导体组件及其制作方法 Download PDF

Info

Publication number
CN102194815A
CN102194815A CN2010102935369A CN201010293536A CN102194815A CN 102194815 A CN102194815 A CN 102194815A CN 2010102935369 A CN2010102935369 A CN 2010102935369A CN 201010293536 A CN201010293536 A CN 201010293536A CN 102194815 A CN102194815 A CN 102194815A
Authority
CN
China
Prior art keywords
grid
contact
oxide semiconductor
metal oxide
semiconductor component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010102935369A
Other languages
English (en)
Other versions
CN102194815B (zh
Inventor
薛福隆
赵治平
周淳朴
彭永州
庄学理
宋国栋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102194815A publication Critical patent/CN102194815A/zh
Application granted granted Critical
Publication of CN102194815B publication Critical patent/CN102194815B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Architecture (AREA)
  • Software Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明揭露一种金属氧化物半导体组件及其制作方法，该金属氧化物半导体(MOS)组件包含具有第一与第二接触的有源区。第一与第二栅极位于第一与第二接触之间。第一栅极邻设于第一接触，且具有第三接触。第二栅极邻设于第二接触，且具有与第三接触耦合的第四接触。为有源区与第一栅极所定义出的晶体管具有第一临界电压，而为有源区与第二栅极所定义出的晶体管具有第二临界电压。

Description

金属氧化物半导体组件及其制作方法
本申请案要求享有于2010年3月5日申请的美国临时专利申请案编号第61/310853号的优先权，在此将此申请案的全部一并列入参考。
技术领域
本发明所揭露的系统与方法是有关于集成电路。更特别的是，所揭露的系统与方法是有关于具有大栅极宽度的集成电路组件，此集成电路的制作是利用互补式金属氧化物半导体(CMOS)科技。
背景技术
根据国际半导体技术蓝图(International Technology Roadmap forSemiconductors；ITRS)，低于40nm的技术节点具有固定间距的固定多晶硅(poly)图案、或具有单向(uni-direction)多晶硅图案，来制作金属氧化物半导体(MOS)组件。对于科技节点小于40nm而言，这些固定多晶硅间距图案使多晶硅不能具有大而连续的长度。这样在大多晶硅宽度尺寸上的限制，会在MOS组件上的许多逻辑电路中造成问题，MOS组件上的逻辑电路需要大栅极-源极电阻，以提供大利益。
因此，需要一种MOS的改良设计。
发明内容
因此，本发明的一目的就是在提供一种金属氧化物半导体组件及其制作方法，其可在维持一致的特性下，制作出栅极长度超过欲制作的最大许可间距图案的MOS组件。
本发明揭露一种金属氧化物半导体组件，此金属氧化物半导体组件包含：具有第一与第二接触的有源区(active area)。第一与第二栅极位于第一与第二接触之间。第一栅极邻设于第一接触，且具有第三接触。第二栅极邻设于第二接触，且具有与第三接触耦合的第四接触。为有源区与第一栅极所定义出的晶体管具有第一临界电压，而为有源区与第二栅极所定义出的晶体管具有第二临界电压。
本发明还揭露一种金属氧化物半导体组件的制作方法，其中提供一金属氧化物半导体组件的初始模型。金属氧化物半导体组件包含具有栅极接触的栅极，此栅极接触位于一有源区上方，且有源区包含第一与第二接触。根据初始模型产生前述的金属氧化物半导体组件的最终模型，如此最终模型中的金属氧化物半导体组件的栅极包含多个手指，且每个手指具有各自的栅极接触。每个手指分别与有源区定义出晶体管。前述的晶体管中的第一者具有第一临界电压，这些晶体管中的第二者具有第二临界电压。将金属氧化物半导体组件的最终模型储存在计算机可读储存媒介中。调整由该有源区与该些手指的一者所定义的该些晶体管的一者的一临界电压，以产生该金属氧化物半导体组件的一中间模型。模拟(simulating)包含该金属氧化物半导体组件的该中间模型的一电路。以及重复该步骤d)与该步骤e)，直至达成该金属氧化物半导体组件的一所需响应。
本发明还揭露一种金属氧化物半导体组件，包含：一有源区，具有一源极接触与一漏极接触相隔一距离；一第一栅极区，形成在该有源区上且位于该源极接触与该漏极接触之间，该第一栅极区与该源极接触及该漏极接触定义出一第一晶体管，该第一晶体管具有一第一临界电压；以及一第二栅极区，形成在该有源区上且位于该源极接触与该漏极接触之间，该第二栅极区与该源极接触及该漏极接触定义出一第二晶体管，该第二晶体管具有一第二临界电压，其中该第一栅极区与该第二栅极区包含各自的一栅极接触，且该些栅极接触耦合在一起而形成该金属氧化物半导体组件的一栅极。
运用本揭露，可在维持一致的特性下，制作出栅极长度超过欲制作的最大许可间距图案的MOS组件。
附图说明
图1A是绘示一种传统MOS组件的布局；
图1B是绘示一种包含多个手指的等效MOS组件的布局；
图2A至图2D是绘示一种包含多个手指的改良MOS组件的布局；
图3是绘示一种改良的多手指的MOS组件的设计方法的一个例子的流程图；以及
图4是绘示一种改良的多手指的MOS组件的模拟系统的一个例子的方块图。
【主要组件符号说明】
100：MOS组件            102：栅极
104：有源区             106：接触
108：接触               110：接触
120：MOS组件            122：手指
122-1：手指             122-2：手指
122-3：手指             122-4：手指
122-5：手指             124：栅极
126：有源区             128：第一接触
130：第二接触           132：接触
200A：MOS组件           200B：MOS组件
200C：MOS组件           200D：MOS组件
202：手指               202-1：手指
202-2：手指             202-3：手指
202-4：手指             204：手指
204-1：手指             204-2：手指
206-1：手指             206-2：手指
208：栅极               210：有源区
212：接触               214：接触
216：接触               218：导电层
300：方法               302：方块
306：方块               308：方块
310：方块               312：方块
314：方块               316：方块
318：方块               400：系统
402：电子设计自动化工具 404：绕线器
406：处理器                  408：通讯接口
410：输入组件                412：屏幕
414：计算机可读储存媒介      416：计算机可读储存媒介
418：集成电路设计与晶胞信息  420：设计规则
422：指令                    424：数据文件
426：预测组件的目录数据      L：长度
Lmin：长度
具体实施方式
在此所揭露的MOS组件的改善方法与布局，可在维持一致的特性下，制作出栅极长度超过欲制作的最大许可间距图案的MOS组件。
图1A是绘示一MOS组件100形成于有源区(active area)104上方，此MOS组件100包含长度L的栅极102。接触106可为漏极接触，接触108可为源极接触，而数个接触110耦合在一起而形成一栅极接触，以连接至其它组件。传统地，若MOS组件100的栅极长度超过ITRS为一特定科技节点所提出的最大间距长度，例如28nm时的1μm栅极长度，利用数个手指，例如均具有100nm的栅极长度的10个手指，来制作MOS组件。图1B是绘示具有五个手指122-1～122-5(共同称为“手指122”)耦合成一串迭状的MOS组件120，这些手指的总栅极长度等于MOS组件100的栅极长度L。每个手指122包含长度Lmin的栅极124，此长度Lmin为栅极102的长度L的一个等分部分，例如长度Lmin等于长度L的五分之一。数个栅极124形成于有源区126的上方，其中有源区126具有第一接触128位于一端、以及第二接触130位于另一端。数个接触132为栅极接触，这些接触132可耦合在一起，并耦合至其它组件，以开启或关闭每个手指122。每个栅极124结合有源区126、以及第一与第二接触128与130，而定义出一晶体管，其中第一与第二接触128与130可分别为源极接触与漏极接触。形成每个晶体管，借此这些晶体管具有相同的临界电压。
然而，由于整个MOS组件120的变化，可能造成包含MOS组件120的电路的不良表现，因此手指122可能不会同时开启或关闭。举例而言，假设接触130的电压大于接触128，例如Vs＞Vd，手指122-1的源极电压大于手指122-2的源极电压，手指122-2具有大于手指122-3的源极电压等等，如此，手指122-5具有最高的源极电压，而手指122-1具有最低的源极电压。整个MOS组件120的源极电压的变化是源自横跨每个栅极124的电压降，导致手指122-1具有较高的漏极至源极崩溃(drain-to-source breakdown)的发生率。
图2A至图2D是绘示一种MOS组件的改良布局的数种实施例。图2A所示的MOS组件200A包含多个手指202-1～202-4与204-1(共同称为“手指202、204”)，这些手指202-1～202-4与204-1具有栅极208形成在有源区210上方。接触212与214可分别为MOS组件200A的源极与漏极接触，虽然熟习此技艺者将了解到，接触212可为漏极接触，接触214可为源极接触。手指202与204的接触216为导电层218所联结在一起，而共同形成MOS组件200A的栅极接触。
不像由多个手指所制成的MOS组件，其每个手指具有相同的临界电压Vth，MOS组件200A包含具有不同临界电压的手指202与204。举例而言，手指202可具有第一临界电压Vth-202，手指204-1可具有第二临界电压Vth-204，其中若接触214为源极接触，临界电压Vth-204低于临界电压Vth-202。通过改变手指的栅极下方的通道的掺杂浓度，可调整任何手指202与204的临界电压。举例而言，有源区210中的通道，其在位于手指202的栅极208下方处可具有较高的掺杂浓度，在位于手指204的栅极208下方处可具有较低的掺杂浓度。额外地或替代地，可调整手指202与204的栅极氧化物的厚度，来改变临界电压。实施具有不同临界电压的多个手指202与204的MOS组件200A，有助于减少手指202与204的漏极至源极的崩溃。
可改变在MOS组件中的手指的数量、以及每个手指之临界电压。举例而言，图2B绘示一实施例，其中MOS组件200B包含具有一临界电压Vth-202的三个手指202-1～202-3、以及具有另一临界电压Vth-204的二个手指204-1与204-2。手指204-1与204-2可相邻设于漏极接触212，且具有低于手指202-1～202-3的临界电压。图2C绘示另一实施例，其中MOS组件200C包含具有第一临界电压Vth-202的三个手指202-1～202-3、具有第二临界电压Vth-204的一个手指204-1、以及具有第三临界电压Vth-206的另一个手指206-1。临界电压Vth-202可大于临界电压Vth-204，且临界电压Vth-204可大于临界电压Vth-206。图2D绘示另一实施例，其中MOS组件200D包含五个手指，其为具有第一临界电压Vth-202的二个手指202-1与202-2、具有第二临界电压Vth-204的一个手指204-1、以及具有第三临界电压Vth-206的二个手指206-1与206-2。熟习此项技艺者可了解到，手指的数量与临界电压的数量并没有限制。
参照图3描述改良的MOS组件的设计与制造。如图3所示，在方块302中，接收包含至少一MOS组件的电路设计，其中此MOS组件的栅极长度超过科技节点的最大多晶硅图案间距。在方块306中，将具有栅极长度L的MOS组件分成多个手指，每个手指具有栅极长度Lmin，且这些手指具有至少两种临界电压。如上所述，每个手指的栅极长度Lmin可为栅极长度L的一个等分部分。举例而言，若MOS组件的栅极长度L为1μm，MOS组件可分成10个手指，每个手指的栅极长度Lmin等于100nm，属于28nm科技节点。
在方块308中，进行包含MOS组件的电路的模拟，此MOS组件具有多个手指。此模拟的进行可利用特别为集成电路模拟的程序(Simulation.Programwith Integrated Circuit Emphasis；SPICE)，其中此模拟程序可在如图4所示的系统400上进行。如图4所示，系统400可包含具有绕线器(router)404的电子设计自动化(Electronic Design Automation；EDA)工具402，其中电子设计自动化工具402可例如为加州山景城(Mountain View，CA)的新思科技股份有限公司(Synopsis，Inc.)所销售的“IC COMPILER TM”，绕线器404也可为新思科技股份有限公司所销售的“ZROUTE TM”。也可使用其它的电子设计自动化工具402，例如“VIRTUOSO”定制设计平台或具有“VIRTUOSO”芯片组装绕线器404的
Figure BSA00000285767100061
数字集成电路设计平台，以上设备均为加州圣荷西(San Jose，CA)的益华计算机科技股份有限公司(Cadence DesignSystem，Inc.)所销售。
电子设计自动化工具402是一特殊目的计算机，其形成是通过从计算机可读储存媒介414与416撷取储存的程序指令422，并在一般用途(general-purpose)处理器406上执行这些指令。处理器406可为任何中央处理单元(CPU)、微处理器、微控制器、或计算器组件或电路，来执行这些指令。处理器406可装设来进行根据储存在一或多个计算机可读储存媒介414与416中的多个数据的电路模拟。
计算机可读储存媒介414与416可包含一或多个寄存器(Register)、随机存取内存(RAM)及/或常驻内存(Persistent Memory)，例如只读存储器(ROM)。随机存取内存的例子包含但不限于静态随机存取内存(SRAM)或动态随机存取内存(DRAM)。只读存储器可以熟悉此项技艺者所了解的可编程只读存储器(PROM)、可抹除可程序只读存储器(EPROM)、可电性抹除可编程只读存储器(EEPROM)、磁性或光学储存媒介来实施。
系统400可包含屏幕412与使用者接口或输入组件410，例如鼠标、触碰屏幕(Touch Screen)、麦克风、轨迹球(Trackball)、键盘或类似组件，透过这些组件，使用者可输入设计指令及/或数据。一或多个计算机可读储存媒介414与416可储存使用者所需入的数据、设计规则420、集成电路设计与晶胞信息418、表示电路的实体布局的数据文件424，例如GSDII文件，以及预测组件的目录数据426。计算机可读储存媒介414与416也可储存各种型式的晶体管模型，这些型式包含但不限于例如BSIM3、BSIM4、PSP与HiSIM。
电子设计自动化工具402可包含通讯接口408，可允许软件与数据在电子设计自动化工具402与外部组件之间传送。通讯接口408的例子包含但不限于调制解调器、以太网络卡、无线网络卡、个人计算机存储卡国际协会(PCMICA)插槽与卡等等。通过通讯接口408传送的软件与数据可呈信号的形式，例如电子、电磁、光学、等等可被通讯接口408接收的信号形式。这些信号可经由通讯路径而提供给通讯接口408，其中通讯路径的实施可利用例如电线、电缆、光纤、电话线、蜂巢式链接(Cellular Link)、与射频(RF)链接。
绕线器404可接收将被包含在集成电路布局中的多个电路构件的辨识(Identification)，此集成电路布局包含一列晶胞对、宏区块(Macro Blocks)、或位于欲互相连接的多个电路构件中的输入/输出(I/O)垫。对于各种科技节点(例如，科技大于、小于或等于40nm)，可使用一组设计规则420。在一些实施例中，设计规则420装配绕线器404，以在制造网格线(Manufacturing Grid)上设置连接线与介层窗。可在屏幕412上对系统400的使用者显示一或多个数据的标绘图(plot)。
在决定方块310中，检查模拟结果，以决定包含多个手指的MOS组件是否适当运转。举例而言，模拟结果可确认MOS组件的每个手指的崩溃电压。若模拟结果为不适合，方法继续进行至方块312，在方块312中，调整MOS组件的一或多个手指的临界电压。于方块308中，再次模拟电路。熟悉此项技艺者将了解到，可进行包含方块308、310与312的回路任意次，直至达成MOS组件的每个手指的所需运作。此重复步骤的进行，可利用计算机针对数个不同晶体管的调整，多次决定MOS组件的每个手指的崩溃电压，如此可在真实硅上的第一重复上，完成可接受的多手指MOS组件。
在方块314中，若包含MOS组件的电路的模拟指示此配置是可接受的，就将包含MOS组件的电路的模拟结果与参数储存在计算机可读储存媒介中。在方块316中，形成包含多手指的MOS组件的电路的掩膜。接着，在方块318中，可制作包含多手指的MOS组件的电路。
在其它例子中，接下来掩膜组的产生以及包含MOS组件的基材的制作，可通过输入应用在硅上的设计来作为图3的输入设计，而利用图3的方法300来进行额外的调整。
本发明可包含一或多个构件，其中这些构件呈计算机执行工艺与实施这些工艺的设备的型式。这些构件也可以计算机可读程序代码的型式加以体现，计算机可读程序代码可实施在实体机器可读储存媒介中，例如随机存取内存(RAM)、软性磁盘(Floppy Diskettes)、只读存储器(ROM)、只读光驱(CD-ROMs)、硬盘机、闪存、或任何其它机械可读储存媒介，其中当计算机程序码加载计算机并由计算机所执行时，计算机变成实施本发明的设备。这些构件也可以计算机程序码的形式实践，此计算机程序码加载计算机并由计算机所执行，借此当计算机程序码加载计算机并由计算机所执行时，计算机变成实施本发明的设备。当实施在一般用途处理器上，计算机程序码程序段安排处理器来产生特殊逻辑电路。这些构件可替代式地体现在特殊应用的集成电路所形成的数字信号处理器上，以根据在此所描述的原理进行一种方法。
虽然本发明已以示范实施例描述如上，然其并非用以限定本发明。应广泛地解释所附的申请专利范围，以包含熟悉此技艺者可能在不脱离本发明的等效范围所做的本发明的其它各种变化与实施例。使用在申请专利范围中的定义符号(delimiters)，例如“a)”与“i)”，应不能视为归于申请专利范围的任何次序，而仅提供来作为视觉上的提示以加入申请专利范围的语法，以及作为申请专利范围中后续将被参照的特定部分的项目中的识别符号。

Claims (10)

1.一种金属氧化物半导体组件，其特征在于，包含：
一有源区，包含一第一接触与一第二接触，其中该第一接触为该金属氧化物半导体组件的一源极接触，该第二接触为该金属氧化物半导体组件的一漏极接触；以及
一第一栅极与一第二栅极，介于该第一接触与该第二接触之间，该第一栅极邻设于该第一接触且具有一第三接触，该第二栅极邻设于该第二接触且具有与该第三接触耦合的一第四接触，
其中，为该有源区与该第一栅极所定义出的一晶体管具有一第一临界电压，为该有源区与该第二栅极所定义出的一晶体管具有一第二临界电压。
2.根据权利要求1所述的金属氧化物半导体组件，其特征在于，该第一临界电压高于该第二临界电压。
3.根据权利要求1所述的金属氧化物半导体组件，其特征在于，还包含多个栅极形成在该第一栅极与该第二栅极之间的该有源区上方，其中位于该第一栅极与该第二栅极之间的每一该些栅极与该有源区定义出一晶体管，且由该有源区、及位于该第一栅极与该第二栅极之间的该些栅极所定义出的每一该些晶体管具有该第一临界电压。
4.根据权利要求3所述的金属氧化物半导体组件，其特征在于，由该有源区、及位于该第一栅极与该第二栅极之间的该些栅极所定义出的每一该些晶体管具有该第二临界电压。
5.根据权利要求3所述的金属氧化物半导体组件，其特征在于，由该有源区、及位于该第一栅极与该第二栅极之间的该些栅极所定义出的该些晶体管的一第一子集具有该第一临界电压。
6.根据权利要求5所述的金属氧化物半导体组件，其特征在于，由该有源区、及位于该第一栅极与该第二栅极之间的该些栅极所定义出的该些晶体管的一第二子集具有该第二临界电压。
7.一种金属氧化物半导体组件的制作方法，其特征在于，包含：
a)提供一金属氧化物半导体组件的一初始模型，该金属氧化物半导体组件包含一栅极，该栅极具有一栅极接触位于一有源区上方，该有源区具有一第一接触与一第二接触；
b)根据该初始模型产生该金属氧化物半导体组件的一最终模型，如此该最终模型中的该金属氧化物半导体组件包含多个手指，每一该些手指具有各自的一栅极接触，每一该些手指分别与该有源区定义出一晶体管，该些晶体管中的一第一者具有一第一临界电压，该些晶体管中的一第二者具有一第二临界电压；以及
c)将该金属氧化物半导体组件的该最终模型储存在一计算机可读储存媒介中；
d)调整由该有源区与该些手指的一者所定义的该些晶体管的一者的一临界电压，以产生该金属氧化物半导体组件的一中间模型；
e)模拟包含该金属氧化物半导体组件的该中间模型的一电路；以及
f)重复该步骤d)与该步骤e)，直至达成该金属氧化物半导体组件的一所需响应。
8.根据权利要求7所述的金属氧化物半导体组件的制作方法，其特征在于，还包含：
d)根据该金属氧化物半导体组件的该最终模型形成一光学工艺的一掩膜；以及
e)利用该掩膜在一半导体晶片上制作该金属氧化物半导体组件。
9.根据权利要求7所述的金属氧化物半导体组件的制作方法，其特征在于，
该第一接触为一源极接触，且该第二接触为一漏极接触，
该些晶体管的该第一者的一栅极邻设于该第一接触，
该些晶体管的该第二者的一栅极邻设于该第二接触，
该第一临界电压小于该第二临界电压，
该金属氧化物半导体组件的该最终模型包含该些晶体管中的一第三者，该第三者包含一第三栅极位于该些晶体管的该第一者的该栅极与该些晶体管的该第二者的该栅极之间，以及
该些晶体管的该第三者具有一第三临界电压大于该第一临界电压。
10.一种金属氧化物半导体组件，其特征在于，包含：
一有源区，具有一源极接触与一漏极接触相隔一距离；
一第一栅极区，形成在该有源区上且位于该源极接触与该漏极接触之间，该第一栅极区与该源极接触及该漏极接触定义出一第一晶体管，该第一晶体管具有一第一临界电压；以及
一第二栅极区，形成在该有源区上且位于该源极接触与该漏极接触之间，该第二栅极区与该源极接触及该漏极接触定义出一第二晶体管，该第二晶体管具有一第二临界电压，
其中该第一栅极区与该第二栅极区包含各自的一栅极接触，且该些栅极接触耦合在一起而形成该金属氧化物半导体组件的一栅极。
CN201010293536.9A 2010-03-05 2010-09-21 金属氧化物半导体组件及其制作方法 Active CN102194815B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US31085310P 2010-03-05 2010-03-05
US61/310,853 2010-03-05
US12/766,972 2010-04-26
US12/766,972 US8847321B2 (en) 2010-03-05 2010-04-26 Cascode CMOS structure

Publications (2)

Publication Number Publication Date
CN102194815A true CN102194815A (zh) 2011-09-21
CN102194815B CN102194815B (zh) 2014-01-01

Family

ID=44530584

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010293536.9A Active CN102194815B (zh) 2010-03-05 2010-09-21 金属氧化物半导体组件及其制作方法

Country Status (2)

Country Link
US (2) US8847321B2 (zh)
CN (1) CN102194815B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8832619B2 (en) * 2013-01-28 2014-09-09 Taiwan Semiconductor Manufacturing Co., Ltd. Analytical model for predicting current mismatch in metal oxide semiconductor arrays
US10978583B2 (en) 2017-06-21 2021-04-13 Cree, Inc. Semiconductor devices having a plurality of unit cell transistors that have smoothed turn-on behavior and improved linearity
US10872189B2 (en) * 2017-12-13 2020-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Uni-gate cell design

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4600933A (en) * 1976-12-14 1986-07-15 Standard Microsystems Corporation Semiconductor integrated circuit structure with selectively modified insulation layer
US5789791A (en) * 1996-08-27 1998-08-04 National Semiconductor Corporation Multi-finger MOS transistor with reduced gate resistance
US20080121997A1 (en) * 2006-07-19 2008-05-29 Hongning Yang Multi-gate semiconductor device and method for forming the same
CN101431078A (zh) * 2007-11-05 2009-05-13 国际商业机器公司 Cmos eprom和eeprom器件以及可编程cmos反相器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245543A (en) * 1990-12-21 1993-09-14 Texas Instruments Incorporated Method and apparatus for integrated circuit design
US6835987B2 (en) * 2001-01-31 2004-12-28 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device in which selection gate transistors and memory cells have different structures
US6611025B2 (en) * 2001-09-05 2003-08-26 Winbond Electronics Corp. Apparatus and method for improved power bus ESD protection
JP2005243928A (ja) * 2004-02-26 2005-09-08 Fujitsu Ltd トレンチアイソレーションで分離されたトランジスタ対を有する半導体装置
JP2006073939A (ja) * 2004-09-06 2006-03-16 Toshiba Corp 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法
JP4830421B2 (ja) * 2005-06-28 2011-12-07 東京エレクトロン株式会社 金属膜の成膜方法及び成膜装置
US7461366B2 (en) * 2005-11-21 2008-12-02 Intersil Americas Inc. Usage of a buildcode to specify layout characteristics
US7802217B1 (en) * 2008-01-25 2010-09-21 Oracle America, Inc. Leakage power optimization considering gate input activity and timing slack
US8067287B2 (en) * 2008-02-25 2011-11-29 Infineon Technologies Ag Asymmetric segmented channel transistors
JP2010045133A (ja) * 2008-08-11 2010-02-25 Toshiba Corp 半導体集積回路装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4600933A (en) * 1976-12-14 1986-07-15 Standard Microsystems Corporation Semiconductor integrated circuit structure with selectively modified insulation layer
US5789791A (en) * 1996-08-27 1998-08-04 National Semiconductor Corporation Multi-finger MOS transistor with reduced gate resistance
US20080121997A1 (en) * 2006-07-19 2008-05-29 Hongning Yang Multi-gate semiconductor device and method for forming the same
CN101431078A (zh) * 2007-11-05 2009-05-13 国际商业机器公司 Cmos eprom和eeprom器件以及可编程cmos反相器

Also Published As

Publication number Publication date
US20150020039A1 (en) 2015-01-15
US8847321B2 (en) 2014-09-30
US20110215420A1 (en) 2011-09-08
CN102194815B (zh) 2014-01-01
US9607121B2 (en) 2017-03-28

Similar Documents

Publication Publication Date Title
US10553575B2 (en) Semiconductor device having engineering change order (ECO) cells and method of using
US12079555B2 (en) Automated circuit generation
US9087170B2 (en) Cell layout design and method
US10169515B2 (en) Layout modification method and system
CN103577625A (zh) 设计半导体器件、制造器件的系统以及使用系统的方法
CN102760651B (zh) 版图逻辑运算方法以及集成电路制造方法
CN102194815B (zh) 金属氧化物半导体组件及其制作方法
CN102237876B (zh) 排列电流源单元的方法与应用此方法的电流源单元阵列
US11855632B2 (en) Logic cell structure and integrated circuit with the logic cell structure
US20220309225A1 (en) Metal Routing Techniques
US8302060B2 (en) I/O cell architecture
Chung et al. Improving performance and power by co-optimizing middle-of-line routing, pin pattern generation, and contact over active gates in standard cell layout synthesis
US20140068535A1 (en) System and method for configuring a transistor device using rx tuck
US20050028120A1 (en) Method and software for automatically designing IC layout
US10509888B1 (en) System and method for forming integrated device
US8438526B2 (en) Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant