CN102194679A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN102194679A
CN102194679A CN2010101302867A CN201010130286A CN102194679A CN 102194679 A CN102194679 A CN 102194679A CN 2010101302867 A CN2010101302867 A CN 2010101302867A CN 201010130286 A CN201010130286 A CN 201010130286A CN 102194679 A CN102194679 A CN 102194679A
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acid treatment
wafer
hydrofluoric acid
treatment
side wall
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CN2010101302867A
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CN102194679B (en
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李强
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention provides a method for manufacturing a semiconductor device. The method comprises the following steps: forming a grid structure on a semiconductor substrate of a wafer; forming side wall layers with an oxide layer-nitride layer-oxide layer laminated structure on the two sides of the grid structure; and performing hydrofluoric acid treatment on the surface of the wafer. The method provided by the invention can greatly reduce oxide impurities formed on the surface of the wafer after the side wall layers are formed.

Description

The manufacture method of semiconductor device
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of semiconductor device.
Background technology
At present, be accompanied by the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, bigger memory data output and more function, wafer develops towards higher component density, high integration direction, and the making of grating of semiconductor element position becomes more and more important.
In the prior art, the manufacture method of semiconductor device may further comprise the steps, and describes below in conjunction with Fig. 1 a to Fig. 1 c.
Step 11, formation grid structure, as shown in Figure 1a: at first need on Semiconductor substrate 100, to generate grid oxic horizon 110, deposit spathic silicon layer 120 on grid oxic horizon 110 then, follow surface coated photoresistance glue-line (not shown) at described polysilicon layer 120, this photoresistance glue-line of exposure imaging patterning, the position of definition grid is a mask with the photoresistance glue-line of patterning, etch polysilicon layer 120 and grid oxic horizon 110 form grid structure successively;
Step 12, form side wall layer (spacer): after removing photoresistance glue in the both sides of grid structure, surface at polysilicon layer 120, and the surface of Semiconductor substrate 100 deposits first oxide layer 130, nitration case 140 and second oxide layer 150 successively, dry etching first oxide layer 130, nitration case 140 then, and the part of second oxide layer 150, shown in Fig. 1 b, because dry etching is an anisotropic etching, so etching is mainly carried out in the horizontal direction, and the thickness on the reservation sidewall (vertical direction); When then the remainder of wet etching second oxide layer 150 is to predetermined thickness, finish etching, shown in Fig. 1 c, form side wall layer, formed here side wall layer is three layers of oxide layer-nitride layer-oxide layer (ONO) laminated construction.Wherein, very fast for preventing dry etching speed, if uncontrollable etch rate when adopting dry etching second oxide layer 150 fully causes etching into Semiconductor substrate, so the part of a dry etching etching second oxide layer 150.And when finishing wet etching second oxide layer 150, still reserve certain thickness on Semiconductor substrate, when second oxide layer 150 of this predetermined thickness was injected at follow-up ion, the protection Semiconductor substrate was not subjected to ion dam age.Oxide layer in the side wall layer generally adopts tetraethoxysilane (TEOS) and ozone (O 3) reactive deposition silica (SiO 2) layer.
It should be noted that, adopt hydrofluoric acid (HF) in the prior art during general wet etching second oxide layer 150, wet etching carries out in acid tank, hydrofluoric acid in the acid tank recycles after filtration afterwards, if after the long-time use of filter, filter effect will variation, have impurity defect in the feasible hydrofluoric acid that reuses, drop on the wafer (wafer) that will carry out wet etching, every wafer comprises a plurality of exposing units (shot), and the pattern that full wafer wafer goes up between each shot is identical, is about to wafer and is divided into the shot that several have periodic structure, comprise a plurality of die again in the shot, a plurality of grids distribute in each die.The discovery of catching by scanning electron microscopy (SEM), lower corners zone at each die, the quantity of this impurity defect is especially serious than other zones, as shown in Figure 2, and the impurity defect distribution map on the die that Fig. 2 catches for scanning electron microscopy.Through X-ray spectral analysis, the main component of this impurity defect still is an oxide.Fig. 3 is transmission electron microscope (TEM, Transmission Electron Microscope) the sample section schematic diagram under, impurity defect also may drop on other zones, for the existing in prior technology problem more clearly is described, only shows the main region that impurity defect occurs among the figure.As shown in Figure 3; impurity defect can drop on the zone between grid and the grid; perhaps the impurity defect of bulk directly couples together grid and grid; this has all increased follow-up zone between grid on the Semiconductor substrate and grid greatly; when carrying out the ion injection, the thickness of protective layer, the effect when having a strong impact on the ion injection; for example same implantation dosage causes injecting problem such as the degree of depth is more shallow.So when impurity defect quantity was too much, scrappage (kill rate) also was very high.
Summary of the invention
In view of this, the technical problem of the present invention's solution is: reduce side wall layer wet etching impurity defect afterwards.
For solving the problems of the technologies described above, technical scheme of the present invention specifically is achieved in that
The invention discloses a kind of manufacture method of semiconductor device, this method comprises:
On the wafer semiconductor substrate, form grid structure;
Has the side wall layer of oxide layer-nitride layer-oxide layer laminated construction in the formation of the both sides of grid structure;
Wafer surface is carried out hydrofluoric acid treatment.
After forming described side wall layer, wafer surface is carried out wafer surface being detected before the hydrofluoric acid treatment, when detecting the oxide impurity defective, wafer surface is carried out hydrofluoric acid treatment.
This method further comprises and adopts sulfuric acid treatment and WITH AMMONIA TREATMENT wafer successively after hydrofluoric acid treatment.
This method further comprises employing sulfuric acid treatment or WITH AMMONIA TREATMENT wafer after hydrofluoric acid treatment.
The method of described hydrofluoric acid treatment is:
Adopting concentration is that 49% diluted hydrofluoric acid DHF and the ratio of deionized water DIW are 100: 1; Temperature range is controlled at 22.5～23.5 degrees centigrade; Processing time is 5 seconds.
The method of described sulfuric acid treatment is:
Employing concentration is 98% sulfuric acid H 2SO 4With oxydol H 2O 2Ratio be 5: 1; Temperature range is controlled at 120～130 degrees centigrade; Processing time is 10 minutes.
The method of described WITH AMMONIA TREATMENT is:
Ammoniacal liquor NH 4OH and H 2O 2With the ratio of DIW be 1: 2: 50; Temperature range is controlled at 28～32 degrees centigrade; Processing time is 420 seconds.
As seen from the above technical solutions, the present invention carries out decontamination with wafer and handles after the wet etching side wall layer, is about to wafer and passes through hydrofluoric acid treatment, sulfuric acid treatment and WITH AMMONIA TREATMENT successively, effectively reduce the impurity defect quantity on the wafer, thereby made kill rate approach zero.
Description of drawings
Fig. 1 a to Fig. 1 c is a prior art semiconductor device manufacturing process structural representation.
Impurity defect distribution map on the die that Fig. 2 catches for scanning electron microscopy.
Fig. 3 is the section of the sample under transmission electron microscope schematic diagram.
Fig. 4 is the manufacture method schematic flow sheet of preferred embodiment of the present invention semiconductor device.
Fig. 5 a is for after the semiconductor device side wall layer completes, the wafer surface scan schematic diagram when defective not being handled.
Fig. 5 b is for after the semiconductor device side wall layer completes, through the wafer surface scan schematic diagram of sulfuric acid treatment and WITH AMMONIA TREATMENT.
Fig. 5 c passes through the wafer surface scan schematic diagram of hydrofluoric acid treatment, sulfuric acid treatment and WITH AMMONIA TREATMENT successively for after the semiconductor device side wall layer completes.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Core concept of the present invention is: after the wet etching side wall layer, wafer is carried out decontamination to be handled, be about to wafer and pass through hydrofluoric acid treatment, sulfuric acid treatment and WITH AMMONIA TREATMENT successively, effectively reduced the impurity defect quantity on the wafer, thereby make kill rate approach zero.
The manufacture method schematic flow sheet of preferred embodiment of the present invention semiconductor device as shown in Figure 4, it may further comprise the steps:
Step 41, on the wafer semiconductor substrate, form grid structure;
As shown in Figure 1a: at first need on Semiconductor substrate 100, to generate grid oxic horizon 110, deposit spathic silicon layer 120 on grid oxic horizon 110 then, follow surface coated photoresistance glue-line (not shown) at described polysilicon layer 120, this photoresistance glue-line of exposure imaging patterning, the position of definition grid, photoresistance glue-line with patterning is a mask, and etch polysilicon layer 120 and grid oxic horizon 110 form grid structure successively;
Step 42, form in the both sides of grid structure and to have the side wall layer of oxide layer-nitride layer-oxide layer laminated construction, the oxide impurity defective appears in wafer surface in the wet etching process that forms side wall layer;
After removing photoresistance glue, surface at polysilicon layer 120, and the surface of Semiconductor substrate 100 deposits first oxide layer 130, nitration case 140 and second oxide layer 150 successively, dry etching first oxide layer 130, nitration case 140 then, and the part of second oxide layer 150, shown in Fig. 1 b, because dry etching is an anisotropic etching, so etching is mainly carried out in the horizontal direction, and the thickness on the reservation sidewall (vertical direction); The remainder that then adopts HF wet etching second oxide layer 150 finishes etching during to predetermined thickness, as shown in Figure 3, forms side wall layer, and formed here side wall layer is three layers of ONO laminated construction.Wherein, very fast for preventing dry etching speed, if uncontrollable etch rate when adopting dry etching second oxide layer 150 fully causes etching into Semiconductor substrate, so the part of a dry etching etching second oxide layer 150.And when finishing wet etching second oxide layer 150, still reserve certain thickness on Semiconductor substrate, when second oxide layer 150 of this predetermined thickness was injected at follow-up ion, the protection Semiconductor substrate was not subjected to ion dam age.Oxide layer in the side wall layer generally adopts TEOS and O 3Reactive deposition SiO 2Layer.
But the impurity defect that main component is an oxide appears in the above-mentioned wet etching process;
Step 43, adopt hydrofluoric acid treatment, sulfuric acid treatment and WITH AMMONIA TREATMENT to remove the oxide impurity defective of wafer surface successively.
Particularly, wafer is passed through hydrofluoric acid treatment, sulfuric acid treatment and WITH AMMONIA TREATMENT successively.Wherein, when carrying out hydrofluoric acid treatment, concentration is 49% diluted hydrofluoric acid (DHF) and the ratio of deionized water (DIW) is 100: 1; Temperature range is controlled at 22.5～23.5 degrees centigrade; Processing time is 5 seconds;
When carrying out sulfuric acid treatment, concentration is 98% sulfuric acid (H 2SO 4) and hydrogen peroxide (H 2O 2) ratio be 5: 1, temperature range is controlled at 120～130 degrees centigrade; Processing time is 10 minutes;
When carrying out WITH AMMONIA TREATMENT, ammoniacal liquor (NH 4OH) and H 2O 2With the ratio of DIW be 1: 2: 50; Temperature range is controlled at 28～32 degrees centigrade; Processing time is 420 seconds.
Through three step processing procedures, the silicon oxide impurity defective on wafer surface is dissolved in fully in the above-mentioned acid-base solution and is removed, so defects count significantly reduces successively.Because the hydrofluoric acid treatment impurity defect is very capable, so through discovering, if only pass through the wafer surface of sulfuric acid treatment and WITH AMMONIA TREATMENT,, but still can see a large amount of defectives though the wafer blemish quantity when defective not being handled reduces to some extent.Shown in Fig. 5 a, Fig. 5 b and 5c, be followed successively by the wafer surface scan schematic diagram when defective not being handled; Only pass through the wafer surface scan schematic diagram of sulfuric acid treatment and WITH AMMONIA TREATMENT; Pass through the wafer surface scan schematic diagram of hydrofluoric acid treatment, sulfuric acid treatment and WITH AMMONIA TREATMENT successively.From three figure as can be seen, wafer blemish quantity reduces successively gradually, the wafer blemish quantity of passing through hydrofluoric acid treatment, sulfuric acid treatment and WITH AMMONIA TREATMENT after the wet etching side wall layer successively is quite few, so be treated to the preferred embodiments of the present invention through three step decontaminations successively.
Need to prove, hydrofluoric acid and oxide impurity defective generation chemical reaction very capable can be removed most oxide impurity defective, so hydrofluoric acid treatment is necessary, further adopting sulfuric acid treatment and WITH AMMONIA TREATMENT, is the effect of removing impurity in order to strengthen.Therefore after the wet etching side wall layer, remove the oxide impurity defective, a kind of embodiment can be process hydrofluoric acid treatment and sulfuric acid treatment, and another kind of embodiment can realize purpose of the present invention for through hydrofluoric acid treatment and WITH AMMONIA TREATMENT.And concentration, time and temperature controlling in above-mentioned various processing procedures are all identical with numerical value in the preferred embodiment.
In sum, through decontamination processing method of the present invention, make to form after the gate lateral wall layer that impurity defect no longer appears in the wafer surface, thereby can accurately control ion implantation dosage, scrappage reduces greatly.And, in order to save cost, can after forming side wall layer, earlier wafer be detected, when finding that wafer surface has the oxide impurity defect, the processing of again wafer being removed the oxide impurity defective.Certainly, because this oxide impurity defective can be present in wafer surface inevitably,, directly after forming side wall layer, carry out the decontamination defect processing so also can wafer not detected.
The above only is preferred embodiment of the present invention, can not be in order to limit the present invention.And the thickness of the more wide region that extends with the concrete numerical value of the present invention etc., all dropping in protection scope of the present invention, those skilled in the art obviously can carry out suitable modifications and variations not breaking away from the spirit or scope of the present invention.

Claims (7)

1. the manufacture method of a semiconductor device, this method comprises:
On the wafer semiconductor substrate, form grid structure;
Has the side wall layer of oxide layer-nitride layer-oxide layer laminated construction in the formation of the both sides of grid structure;
Wafer surface is carried out hydrofluoric acid treatment.
2. the method for claim 1 is characterized in that, after forming described side wall layer, wafer surface is carried out wafer surface being detected before the hydrofluoric acid treatment, when detecting the oxide impurity defective, wafer surface is carried out hydrofluoric acid treatment.
3. the method for claim 1 is characterized in that, this method further comprises and adopts sulfuric acid treatment and WITH AMMONIA TREATMENT wafer successively after hydrofluoric acid treatment.
4. the method for claim 1 is characterized in that, this method further comprises employing sulfuric acid treatment or WITH AMMONIA TREATMENT wafer after hydrofluoric acid treatment.
5. as claim 3 or 4 described methods, it is characterized in that the method for described hydrofluoric acid treatment is:
Adopting concentration is that 49% diluted hydrofluoric acid DHF and the ratio of deionized water DIW are 100: 1; Temperature range is controlled at 22.5～23.5 degrees centigrade; Processing time is 5 seconds.
6. as claim 3 or 4 described methods, it is characterized in that the method for described sulfuric acid treatment is:
Employing concentration is 98% sulfuric acid H 2SO 4With oxydol H 2O 2Ratio be 5: 1; Temperature range is controlled at 120～130 degrees centigrade; Processing time is 10 minutes.
7. as claim 3 or 4 described methods, it is characterized in that the method for described WITH AMMONIA TREATMENT is:
Ammoniacal liquor NH 4OH and H 2O 2With the ratio of DIW be 1: 2: 50; Temperature range is controlled at 28～32 degrees centigrade; Processing time is 420 seconds.
CN 201010130286 2010-03-15 2010-03-15 Method for manufacturing semiconductor device Active CN102194679B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103346126A (en) * 2013-06-26 2013-10-09 上海宏力半导体制造有限公司 Method for forming flash memory storage unit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050136603A1 (en) * 2003-10-29 2005-06-23 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device
CN101217145A (en) * 2007-01-04 2008-07-09 台湾积体电路制造股份有限公司 Semiconductor element with selective stress memory effect and fabrication methods thereof
CN101315904A (en) * 2007-05-31 2008-12-03 联华电子股份有限公司 Production method for gate oxide layers with different thickness
CN101356650A (en) * 2006-01-12 2009-01-28 夏普株式会社 Semiconductor device and display device
CN101625996A (en) * 2008-07-08 2010-01-13 中芯国际集成电路制造(上海)有限公司 ONO side wall etching process for reducing dark current

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050136603A1 (en) * 2003-10-29 2005-06-23 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device
CN101356650A (en) * 2006-01-12 2009-01-28 夏普株式会社 Semiconductor device and display device
CN101217145A (en) * 2007-01-04 2008-07-09 台湾积体电路制造股份有限公司 Semiconductor element with selective stress memory effect and fabrication methods thereof
CN101315904A (en) * 2007-05-31 2008-12-03 联华电子股份有限公司 Production method for gate oxide layers with different thickness
CN101625996A (en) * 2008-07-08 2010-01-13 中芯国际集成电路制造(上海)有限公司 ONO side wall etching process for reducing dark current

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103346126A (en) * 2013-06-26 2013-10-09 上海宏力半导体制造有限公司 Method for forming flash memory storage unit

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