CN102185622B - Mismatch calibrating device for I and Q channel signals of orthogonal down-conversion receiver - Google Patents

Abstract

The invention discloses a mismatch calibrating device for I and Q channel signals of an orthogonal down-conversion receiver, which belongs to the technical field of frequency conversion receiver calibration. The device comprises two calibrating modules with same structures of an I channel and a Q channel, wherein each calibrating module comprises twelve MOS (Metal Oxide Semiconductor) transistors M1-M12, two load resistors R11 and R12, three adjustable resistors Rsp1, Rsp2 and Rsg and seven bias current sources I1-I7. The phase mismatch of I and Q channel signals of the orthogonal down-conversion receiver can be calibrated by adjusting resistance values of the first adjustable resistor Rsp1 and the second adjustable resistor Rsp2; and the amplitude mismatch of the I and Q channel signals of the orthogonal down-conversion receiver can be calibrated by adjusting a resistance value of the third adjustable resistor Rsg. The calibrating device improves the capability for inhibiting an image signal of the frequency conversion receiver and reduces the error rate of the receiver. A calibrating method is simple.

Description

Quadrature frequency conversion receiver I, Q channel signal mismatch calibration device

Technical field

The invention belongs to Conversion Receiver collimation technique field, particularly a kind of quadrature frequency conversion receiver I, Q channel signal mismatch calibration device.

Background technology

In modern wireless receiver, low intermediate frequency structure and zero-if architecture are widely adopted, radiofrequency signal produces homophase I, quadrature Q two paths signal through quadrature frequency conversion, through follow-up signal, processes cancellation receiver image frequency place signal, thereby has saved the image-reject filter before down-conversion.Because I, Q two paths signal exist amplitude and phase mismatch, at this moment the follow-up signal treatment circuit can't suppress image signal fully, and useful signal still can be subject to the interference of image signal, causes the error rate to rise, and reduces the performance of receiver.For low intermediate frequency receiver, because IF-FRE is non-vanishing, image signal and useful signal be not in same channel, and their energy size is unpredictable, and the image signal energy may be than the high 50-70dB of useful signal; For zero intermediate frequency reciver, image signal is exactly useful signal itself, and they have identical energy, and the requirement that receiver suppresses mirror image is more lower slightly than low intermediate frequency receiver, but the High Performance Zero intermediate-frequency receiver still needs the above mirror image inhibiting rate of 25dB.These have all proposed requirement to the coupling of I, Q two paths signal.

Consider that I, Q two paths SLM Signal Label Mismatch degree temporal evolution are slow, can adopt the method for numeral or analog circuit to be calibrated the not matching degree of I, the existence of Q channel signal, with the mismatch that reduces I, Q two paths signal, produce the impact on receiver performance.

Summary of the invention

The object of the invention is to propose a kind of quadrature frequency conversion receiver I, Q channel signal mismatch calibration device, this quadrature frequency conversion receiver I, Q channel signal mismatch calibration device are for compensating amplitude and the phase mismatch of quadrature frequency conversion receiver homophase I, quadrature Q two paths signal, increase the mirror image inhibiting rate of receiver, thereby reduce the receiver error rate, improve receiver performance.

A kind of quadrature frequency conversion receiver I, Q channel signal mismatch calibration device, it is characterized in that, described quadrature frequency conversion receiver I passage and Q passage adopt the calibration module of same structure, and calibration module comprises transistor, fixed value resistance and do the adjustable resistance of calibration use, and concrete structure is as follows:

In described I calibrate module I cal, first signal input 1 meets I passage first signal input I ' p, secondary signal input 2 meets I passage secondary signal input I ' n, and the first calibration input 3, the second calibration input 4 meet respectively the 3rd signal input Q ' p, the 4th signal input Q ' n of Q passage; The first signal output 5 of I passage meets first signal output I " p, secondary signal output 6 meet secondary signal output I " n;

In described Q calibrate module Qcal, the 3rd signal input part 7 meets Q passage the 3rd signal input Q ' p, the 4th signal input part 8 meets Q passage the 4th signal input Q ' n, the 3rd calibration input 9, the 4th calibration input 10 meet respectively I passage first signal input I ' p, I passage secondary signal input I ' n, and Q passage the 3rd signal output part 19 meets the 3rd signal output Q " p, the 4th signal output part 20 meet the 4th signal output Q " n;

Calibration module contains:

Nmos pass transistor (M1), grid connects first signal input voltage (Vip), source electrode connects the 6th bias current sources (I6) and nmos pass transistor (M12) drain electrode, and nmos pass transistor (M1) drain electrode connects secondary signal output voltage (Von);

Nmos pass transistor (M2), grid connects secondary signal input voltage (Vin), source electrode connects the 7th bias current sources (I7) and nmos pass transistor (M11) drain electrode, and nmos pass transistor (M2) drain electrode connects first signal output voltage (Vop); Connect the 3rd adjustable resistance (Rsg) between described nmos pass transistor (M1), nmos pass transistor (M2) source electrode;

PMOS transistor (M3), grid connects the first calibration input voltage (Vcalp), and source electrode connects the first bias current sources (I1), and drain electrode connects secondary signal output voltage (Von);

PMOS transistor (M4), grid connects the second calibration input voltage (Vcaln), and source electrode connects the second bias current sources (I2), and drain electrode connects first signal output voltage (Vop); Connect the first adjustable resistance (Rsp1) between PMOS transistor (M3) and PMOS transistor (M4) source electrode;

PMOS transistor (M5), grid connects the second calibration input voltage (Vcaln), and source electrode connects the 3rd bias current sources (I3), and drain electrode connects secondary signal output voltage (Von);

PMOS transistor (M6), grid connects the first calibration input voltage (Vcalp), and source electrode connects the 4th bias current sources (I4), and drain electrode connects signal first signal output voltage (Vop); Connect the second adjustable resistance (Rsp2) between PMOS transistor (M5) and PMOS transistor (M6) source electrode;

One termination secondary signal output voltage (Von) of the first load resistance (Rl1), another termination PMOS transistor (M8) grid;

One termination first signal output voltage (Vop) of the second load resistance (Rl2), another termination PMOS transistor (M8) grid;

PMOS transistor (M7), grid connects input common mode voltage (Vcm), and source electrode connects the 5th bias current sources (I5), and drain electrode connects nmos pass transistor (M10) grid and drain electrode;

PMOS transistor (M8), grid connects an end of the first load resistance (Rl1) and the second load resistance (Rl2), and source electrode connects the 5th bias current sources (I5), and drain electrode connects nmos pass transistor (M9) grid and drain electrode;

Nmos pass transistor (M9), grid is connected PMOS transistor (M8) drain electrode with drain electrode, and source electrode connects power supply (VDD);

Nmos pass transistor (M10), grid is connected PMOS transistor (M7) drain electrode and nmos pass transistor (M11), (M12) grid with drain electrode; Source electrode connects power supply (VDD);

Nmos pass transistor (M11), grid connects nmos pass transistor (M10) grid, and source electrode connects power supply (VDD), and drain electrode connects nmos pass transistor (M2) source electrode;

Nmos pass transistor (M12), grid connects nmos pass transistor (M10) grid, and source electrode connects power supply (VDD), and drain electrode connects nmos pass transistor (M1) source electrode.

Can be by the resistance value calibration quadrature frequency conversion receiver I that adjusts the first adjustable resistance Rsp1, the second adjustable resistance Rsp2, the phase mismatch of Q channel signal, by the resistance value calibration I that adjusts the 3rd adjustable resistance Rsg, the amplitude mismatch of Q channel signal.

The invention has the beneficial effects as follows the calibration that can realize quadrature frequency conversion receiver I, Q two channel signal amplitudes and phase mismatch.The input impedance approach infinity of this device, low to the requirement of front stage circuits driving force, there is high bandwidth, low noise, low-power consumption simultaneously, the adjustable amplitude range is ± 1.6dB, calibration stepping 0.2dB, adjustable phase range ± 5 °, 0.5 ° of calibration stepping.This device has good IQ channel signal mismatch calibration performance.

The accompanying drawing explanation

Fig. 1, the circuit diagram of quadrature frequency conversion receiver I, Q channel signal mismatch calibration device;

Fig. 2, quadrature frequency conversion receiver I, Q channel signal mismatch calibration device alignment module circuit diagram.

Embodiment

The present invention proposes a kind of quadrature frequency conversion receiver I, Q channel signal mismatch calibration device.Below in conjunction with accompanying drawing, the present invention is explained.

As shown in Figure 1, this calibrating installation is comprised of identical calibration module on I, Q two passages, in I calibrate module I cal, first signal input 1 meets I passage first signal input I ' p, secondary signal input 2 meets I passage secondary signal input I ' n, and the first calibration input 3, the second calibration input 4 meet respectively the 3rd signal input Q ' p, the 4th signal input Q ' n of Q passage; The first signal output 5 of I passage meets first signal output I " p, secondary signal output 6 meet secondary signal output I " n;

In Q calibrate module Qcal, the 3rd signal input part 7 meets Q passage the 3rd signal input Q ' p, the 4th signal input part 8 meets Q passage the 4th signal input Q ' n, the 3rd calibration input 9, the 4th calibration input 10 meet respectively I passage first signal input I ' p, I passage secondary signal input I ' n, and Q passage the 3rd signal output part 19 meets the 3rd signal output Q " p, the 4th signal output part 20 meet the 4th signal output Q " n;

As shown in Figure 2, calibration module is comprised of 12 MOS transistor M1-M12, two resistance R l1, Rl2, three adjustable resistance Rsp1, Rsp2, Rsg, seven bias current sources I1-I7.Annexation between them is: the signal input part differential voltage is that first signal input voltage Vip, secondary signal input voltage vin first signal input voltage Vip connect the grid of nmos pass transistor M1, the grid that the secondary signal input voltage vin meets nmos pass transistor M2, the source electrode of nmos pass transistor M1, M2 connects the 6th bias current sources I6, the 7th bias current sources I7, nmos pass transistor M11 drain electrode and nmos pass transistor M12 drain electrode, meets the 3rd adjustable resistance Rsg between nmos pass transistor M1, M2 source electrode simultaneously, calibration input differential voltage is the first calibration input voltage Vcalp, the second calibration input voltage Vcaln, the first calibration input voltage Vcalp meets PMOS transistor M3, the M6 grid, the second calibration input voltage Vcaln meets PMOS transistor M4, the M5 grid, PMOS transistor M3, M4, M5, the M6 source electrode meets respectively bias current sources the first bias current sources I1, the second bias current sources I2, the 3rd bias current sources I3, the 4th bias current sources I4, PMOS transistor M3, meet the first adjustable resistance Rsp1 between the M4 source electrode, PMOS transistor M5, meet the second adjustable resistance Rsp2 between the M6 source electrode, MOS transistor M1, M3, M5 drain electrode are joined as secondary signal output voltage V on, M2, M4, M6 drain electrode are joined as first signal output voltage V op, first signal output voltage V op and secondary signal output voltage V on form differential output signal, series load resistance R l1, Rl2 between first signal output voltage V op, secondary signal output voltage V on, the first load resistance Rl1, the second load resistance Rl2 tie point connect PMOS transistor M8 grid, input common mode voltage Vcm connects PMOS transistor M7 grid, PMOS transistor M7, M8 source electrode are connected together and join with the 5th bias current sources I5, PMOS transistor M7, M8 drain electrode connects respectively nmos pass transistor M10, M9 drain electrode, nmos pass transistor M9 grid and drain electrode are joined, source electrode meets power vd D, nmos pass transistor M10 grid and drain electrode are joined and are connect nmos pass transistor M11, M12 grid, source electrode connects power supply, and nmos pass transistor M11, M12 source electrode connect power supply.

The operation principle of this circuit is soluble as follows:

Suppose that signal I, Q are desirable orthogonal signalling, can be expressed as I=cos (ω t), Q=sin (ω t), I ', Q ' be in actual quadrature frequency conversion receiver with the orthogonal signalling of phase place and amplitude mismatch, be expressed as I '=(1+ α/2) cos (ω t+ θ/2), Q '=(1-α/2) sin (ω t-θ/2).In formula, α and θ mean amplitude and phase mismatch size, are the high-order a small amount of, through high-order, are similar to and can obtain in a small amount the writing matrix form is:

$\left[\begin{array}{c}{I}^{\′}\\ Q^{\′}\end{array}\right]=\left[\begin{array}{cc}1+\frac{\mathrm{\α}}{2}& -\frac{\mathrm{\θ}}{2}\\ -\frac{\mathrm{\θ}}{2}& 1-\frac{\mathrm{\α}}{2}\end{array}\right]\left[\begin{array}{c}I\\ Q\end{array}\right]---\left(1\right)$

Amplitude mismatch amount α in above formula and phase misalignment dosage θ, the amplitude-phase mismatch of the orthogonal local oscillation signal of input mixer in the quadrature frequency conversion receiver, and after down-conversion, amplitude and the phase mismatch of processing circuitry of intermediate frequency produces.Orthogonal signalling Image-rejection ration with mismatch can descend, thus the error rate of the receiver that raise.Calibration module need to realize the amplitude-phase calibration by the amplitude in above formula and phase deviation item α and θ elimination, thereby improves the purpose of receiver mirror image inhibiting rate, the reduction receiver error rate.If the IQ two paths of signals after calibration is I " and Q ", and meet following formula:

$\left[\begin{array}{c}{I}^{\′\′}\\ Q^{\′\′}\end{array}\right]=\left[\begin{array}{cc}1-\frac{\mathrm{\α}}{2}& \frac{\mathrm{\θ}}{2}\\ \frac{\mathrm{\θ}}{2}& 1+\frac{\mathrm{\α}}{2}\end{array}\right]\left[\begin{array}{c}{I}^{\′}\\ Q^{\′}\end{array}\right]---\left(2\right)$

Ignore the high-order of α and θ in a small amount, the signal after calibration can be expressed as:

$\left[\begin{array}{c}{I}^{\′\′}\\ Q^{\′\′}\end{array}\right]\≈\left[\begin{array}{cc}1& \\ & 1\end{array}\right]\left[\begin{array}{c}I\\ Q\end{array}\right]---\left(3\right)$

Visible, if calibrating installation meets (2) formula, can will be calibrated to desirable orthogonal signalling I, Q with actual orthogonal signalling I ', the Q ' of amplitude and phase mismatch, the mismatch of I, Q two signal paths can be eliminated.

In calibration module of the present invention, for first signal input voltage Vip, secondary signal input voltage vin, circuit forms take nmos pass transistor M1, M2 as amplifier tube, the 3rd adjustable resistance Rsg is source degeneracy resistance, the first load resistance Rl1 connects as total load resistance with the second load resistance Rl2, gains as Vo/Vi=Rl/Rsg.The resistance that wherein Rl is total load resistance, for the first calibration input voltage Vcalp, the second calibration input voltage Vcaln, circuit forms two resistance source degeneracys, the topological structure of ohmic load amplifier parallel connection, first amplifier is with PMOS transistor M3, M4 is amplifier tube, the first adjustable resistance Rsp1 is source degeneracy resistance, the first load resistance Rl1 connects as total load resistance with the second load resistance Rl2, second amplifier is with MOS transistor M5, M6 is amplifier tube, the second adjustable resistance Rsp2 is source degeneracy resistance, the first load resistance Rl1 connects as total load resistance with the second load resistance Rl2, gain can be expressed as Vo/Vcal=Rl/Rsp1-Rl/Rsp2, the resistance that wherein Rl is total load resistance.The whole output of calibration module can be expressed as:

$V_o=R_l[\frac{1}{R_{\mathrm{sg}}}{V}_i+(\frac{1}{R_{\mathrm{sp}1}}-\frac{1}{R_{\mathrm{sp}2}})V_{\mathrm{cal}}]---\left(4\right)$

In this calibrating installation, I tributary signal I ' with the amplitude-phase mismatch receives the signal input part of I branch road calibration module and the calibration input of Q branch road calibration module, with the Q tributary signal Q ' of amplitude-phase mismatch, receives the signal input part of Q branch road calibration module and the calibration input of I branch road calibration module.After output calibration, signal is I ", Q ",, according to (4) formula, output signal can be expressed as:

$\left[\begin{array}{c}{I}^{\′\′}\\ Q^{\′\′}\end{array}\right]=R_l\·\left[\begin{array}{cc}\frac{1}{R_{\mathrm{sgI}}}& \frac{1}{R_{\mathrm{sp}1I}}-\frac{1}{R_{\mathrm{sp}2I}}\\ \frac{1}{R_{\mathrm{sp}1Q}}-\frac{1}{R_{\mathrm{sp}2Q}}& \frac{1}{R_{\mathrm{sgQ}}}\end{array}\right]\left[\begin{array}{c}{I}^{\′}\\ Q^{\′}\end{array}\right]---\left(5\right)$

If RsgI=Rs0+ Δ Rsg, RsgQ=Rs0-Δ Rsg, Rsp1I=Rsp1Q=Rs0-Δ Rsp, Rsp2I=Rsp2Q=Rs0+ Δ Rsp because Rs0>>Δ Rsg, Rs0>>Δ Rsp, ignore second order in a small amount, (5) but the formula abbreviation be:

$\left[\begin{array}{c}{I}^{\′\′}\\ Q^{\′\′}\end{array}\right]=\frac{R_l}{R_{s0}}\·\left[\begin{array}{cc}1-\frac{{\mathrm{\ΔR}}_{\mathrm{sg}}}{R_{s0}}& \frac{{2\mathrm{\ΔR}}_{\mathrm{sp}}}{R_{s0}}\\ \frac{{2\mathrm{\ΔR}}_{\mathrm{sp}}}{R_{s0}}& 1+\frac{{\mathrm{\ΔR}}_{\mathrm{sg}}}{R_{s0}}\end{array}\right]\left[\begin{array}{c}{I}^{\′}\\ Q^{\′}\end{array}\right]---\left(6\right)$

From above formula, when Δ Rsg/Rs0=α/2,2 Δ Rsp/Rs0=θ/2, (6) formula can meet (2) formula that realizes that the calibration function needs meet, and this quadrature frequency conversion receiver I, Q channel signal mismatch calibration device can be realized IQ signal path phase and magnitude calibration function.

In calibration module of the present invention, MOS transistor M7-M12 and the 5th bias current sources I5 form common mode feedback circuit, can be by the first signal output voltage V of calibration module _oPwith the secondary signal output voltage V _oNbe stable at common mode input V _cM, reduce the impact of the deviation such as technological temperature on circuit performance, can be with this module connecting circuit simultaneously stable common mode input is provided.

In a word, the I proposed by us, Q channel signal calibrating installation, can be compensated the mismatch of I, Q channel signal in the quadrature frequency conversion receiver, improves the orthogonality of I, Q two channel signals, thereby improve receiver mirror image inhibiting rate, reduce the receiver error rate.

Claims (5)

1. a quadrature frequency conversion receiver I, Q channel signal mismatch calibration device, it is characterized in that, described quadrature frequency conversion receiver I passage and Q passage adopt the calibration module of same structure, calibration module comprises transistor, fixed value resistance and does the adjustable resistance of calibration use, by the resistance value calibration quadrature frequency conversion receiver I that adjusts adjustable resistance, phase place and the amplitude mismatch of Q channel signal, concrete structure is as follows:

In described I calibrate module I cal, first signal input (1) connects I passage first signal input (I ' p), secondary signal input (2) connects I passage secondary signal input (I ' n), and the first calibration input (3), the second calibration input (4) connect respectively the 3rd signal input (Q ' p), the 4th signal input (Q ' n) of Q passage; The first signal output (5) of I passage connects first signal output (I ' ' p), secondary signal output (6) and connects secondary signal output (I ' ' n);

In described Q calibrate module Qcal, the 3rd signal input part (7) connects Q passage the 3rd signal input (Q ' p), the 4th signal input part (8) and connects Q passage the 4th signal input (Q ' n), the 3rd calibration input (9), the 4th calibration input (10) connect respectively I passage first signal input (I ' p), secondary signal input (I ' n), Q passage the 3rd signal output part (19) connect the 3rd signal output (Q ' ' p), the 4th signal output part (20) connect the 4th signal output (Q ' ' n; );

Calibration module contains:

Nmos pass transistor (M1), grid connects first signal input voltage (Vip), and source electrode connects the 6th bias current sources (I6) and nmos pass transistor (M12) drain electrode, and nmos pass transistor (M1) drain electrode connects secondary signal output voltage (Von);

Nmos pass transistor (M2), grid connects secondary signal input voltage (Vin), and source electrode connects the 7th bias current sources (I7) and nmos pass transistor (M11) drain electrode, and nmos pass transistor (M2) drain electrode connects first signal output voltage (Vop); Connect the 3rd adjustable resistance (Rsg) between described nmos pass transistor (M1), nmos pass transistor (M2) source electrode;

PMOS transistor (M3), grid connects the first calibration input voltage (Vcalp), and source electrode connects the first bias current sources (I1), and drain electrode connects secondary signal output voltage (Von);

PMOS transistor (M4), grid connects the second calibration input voltage (Vcaln), and source electrode connects the second bias current sources (I2), and drain electrode connects first signal output voltage (Vop); Connect the first adjustable resistance (Rsp1) between PMOS transistor (M3) and PMOS transistor (M4) source electrode;

PMOS transistor (M5), grid connects the second calibration input voltage (Vcaln), and source electrode connects the 3rd bias current sources (I3), and drain electrode connects secondary signal output voltage (Von);

PMOS transistor (M6), grid connects the first calibration input voltage (Vcalp), and source electrode connects the 4th bias current sources (I4), and drain electrode connects signal first signal output voltage (Vop); Connect the second adjustable resistance (Rsp2) between PMOS transistor (M5) and PMOS transistor (M6) source electrode;

One termination secondary signal output voltage (Von) of the first load resistance (Rl1), another termination PMOS transistor (M8) grid;

One termination first signal output voltage (Vop) of the second load resistance (Rl2), another termination PMOS transistor (M8) grid;

PMOS transistor (M7), grid connects input common mode voltage (Vcm), and source electrode connects the 5th bias current sources (I5), and drain electrode connects nmos pass transistor (M10) grid and drain electrode;

PMOS transistor (M8), grid connects an end of the first load resistance (Rl1) and the second load resistance (Rl2), and source electrode connects the 5th bias current sources (I5), and drain electrode connects nmos pass transistor (M9) grid and drain electrode;

Nmos pass transistor (M9), grid is connected PMOS transistor (M8) drain electrode with drain electrode, and source electrode connects power supply (VDD);

Nmos pass transistor (M10), grid is connected PMOS transistor (M7) drain electrode and nmos pass transistor (M11), (M12) grid with drain electrode; Source electrode connects power supply (VDD);

Nmos pass transistor (M11), grid connects nmos pass transistor (M10) grid, and source electrode connects power supply (VDD), and drain electrode connects nmos pass transistor (M2) source electrode;

Nmos pass transistor (M12), grid connects nmos pass transistor (M10) grid, and source electrode connects power supply (VDD), and drain electrode connects nmos pass transistor (M1) source electrode.

2. quadrature frequency conversion receiver I according to claim 1, Q channel signal mismatch calibration device is characterized in that: the calibration amplitude scope is ± 1.6dB, and the calibration stepping is 0.2dB.

3. quadrature frequency conversion receiver I according to claim 1, Q channel signal mismatch calibration device is characterized in that: the calibration phase range be ± 5 °, and calibrating stepping is 0.5 °.

4. quadrature frequency conversion receiver I according to claim 1, Q channel signal mismatch calibration device, is characterized in that: MOS transistor (M7, M8, M9, M10, M11, M12) and the 5th bias current sources (I5) formation common mode feedback circuit.

5. quadrature frequency conversion receiver I according to claim 1, Q channel signal mismatch calibration device, it is characterized in that: by the resistance value calibration quadrature frequency conversion receiver I that adjusts the first adjustable resistance (Rsp1), the second adjustable resistance (Rsp2), the phase mismatch of Q channel signal, by the resistance value calibration I that adjusts the 3rd adjustable resistance (Rsg), the amplitude mismatch of Q channel signal.

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