CN102184966B - Transistor array substrate - Google Patents
Transistor array substrate Download PDFInfo
- Publication number
- CN102184966B CN102184966B CN 201110094494 CN201110094494A CN102184966B CN 102184966 B CN102184966 B CN 102184966B CN 201110094494 CN201110094494 CN 201110094494 CN 201110094494 A CN201110094494 A CN 201110094494A CN 102184966 B CN102184966 B CN 102184966B
- Authority
- CN
- China
- Prior art keywords
- those
- oxide semiconductor
- array substrate
- transistor array
- metal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
The invention relates to a transistor array substrate. The transistor array substrate comprises a substrate, a plurality of scanning lines, a plurality of data lines and a plurality of pixel units. The scanning lines and the data lines are arranged on the substrate. Each pixel unit comprises a transistor and a pixel electrode. The transistor is electrically connected with the pixel electrode, the scanning lines and the data lines. Each transistor comprises a gate electrode, a drain electrode, a source electrode, a metal oxide semiconductor layer and a channel protection layer. A channel gap is reserved between the drain electrode and the source electrode. The metal oxide semiconductor layer is provided with a pair of side edges opposite to each other, and the side edges are positioned at two ends of the channel gap. The channel protection layer covers the metal oxide semiconductor layer in the channel gap, and is protruded out of the side edges of the metal oxide semiconductor layer. By the transistor array substrate, a metal oxide semiconductor can be prevented from being influenced by the gas for processing.
Description
Technical field
The present invention relates to a kind of assembly of display, and particularly relevant for a kind of transistor array substrate.
Background technology
A kind of liquid crystal display (Liquid Crystal Display, LCD) with metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor, MOS) has appearred at present.The thin-film transistor that this liquid crystal display has (Thin Film Transistor, TFT), its semiconductor layer is made by metal-oxide semiconductor (MOS).Yet in the general processing procedure of this liquid crystal display, metal-oxide semiconductor (MOS) easily is subject to the gas that processing procedure is used, hydrogen for example, affect and become conductor.So, thin-film transistor can lose switching function, causes normally show image of liquid crystal display.
Summary of the invention
In view of the deficiencies in the prior art, the object of the present invention is to provide a kind of transistor array substrate, avoid being affected by the gas that processing procedure is used with the protection metal-oxide semiconductor (MOS).
To achieve these goals, technical scheme of the present invention is: a kind of transistor array substrate, it is characterized in that, and comprising: a substrate; Multi-strip scanning line and many data wires all are configured on this substrate, and interlaced with each other; A plurality of pixel cells, respectively this pixel cell comprises a transistor AND gate one pixel electrode, respectively this transistor comprises: a grid is disposed on this substrate, and is electrically connected wherein this scan line; One drain electrode is electrically connected wherein this pixel electrode; One source pole is electrically connected wherein this data wire, wherein has a path clearance between this drain electrode and this source electrode; One metal oxide semiconductor layer is disposed between this grid and this drain electrode, and between this grid and this source electrode, and has a pair of lateral edges, and wherein those lateral edges and are positioned at two end places of this path clearance toward each other; One channel protective layer covers this metal oxide semiconductor layer in this path clearance, and protrudes from those lateral edges of this metal oxide semiconductor layer; And a plurality of the first neonychiums; be disposed between those scan lines and those data wires; and lay respectively at the staggered place of those scan lines and those data wires; wherein respectively this first neonychium comprises one first bed course and one second bed course, and those first bed courses are between those second bed courses and those scan lines.
In an embodiment of the present invention, the material of this metal oxide semiconductor layer is indium gallium zinc oxide semiconductor (InGaZnO, IGZO) or indium tin zinc oxide semiconductor (In-Sn-Zn-O, ITZO).
In an embodiment of the present invention, the material of those the first bed courses is identical with the material of those metal oxide semiconductor layers.
In an embodiment of the present invention, the material of those the second bed courses is identical with the material of those channel protective layer.
In an embodiment of the present invention, the material of this channel protective layer is silicon compound or silicon.
In an embodiment of the present invention, in this transistor respectively, local this metal oxide semiconductor layer that covers of this channel protective layer, and should drain electrode and local this metal oxide semiconductor layer that covers of this source electrode.
In an embodiment of the present invention; this transistor array substrate more comprises many common lines and a plurality of the second neonychium; those common lines all are configured on this substrate; and be positioned at the below of those pixel electrodes; wherein those common lines and those scan lines are arranged side by side; and interlaced with each other with those data wires, those second neonychiums are disposed between those common lines and those data wires, and lay respectively at the staggered place of those common lines and those data wires.
In an embodiment of the present invention, those second neonychiums more are disposed between those common lines and those pixel electrodes.
In an embodiment of the present invention, respectively this second neonychium comprises one the 3rd bed course and one the 4th bed course, and those the 3rd bed courses are between those the 4th bed courses and those common lines.
In an embodiment of the present invention, the material of those the 3rd bed courses is identical with the material of those metal oxide semiconductor layers.
In an embodiment of the present invention, the material of those the 4th bed courses is identical with the material of those channel protective layer.
In an embodiment of the present invention, wherein those the 4th bed courses cover those the 3rd bed courses and those common lines fully.
In an embodiment of the present invention, wherein in this transistor respectively, this channel protective layer covers this metal oxide semiconductor layer fully, and this drain electrode and this source electrode all cover this channel protective layer.
In an embodiment of the present invention, this transistor array substrate more comprises a gate protection layer, and this gate protection layer is disposed between those grids and those metal-oxide semiconductor (MOS)s, and those grids of comprehensive covering.
In an embodiment of the present invention, this transistor array substrate more comprises an insulating barrier, and respectively this pixel cell comprises a conductive pole, this insulating barrier is between those pixel electrodes of those transistor AND gates, and those conductive poles are disposed in this insulating barrier, and are connected between those pixel electrodes and those drain electrodes.
Advantage of the present invention: because channel protective layer covers the metal oxide semiconductor layer in the raceway groove gap; and protrude from the dual side-edge edge of metal oxide semiconductor layer; separate with source electrode thereby will drain; therefore channel protective layer can make gas-insulated that the metal oxide semiconductor layer raceway groove gap in and processing procedure use, and then protects metal-oxide semiconductor (MOS) to avoid being affected by the gas that processing procedure is used.
Description of drawings
Figure 1A is the schematic top plan view of the transistor array substrate of first embodiment of the invention.
Figure 1B is the generalized section that I-I section along the line illustrates among Figure 1A.
Fig. 1 C is the generalized section that J-J section along the line illustrates among Figure 1A.
Fig. 2 A is the schematic top plan view of the transistor array substrate of second embodiment of the invention.
Fig. 2 B is the generalized section that K-K section along the line illustrates among Fig. 2 A.
Fig. 2 C is the generalized section that L-L section along the line illustrates among Fig. 2 A.
[primary clustering symbol description]
100,200 transistor array substrates
110 substrates
The 120c common lines
The 120d data wire
The 120s scan line
130,230 pixel cells
132,232 transistors
The 132c metal oxide semiconductor layer
The 132d drain electrode
The 132g grid
132p, 232p channel protective layer
The 132s source electrode
134 pixel electrodes
136 conductive poles
140 insulating barriers
150 gate protection layers
160,260 first neonychiums
162 first bed courses
164,264 second bed courses
170,270 second neonychiums
172 the 3rd bed courses
174,274 the 4th bed courses
The E1 lateral edges
The E2 end
The G1 path clearance.
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and be described in detail below by reference to the accompanying drawings.
Figure 1A is the schematic top plan view of the transistor array substrate of first embodiment of the invention, and Figure 1B is the generalized section that I-I section along the line illustrates among Figure 1A.See also Figure 1A and Figure 1B, the transistor array substrate 100 of the first embodiment comprises a substrate 110, multi-strip scanning line 120s, many data wire 120d and a plurality of pixel cell 130, and wherein these scan lines 120s, these data wires 120d and these pixel cells 130 all are configured on the substrate 110.
These scan lines 120s and these data wires 120d are interlaced with each other, wherein these scan lines 120s is arranged side by side each other, and these data wires 120d is arranged side by side each other, so that these scan lines 120s and these data wires 120d are netted arrangement, be that these scan lines 120s and these data wires 120d can form network structure, shown in Figure 1A.In addition, in the present embodiment, these data wires 120d all can be positioned at the top of these scan lines 120s.
Each pixel cell 130 comprises a transistor 132 and a pixel electrode 134, and wherein each transistor 132 is electrically connected a pixel electrode 134, a scan line 120s and a data wire 120d.Specifically, these transistors 132 all can be field-effect transistor (Field-Effect Transistor, FET), so each transistor 132 comprises a grid 132g, drain electrode 132d, one source pole 132s and a metal oxide semiconductor layer 132c.In addition, the material of metal oxide semiconductor layer 132c can be indium gallium zinc oxide semiconductor or indium tin zinc oxide semiconductor.
In each transistor 132, metal oxide semiconductor layer 132c be disposed at grid 132g and the drain electrode 132d between, with and gate pole 132g and source electrode 132s between, as shown in Figure 1B.Therefore, source electrode 132s and all local covering metal oxide semiconductor layer of drain electrode 132d 132c.In addition, each metal oxide semiconductor layer 132c has a pair of lateral edges E1.These lateral edges E1 and is positioned at the two end E2 places of path clearance G1 toward each other.
Each grid 132g is disposed on the substrate 110, and is electrically connected wherein scan line 120s.Each drain electrode 132d is electrically connected one of them pixel electrode 134, and each source electrode 132s is electrically connected wherein data wire 120d, wherein draining has a path clearance G1 between 132d and the source electrode 132s, so these drain electrodes 132d can directly not connect these source electrodes 132s.
Each pixel cell 130 can more comprise a conductive pole 136, and these drain electrodes 132d can be electrically connected one of them pixel electrode 134 through these conductive poles 136, and wherein these conductive poles 136 are connected between these pixel electrodes 134 and these drain electrodes 132d.Transistor array substrate 100 can comprise more that an insulating barrier 140(as shown in Figure 1B), wherein insulating barrier 140 can be between these transistors 132 and these pixel electrodes 134, and cover these transistors 132, and these conductive poles 136 all are disposed in the insulating barrier 140.
Hold above-mentioned, the material of insulating barrier 140 can be silica, silicon dioxide for example, and insulating barrier 140 can be to see through chemical vapour deposition technique (Chemical Vapor Deposition, CVD) form, wherein this chemical vapour deposition technique for example is plasma enhanced chemical vapor deposition method (Plasma-Enhanced CVD, PECVD), the processing procedure material that it adopts can comprise that (silane, chemical formula are SiH to silane
4).In addition, when insulating barrier 140 is when forming with above-mentioned plasma enhanced chemical vapor deposition method, silane can decomposite hydrogen.
Each transistor 132 more comprises a channel protective layer 132p, and the material of channel protective layer 132p is silicon compound, and it for example is silica or silicon nitride, and wherein this silica can be silicon dioxide.In each transistor 132; the local covering metal oxide semiconductor layer 132c of channel protective layer 132p meeting; and cover the metal oxide semiconductor layer 132c in the path clearance G1; wherein channel protective layer 132p can protrude from these lateral edges E1 of metal oxide semiconductor layer 132c, so each channel protective layer 132p can separate drain electrode 132d and the source electrode 132s of same transistor 132.
In the processing procedure of transistor array substrate 100; these channel protective layer 132p can be used as shielding; and the gas (for example decomposing and next hydrogen from silane) that the interior metal oxide semiconductor layer 132c of path clearance G1 and processing procedure are used is isolated; therefore channel protective layer 132p can prevent that the metal oxide semiconductor layer 132c in the path clearance G1 from becoming conductor, so that transistor 132 is possessed switching function.So, when transistor 132 is applied to transistor array substrate 100, can impel normally show image of liquid crystal display.
In addition, transistor array substrate 100 can more comprise a gate protection layer 150, and as shown in Figure 1B, and the material of gate protection layer 150 for example is silicon nitride or silica (for example silicon dioxide).Gate protection layer 150 is disposed between these grids 132g and these metal oxide semiconductor layers 132c, and is positioned on the substrate 110, wherein gate protection layer 150 these grids of comprehensive covering 132g.
Fig. 1 C is the generalized section that J-J section along the line illustrates among Figure 1A.See also Figure 1A and Fig. 1 C, each first neonychium 160 has sandwich construction.Specifically; each first neonychium 160 can comprise one first bed course 162 and one second bed course 164; wherein these first bed courses 162 are between these second bed courses 164 and these scan lines 120s; and the first bed course 162 can be disposed on the gate protection layer 150, and namely the first neonychium 160 can be positioned on the gate protection layer 150.
See also Figure 1B and Fig. 1 C, in the present embodiment, these first bed courses 162 are formed by the same layer rete with these metal oxide semiconductor layers 132c, and the method that wherein forms the first bed course 162 and metal oxide semiconductor layer 132c can comprise little shadow (photolithography) and etching (etching).Therefore, the material of the first bed course 162 can be identical with the material of metal oxide semiconductor layer 132c, and namely the material of the first bed course 162 can be indium gallium zinc oxide semiconductor or indium tin zinc oxide semiconductor.
In addition, these second bed courses 164 are formed by the same layer rete with these channel protective layer 132p, and the method that wherein forms the second bed course 164 and channel protective layer 132p can comprise little shadow and etching.Therefore, the material of the second bed course 164 can be identical with the material of channel protective layer 132p, and namely the material of the second bed course 164 can be the silicon compounds such as silica (such as silicon dioxide) or silicon nitride.
See also Figure 1A and Figure 1B, transistor array substrate 100 can more comprise many common lines 120c and a plurality of the second neonychium 170.Common lines 120c and the second neonychium 170 all are configured on the substrate 110, and common lines 120c is positioned at the below of pixel electrode 134.These common lines 120c and these scan lines 120s are arranged side by side, and interlaced with each other with these data wires 120d.
These second neonychiums 170 are disposed between these common lines 120c and these data wires 120d; and lay respectively at the staggered place of these common lines 120c and these data wires 120d, wherein these second neonychiums 170 more are disposed between these common lines 120c and these pixel electrodes 134.
Each second neonychium 170 has sandwich construction.Specifically; each second neonychium 170 comprises one the 3rd bed course 172 and one the 4th bed course 174; and these the 3rd bed courses 172 are between these the 4th bed courses 174 and these common lines 120c; and the 3rd bed course 172 can be disposed on the gate protection layer 150, so the second neonychium 170 can be positioned on the gate protection layer 150.In addition, these the 4th bed courses 174 can cover these the 3rd bed courses 172 and these common lines 120c fully.
In the present embodiment, these the 3rd bed courses 172 are formed by the same layer rete with these metal oxide semiconductor layers 132c, and the method that forms the 3rd bed course 172 and metal oxide semiconductor layer 132c can comprise little shadow and etching.Therefore, the material of the 3rd bed course 172 can be identical with the material of metal oxide semiconductor layer 132c, so the material of the 3rd bed course 172 can be indium gallium zinc oxide semiconductor or indium tin zinc oxide semiconductor.
These the 4th bed courses 174 are formed by the same layer rete with these channel protective layer 132p, and the method that wherein forms the 4th bed course 174 and channel protective layer 132p can comprise little shadow and etching.Therefore, the material of the 4th bed course 174 can be identical with the material of channel protective layer 132p, and namely the material of the 4th bed course 174 can be the silicon compounds such as silica (such as silicon dioxide) or silicon nitride.
It is worth mentioning that, the etching solution that generally is used for etching oxidation silicon also can injure silicon nitride.When the material of gate protection layer 150 is silicon nitride; and the material of the 4th bed course 174 is when being silica (for example silicon dioxide); the gate protection layer 150 that is positioned at these common lines 120c edge has comparatively weak structure, so the etching solution of easy etched silica destroys.
Yet; because the 4th bed course 174 covers the 3rd bed course 172 and common lines 120c fully; and the method that forms the 4th bed course 174 comprises little shadow; therefore in the process that forms these the 4th bed courses 174, will inevitably form the photoresist layer (not illustrating) that hides common lines 120c fully at gate protection layer 150.So, be positioned at common lines 120c edge gate protection layer 150 in order to avoid suffer the destruction of etching solution, and the 4th bed course 174 is covered common lines 120c fully.
Fig. 2 A is the schematic top plan view of the transistor array substrate of second embodiment of the invention, and Fig. 2 B is the generalized section that K-K section along the line illustrates among Fig. 2 A.See also Fig. 2 A and Fig. 2 B; the transistor array substrate 200 of the second embodiment is similar to transistor array substrate 100, and for example transistor array substrate 200 also comprises substrate 110, multi-strip scanning line 120s, many data wire 120d, many common lines 120c, insulating barrier 140 and gate protection layers 150.Below will be elaborated mainly for transistor array substrate 100,200 the two differences, no longer repeat to introduce the two identical technical characterictic.
Transistor array substrate 100,200 the two Main Differences are: a plurality of pixel cells 230, a plurality of the first neonychium 260 and a plurality of the second neonychium 270 that transistor array substrate 200 is included.Each pixel cell 230 comprises a transistor 232, a pixel electrode 134 and a conductive pole 136, and each transistor 232 comprises a grid 132g, drain electrode 132d, one source pole 132s, a metal oxide semiconductor layer 132c and a channel protective layer 232p.
In each transistor 232, grid 132g, drain electrode 132d, source electrode 132s and metal oxide semiconductor layer 132c relative position each other all are same as the first embodiment, therefore no longer repeat to introduce.Yet the material of channel protective layer 232p but is different from the material of the channel protective layer 232p of the first embodiment.Specifically, the material of channel protective layer 232p is silicon, and it for example is amorphous silicon (amorphous silicon).
In each transistor 232; the complete covering metal oxide semiconductor layer of channel protective layer 232p 132c; therefore channel protective layer 232p not only covers the metal oxide semiconductor layer 132c in the path clearance G1, and protrudes from these lateral edges E1 of metal oxide semiconductor layer 132c.In addition, drain electrode 132d and source electrode 132s all cover channel protective layer 232p, shown in Fig. 2 B.
Based on above-mentioned; in the processing procedure of transistor array substrate 200; because the complete covering metal oxide semiconductor layer of channel protective layer 232p 132c; therefore channel protective layer 232p can be used as shielding, and the gas (for example decomposing and next hydrogen from silane) that metal oxide semiconductor layer 132c and processing procedure are used is isolated.So, channel protective layer 232p can prevent that metal oxide semiconductor layer 132c from becoming conductor, so that transistor 232 is possessed switching function, impels the liquid crystal display show image normally that adopts transistor array substrate 200.
In addition; these first neonychiums 260 are disposed between these scan lines 120s and these data wires 120d; and lay respectively at the staggered place of these scan lines 120s and these data wires 120d; and these second neonychiums 270 are disposed between these common lines 120c and these data wires 120d, and lay respectively at the staggered place of these common lines 120c and these data wires 120d.
Fig. 2 C is the generalized section that L-L section along the line illustrates among Fig. 2 A.See also Fig. 2 A to Fig. 2 C, each first neonychium 260 comprises one first bed course 162 and one second bed course 264, and each second neonychium 270 comprises one the 3rd bed course 172 and one the 4th bed course 274.These first bed courses 162 are between these second bed courses 264 and these scan lines 120s; and these the 3rd bed courses 172 are between these the 4th bed courses 274 and these common lines 120c, and wherein these first bed courses 162 all can be disposed on the gate protection layer 150 with these the 3rd bed courses 172.
In the present embodiment, the second bed course 264, the 4th bed course 274 and channel protective layer 232p are formed by the same layer rete, and form the second bed course 264, the 4th bed course 274 can comprise little shadow and etching with the method for channel protective layer 232p.Therefore, the two material of the second bed course 264 and the 4th bed course 274 all can be same as the material of channel protective layer 232p, and namely the two material of the second bed course 264 and the 4th bed course 274 can be silicon (for example amorphous silicon).
General not conference of the etching solution injury silicon nitride that is used for etching silicon.So when the material of gate protection layer 150 is silicon nitride, and the material of the 4th bed course 274 is when being silicon (for example amorphous silicon), the etching solution of etching silicon can't destroy gate protection layer 150 in fact.Therefore, be different from the first embodiment, in the etching process that carries out the 4th bed course 274, even do not keep the 4th bed course 274 directly over the common lines 120c, gate protection layer 150 can't be damaged in fact.In other words, in the present embodiment, the 4th bed course 274 need not cover common lines 120c fully, shown in Fig. 2 A.
In sum, in transistor array substrate of the present invention, the included channel protective layer of each transistor covers the metal oxide semiconductor layer in the raceway groove gap, and protrudes from the dual side-edge edge of metal oxide semiconductor layer, separates with source electrode thereby will drain.Therefore, it is isolated that channel protective layer can make the gas that metal oxide semiconductor layer in the raceway groove gap and processing procedure use (for example decomposing and the hydrogen that comes from silane).So, channel protective layer can protect metal-oxide semiconductor (MOS) to avoid being affected by the gas that processing procedure is used, and impels the liquid crystal display show image normally that adopts transistor array substrate of the present invention.
Although the present invention discloses as above with previous embodiment, so it is not to limit the present invention, anyly has the knack of alike skill person, and without departing from the spirit and scope of the present invention, institute does to change and the equivalence replacement of retouching, and still is in the scope of patent protection of the present invention.
Claims (15)
1. a transistor array substrate is characterized in that, comprising:
One substrate;
Multi-strip scanning line and many data wires all are configured on this substrate, and interlaced with each other;
A plurality of pixel cells, respectively this pixel cell comprises a transistor AND gate one pixel electrode, respectively this transistor comprises:
One grid is disposed on this substrate, and is electrically connected wherein this scan line;
One drain electrode is electrically connected wherein this pixel electrode;
One source pole is electrically connected wherein this data wire, wherein has a path clearance between this drain electrode and this source electrode;
One metal oxide semiconductor layer is disposed between this grid and this drain electrode, and between this grid and this source electrode, and has a pair of lateral edges, and wherein those lateral edges and are positioned at two end places of this path clearance toward each other;
One channel protective layer covers this metal oxide semiconductor layer in this path clearance, and protrudes from those lateral edges of this metal oxide semiconductor layer; And
A plurality of the first neonychiums; be disposed between those scan lines and those data wires; and lay respectively at the staggered place of those scan lines and those data wires; wherein respectively this first neonychium comprises one first bed course and one second bed course, and those first bed courses are between those second bed courses and those scan lines.
2. transistor array substrate according to claim 1, it is characterized in that: the material of this metal oxide semiconductor layer is indium gallium zinc oxide semiconductor or indium tin zinc oxide semiconductor.
3. transistor array substrate according to claim 1, it is characterized in that: the material of those the first bed courses is identical with the material of those metal oxide semiconductor layers.
4. transistor array substrate according to claim 1, it is characterized in that: the material of those the second bed courses is identical with the material of those channel protective layer.
5. transistor array substrate according to claim 1, it is characterized in that: the material of this channel protective layer is silicon compound or silicon.
6. transistor array substrate according to claim 1 is characterized in that: in this transistor respectively, and local this metal oxide semiconductor layer that covers of this channel protective layer, and should drain electrode and local this metal oxide semiconductor layer that covers of this source electrode.
7. transistor array substrate according to claim 1; it is characterized in that: more comprise many common lines and a plurality of the second neonychium; those common lines all are configured on this substrate; and be positioned at the below of those pixel electrodes; wherein those common lines and those scan lines are arranged side by side; and interlaced with each other with those data wires, those second neonychiums are disposed between those common lines and those data wires, and lay respectively at the staggered place of those common lines and those data wires.
8. transistor array substrate according to claim 7, it is characterized in that: those second neonychiums more are disposed between those common lines and those pixel electrodes.
9. transistor array substrate according to claim 7, it is characterized in that: respectively this second neonychium comprises one the 3rd bed course and one the 4th bed course, and those the 3rd bed courses are between those the 4th bed courses and those common lines.
10. transistor array substrate according to claim 9, it is characterized in that: the material of those the 3rd bed courses is identical with the material of those metal oxide semiconductor layers.
11. transistor array substrate according to claim 9 is characterized in that: the material of those the 4th bed courses is identical with the material of those channel protective layer.
12. transistor array substrate according to claim 9 is characterized in that: those the 4th bed courses cover those the 3rd bed courses and those common lines fully.
13. transistor array substrate according to claim 1 is characterized in that: in this transistor respectively, this channel protective layer covers this metal oxide semiconductor layer fully, and this drain electrode and this source electrode all cover this channel protective layer.
14. transistor array substrate according to claim 1 is characterized in that: more comprise a gate protection layer, this gate protection layer is disposed between those grids and those metal-oxide semiconductor (MOS)s, and those grids of comprehensive covering.
15. transistor array substrate according to claim 1, it is characterized in that: more comprise an insulating barrier, and respectively this pixel cell comprises a conductive pole, this insulating barrier is between those pixel electrodes of those transistor AND gates, and those conductive poles are disposed in this insulating barrier, and are connected between those pixel electrodes and those drain electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110094494 CN102184966B (en) | 2011-04-15 | 2011-04-15 | Transistor array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110094494 CN102184966B (en) | 2011-04-15 | 2011-04-15 | Transistor array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102184966A CN102184966A (en) | 2011-09-14 |
| CN102184966B true CN102184966B (en) | 2013-02-13 |
Family
ID=44571105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110094494 Expired - Fee Related CN102184966B (en) | 2011-04-15 | 2011-04-15 | Transistor array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102184966B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102636926A (en) * | 2011-11-02 | 2012-08-15 | 深圳市华星光电技术有限公司 | Liquid display panel and manufacturing method thereof |
| CN104124253A (en) * | 2013-05-23 | 2014-10-29 | 深超光电（深圳）有限公司 | Thin film transistor substrate |
| CN106371253A (en) * | 2016-08-26 | 2017-02-01 | 武汉华星光电技术有限公司 | Array substrate, liquid crystal display panel and manufacturing method |
| CN113985669B (en) | 2021-10-27 | 2022-09-27 | Tcl华星光电技术有限公司 | Array substrate and display panel |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101189271B1 (en) * | 2005-07-12 | 2012-10-09 | 삼성디스플레이 주식회사 | Thin film transistor array panel and method for manufacturing the same |
| CN100521166C (en) * | 2007-11-15 | 2009-07-29 | 友达光电股份有限公司 | Indicator element and manufacturing method therefor |
| JP2009302273A (en) * | 2008-06-13 | 2009-12-24 | Sony Corp | Semiconductor device, manufacturing method of semiconductor device, display, and electronic apparatus |
| TWI622175B (en) * | 2008-07-31 | 2018-04-21 | 半導體能源研究所股份有限公司 | Semiconductor device |
-
2011
- 2011-04-15 CN CN 201110094494 patent/CN102184966B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN102184966A (en) | 2011-09-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10269973B2 (en) | TFT backplane and manufacturing method thereof | |
| US10297694B2 (en) | Semiconductor device and method for manufacturing same | |
| KR101832361B1 (en) | Thin film transistor array panel | |
| CN102184966B (en) | Transistor array substrate | |
| KR20120063809A (en) | Thin film transistor array panel | |
| TWI481035B (en) | Thin film transistor and array substrate including the same | |
| US20150034943A1 (en) | Thin film transistor array substrate | |
| US9165947B2 (en) | Semiconductor device, TFT, capacitor and method of manufacturing the same | |
| JPWO2012117695A1 (en) | Manufacturing method of semiconductor device | |
| US20130134514A1 (en) | Thin film transistor and method for fabricating the same | |
| CN105097829A (en) | Array substrate and preparation method thereof | |
| CN109119427B (en) | Manufacturing method of back channel etching type TFT substrate and back channel etching type TFT substrate | |
| KR20160120394A (en) | Thin film transistor array panel and method for manufacturing the same | |
| CN108490707B (en) | Array substrate and display panel | |
| CN103579357A (en) | Semiconductor structure | |
| US9117912B2 (en) | IGZO transistor structure and manufacturing method for the same | |
| JP2012114245A (en) | Thin-film transistor, electrode substrate for display device, and manufacturing methods thereof | |
| US9373589B2 (en) | Display substrate and manufacturing method thereof as well as display device | |
| TWI459563B (en) | Transistor array substrate | |
| CN105762161B (en) | Method for manufacturing light sensing unit of light sensing array and structure thereof | |
| JP2015056566A (en) | Thin film transistor, electrode substrate for display device and manufacturing methods of those | |
| US9653488B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN104465784A (en) | Thin film transistor and display panel | |
| JP6262477B2 (en) | THIN FILM TRANSISTOR, ELECTRODE SUBSTRATE FOR DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME | |
| US10553614B2 (en) | Thin-film transistor array substrate and manufacturing method for the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130213 Termination date: 20190415 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |