CN102184865A - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN102184865A CN102184865A CN201110095235XA CN201110095235A CN102184865A CN 102184865 A CN102184865 A CN 102184865A CN 201110095235X A CN201110095235X A CN 201110095235XA CN 201110095235 A CN201110095235 A CN 201110095235A CN 102184865 A CN102184865 A CN 102184865A
- Authority
- CN
- China
- Prior art keywords
- semiconductor layer
- oxide
- film transistor
- patterning
- oxide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a thin film transistor and a manufacturing method thereof. The manufacturing method comprises the following steps of: forming a source electrode and a drain electrode which are mutually insulated on a substrate; forming a patterned oxide semiconductor layer and a pixel semiconductor layer on the substrate at the same time; forming a patterned etched barrier layer on the oxide semiconductor layer, and exposing a part of patterned oxide semiconductor layer positioned on the two sides of the patterned etched barrier layer; forming a gate insulating layer on the substrate; forming the part of patterned oxide semiconductor layer exposed by the patterned etched barrier layer into two ohmic contact layers and forming the pixel semiconductor layer into a pixel electrode at the same time in the process of forming the gate insulating layer; and forming a gate electrode on the gate insulating layer above the patterned oxide semiconductor layer.
Description
Technical field
The invention relates to a kind of thin-film transistor and manufacture method thereof, and particularly relevant for a kind of thin-film transistor and manufacture method thereof with oxide semiconductor layer.
Background technology
Recently environmental consciousness comes back, and the display panels (Liquid crystal display panels) with advantageous characteristic such as low consumpting power, space utilization efficient are good, radiationless, high image quality has become the market mainstream.
In the past, display panels adopt mostly amorphous silicon (
a-Si) thin-film transistor or low temperature polycrystalline silicon (Low-temperature polysilicon, LTPS) thin-film transistor is as the switch module of each image element structure.Yet in recent years, existing research is pointed out: compared to amorphous silicon film transistor, oxide semiconductor (oxide semiconductor) thin-film transistor has higher carrier mobility (mobility); And compared to low-temperature polysilicon film transistor, oxide semiconductor thin-film transistor has preferable critical voltage (threshold voltage, Vth) uniformity.Therefore, the potential key component that becomes flat-panel screens of future generation of oxide semiconductor thin-film transistor.
Generally speaking, the manufacturing process of oxide semiconductor thin-film transistor roughly can use seven road light shield processing procedures.At first, use the first road light shield processing procedure, on substrate, form gate.Then, on substrate, form the lock insulating barrier to cover gate comprehensively.Then, use the second road light shield processing procedure, on the lock insulating barrier of gate top, form oxide semiconductor layer.Come again, use the 3rd road light shield processing procedure, on the oxide semiconductor layer of part, form etch stop layer.Then, on lock insulating barrier, oxide semiconductor layer and etch stop layer, form dielectric layer, and carry out hydrogen doping and make it be transformed into two ohmic contact layers for the oxide semiconductor layer that is positioned at the etch stop layer both sides.Afterwards, utilize the 4th road light shield processing procedure, in the dielectric layer of two ohmic contact layers top, form two openings, and expose two ohmic contact layers respectively.Come again, utilize the 5th road light shield processing procedure, on dielectric layer, form source electrode and the drain be electrically insulated each other, and source electrode and drain are inserted respectively in two openings and be connected with two ohmic contact layers.Then, on substrate, form insulating barrier to cover source electrode and drain.Afterwards, utilize the 6th road light shield processing procedure, on insulating barrier, form contact window to expose drain.At last, utilize the 7th road light shield, form pixel electrode on substrate, this pixel electrode is inserted contact window and is electrically connected with drain.In this, just finish the making of known oxide semiconductor thin-film transistor.Yet, the complicated and cost of manufacture height of the manufacturing process of above-mentioned oxide semiconductor thin-film transistor.
Summary of the invention
In view of this, the invention provides a kind of method of manufacturing thin film transistor, can simplify the processing procedure of thin-film transistor and reduce cost of manufacture.
The present invention also provides a kind of thin-film transistor, and it is low to have simple structure and cost of manufacture.
The invention provides a kind of method of manufacturing thin film transistor.On substrate, form source electrode and the drain that is electrically insulated each other.Form patterning oxide semiconductor layer and picture element semiconductor layer on substrate simultaneously, wherein, the patterning oxide semiconductor layer is between source electrode and drain, and the picture element semiconductor layer is positioned at the pixel electrode presumptive area.Form the pattern etched barrier layer on the patterning oxide semiconductor layer, the pattern etched barrier layer exposes the patterning oxide semiconductor layer of the part that is positioned at both sides, pattern etched barrier layer.On substrate, form the lock insulating barrier, in the process that forms the lock insulating barrier, make simultaneously and be patterned the partially patterned oxide semiconductor layer that etch stop layer exposes and form two ohmic contact layers and make the picture element semiconductor layer that is positioned at the picture element presumptive area form pixel electrode, pixel electrode and drain electrically connect, and two ohmic contact layers electrically connect with source electrode and drain respectively.On the lock insulating barrier of patterning oxide semiconductor layer top, form gate.
The invention provides a kind of thin-film transistor, comprising: source electrode, drain, patterning oxide semiconductor layer, pattern etched barrier layer, lock insulating barrier, gate and pixel electrode.The patterning oxide semiconductor layer is between source electrode and drain, and the patterning oxide semiconductor layer has two ohmic contact layers.The pattern etched barrier layer is positioned on the patterning oxide semiconductor layer and exposes ohmic contact layer.Lock insulating barrier overlay pattern etch stop layer and patterning oxide semiconductor layer.Gate is positioned on the lock insulating barrier of patterning oxide semiconductor layer top.Pixel electrode electrically connects drain via ohmic contact layer, wherein, pixel electrode, patterning oxide semiconductor layer are the identical rete in position with ohmic contact layer, and pixel electrode is identical with the material of ohmic contact layer.
In one embodiment of this invention, the material of above-mentioned picture element semiconductor layer and patterning oxide semiconductor layer is identical and be selected from: indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), indium oxide gallium (IGO), tin oxide (ZnO), cadmium oxide, germanium oxide (2CdOGeO
2), cobalt nickel oxide (NiCo
2O
4) and combination.
In one embodiment of this invention, the above-mentioned formation ohmic contact layer and the method for pixel electrode comprise: when forming the lock insulating barrier, carry out hydrogen doping for patterning oxide semiconductor layer and picture element semiconductor.
In one embodiment of this invention, the above-mentioned ohmic contact layer and the material of pixel electrode are to be selected from hydrogeneous indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), indium oxide gallium (IGO), tin oxide (ZnO), cadmium oxide, germanium oxide (2CdOGeO
2), cobalt nickel oxide (NiCo
2O
4) and combination.
In one embodiment of this invention, above-mentioned method for fabricating thin film transistor more comprises: when forming the source electrode be electrically insulated each other on the substrate, on substrate, form data wire with drain, and data wire and source electrode electric connection.
In one embodiment of this invention, above-mentioned method for fabricating thin film transistor more comprises: when forming gate on the lock insulating barrier of patterning oxide semiconductor layer top, on substrate, form scan line, and scan line and gate electric connection.
In one embodiment of this invention, above-mentioned method of manufacturing thin film transistor more comprises: form on the lock insulating barrier of patterning oxide semiconductor layer top after the gate, form the patterning protective layer on substrate.The patterning protective layer has a plurality of contact windows, and contact window exposes the end of scan line of thin-film transistor and the end of data line, provides the source so that scan line and data wire are electrically connected to the external drive signal via contact window.
In one embodiment of this invention, the material of above-mentioned source electrode, drain and gate comprises: the metal of single rete or the metal of composite film.
Based on above-mentioned, in thin-film transistor of the present invention and manufacture method thereof, in the time of by formation lock insulating barrier, ohmic contact layer and pixel electrode have been formed in the lump, can in step, reduce the resistance value of patterning oxide semiconductor layer and picture element semiconductor layer simultaneously, can simplify the processing procedure of thin-film transistor, and make thin-film transistor have splendid electrical characteristic.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Figure 1A to Fig. 1 F be one embodiment of the invention the thin-film transistor manufacturing process on look schematic diagram.
Fig. 2 A to Fig. 2 F is the generalized section of the thin-film transistor manufacturing process that illustrated corresponding to the line A-A ' of Figure 1A to Fig. 1 F successively.
[primary clustering symbol description]
100: thin-film transistor
110: substrate
122: the patterning oxide semiconductor
122a: ohmic contact layer
124: the picture element semiconductor layer
124a: pixel electrode
130: the pattern etched barrier layer
140: the lock insulating barrier
150: the patterning protective layer
D: drain
DL
T: the end of data line
DL: data line
G: gate
H: opening
PS: the external drive signal provides the source
R: pixel electrode presumptive area
S: source electrode
SL
T: the end of scan line
SL: scan line.
Embodiment
[method of manufacturing thin film transistor]
Figure 1A to Fig. 1 F be one embodiment of the invention the thin-film transistor manufacturing process on look schematic diagram.Fig. 2 A to Fig. 2 F is the generalized section of the thin-film transistor manufacturing process that illustrated according to the line A-A ' of Figure 1A to Fig. 1 F.
Please refer to Figure 1A and Fig. 2 A, at first, on substrate 110, form source S and the drain D that is electrically insulated each other.When forming source S and drain D, more can on substrate 110, form data wire DL, and data wire DL is electrically connected to source S.The material of source S, drain D and data wire DL can be used metal material (as Ti, Mo, Al etc.) alloy, the nitride of metal material, the oxide of metal material, the nitrogen oxide of metal material etc., and source S, drain D and data line DL can be single rete or compound storehouse rete.
Source S, drain D can adopt general forming sputtering film with the production method of data wire DL, cooperate micro image etching procedure (that is step such as photoresistance coating, little shadow, etching, stripping), and the pattern of formation source S, drain D and data wire DL will not describe in detail at this.
Please refer to Figure 1B and Fig. 2 B, then, on substrate 110, form patterning oxide semiconductor layer 122 and picture element semiconductor layer 124 simultaneously, wherein, patterning oxide semiconductor layer 122 is between source S and drain D, and picture element semiconductor layer 124 is positioned at pixel electrode presumptive area R.
Further say, shown in Figure 1B, patterning oxide semiconductor layer 122 with picture element semiconductor layer 124 with light shield manufacture, patterning oxide semiconductor layer 122 covers source S and drain D partly, and patterning oxide semiconductor layer 122 can be connected to picture element semiconductor layer 124.In a further embodiment, patterning oxide semiconductor layer 122 also can be free of attachment to picture element semiconductor layer 124, as long as patterning oxide semiconductor layer 122 all has the drain of being positioned at D to go up (follow-up can the electric connection via drain D) with picture element semiconductor layer 124.
The material of picture element semiconductor layer 124 and patterning oxide semiconductor layer 122 is identical and can be selected from: indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), indium oxide gallium (IGO), tin oxide (ZnO), cadmium oxide, germanium oxide (2CdOGeO
2), cobalt nickel oxide (NiCo
2O
4) and combination, but not as limit.
Patterning oxide semiconductor layer 122 can adopt general forming sputtering film with the production method of picture element semiconductor layer 124, cooperates micro image etching procedure (that is step such as photoresistance coating, little shadow, etching, stripping), and the patterning oxide semiconductor layer 122 of formation shown in Figure 1B and Fig. 2 B and the pattern of picture element semiconductor layer 124 will not describe in detail at this.
Please refer to Fig. 1 C and Fig. 2 C, then, on patterning oxide semiconductor layer 122, form pattern etched barrier layer 130.Pattern etched barrier layer 130 exposes the patterning oxide semiconductor layer 122 of the part that is positioned at 130 both sides, pattern etched barrier layer.
The subregional patterning oxide semiconductor layer 122 of pattern etched barrier layer 130 covering part; patterning oxide semiconductor layer 122 in order to protection 130 belows, pattern etched barrier layer is still being kept characteristic of semiconductor (can be used as the channel layer between follow-up source S and the drain D) through after the successive process, so pattern etched barrier layer 130 can be described as the path protection layer again.
The production method on pattern etched barrier layer 130 can adopt general forming sputtering film, cooperates micro image etching procedure (that is steps such as photoresistance coating, little shadow, etching, stripping), and the pattern on the pattern etched barrier layer 130 of formation shown in Fig. 1 C and Fig. 2 C will not describe in detail at this.The material on pattern etched barrier layer 130 can be silicon dioxide or other material that is fit to.
Please refer to Fig. 1 D and Fig. 2 D, then, on substrate 110, form lock insulating barrier 140 all sidedly, in the process that forms lock insulating barrier 140, make simultaneously and be patterned the partially patterned oxide semiconductor layer 122 that etch stop layer 130 exposed and form two ohmic contact layer 122a and make the picture element semiconductor layer 124 that is positioned at picture element presumptive area R form pixel electrode 124a, pixel electrode 124a and drain D electrically connect, and two ohmic contact layer 122a electrically connect with source S and drain D respectively.
Further say, the method that forms two ohmic contact layer 122a and pixel electrode 124a comprises: when forming lock insulating barrier 140, carry out hydrogen doping for patterning oxide semiconductor layer 122 and picture element semiconductor layer 124, be not patterned the conductive ohmic contact layer 122a of patterning oxide semiconductor layer 122 formation that etch stop layer 130 covers and make, picture element semiconductor 124 forms conductive pixel electrode 124a.
For example, can adopt plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition, PECVD) form lock insulating barrier 140, employed gas is to be selected from silicon tetrahydride (SiH in the plasma enhanced chemical vapor deposition method
4), nitrous oxide (N
2O), helium (He) and the combination, the lock insulating barrier 140 of present embodiment for example is silica (SiOx).So, the invention is not restricted to this, in other embodiments, can be selected from silicon tetrahydride (SiH in order to the gas that forms lock insulating barrier 140
4), hydrogenation nitrogen (NH
3), nitrogen (N
2), hydrogen (H
2) and combination, lock insulating barrier 140 also can be silicon nitride (SiN
x).Therefore, when forming lock insulating barrier 140, patterning oxide semiconductor layer 122 that exposes and picture element semiconductor layer 124(such as indium oxide gallium zinc (IGZO)) can be exposed in the electricity slurry that contains hydrogen ion and be mixed by hydrogen ion, and change the material with conductive characteristic, i.e. ohmic contact layer 122a and pixel electrode 124a respectively into.
That is the material of ohmic contact layer 122a and pixel electrode 124a can be selected from hydrogeneous indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), indium oxide gallium (IGO), tin oxide (ZnO), cadmium oxide, germanium oxide (2CdOGeO
2), cobalt nickel oxide (NiCo
2O
4) and combination.
What deserves to be mentioned is, because in the fabrication steps of Fig. 1 D and Fig. 2 D, be to form ohmic contact layer 122a and pixel electrode 124a when utilize forming lock insulating barrier 140 in the lump, therefore, do not need extra processing procedure can reduce the resistance value of patterning oxide semiconductor layer 122 and picture element semiconductor layer 124, change conductive ohmic contact layer 122a and pixel electrode 124a respectively into.Thus, can simplify the processing procedure of this thin-film transistor.
Please refer to Fig. 1 E and Fig. 2 E, then, on the lock insulating barrier 140 of patterning oxide semiconductor layer 122 tops, form gate G.When forming gate G, more can on substrate 110, form scan line SL, and scan line SL and gate G electric connection.
The material of gate G and scan line SL can be used metal material (as Ti, Mo, Al etc.) alloy, the nitride of metal material, the oxide of metal material, the nitrogen oxide of metal material etc., and gate G and scan line SL can be single rete or compound storehouse rete.Gate G can adopt general forming sputtering film with the production method of scan line SL, cooperates micro image etching procedure (that is steps such as photoresistance coating, little shadow, etching, stripping), and forms the pattern of gate G and scan line SL, will not describe in detail at this.So far, gate G, source S and drain D can constitute thin-film transistor 100.
Please refer to Fig. 1 F and Fig. 2 F, also can on substrate 110, form patterning protective layer 150.Patterning protective layer 150 has a plurality of contact window H, and contact window H exposes the end SL of the scan line SL of thin-film transistor
TEnd DL with data line DL
T, provide source PS so that scan line SL and data wire DL are electrically connected to the external drive signal via contact window H.
The material of patterning protective layer 150 (for example: the stack layer of silicon nitride, silica, silicon oxynitride or above-mentioned at least two kinds of materials), organic material or above-mentioned combination can be inorganic material.The external drive signal provides source PS for example to be chip for driving.
In sum, the manufacture method of thin-film transistor 100 is when forming lock insulating barrier 140, form ohmic contact layer 122a and pixel electrode 124a in the lump, therefore, do not needed extra processing procedure can reduce the resistance value of patterning oxide semiconductor layer 122 and picture element semiconductor layer 124.Whole required light shield processing procedure quantity can reduce, simplify the processing procedure of thin-film transistor 100, and thin-film transistor 100 can have splendid electrical characteristic.
[thin-film transistor]
Fig. 1 F be one embodiment of the invention thin-film transistor on look schematic diagram.Fig. 2 F is the generalized section of the thin-film transistor that illustrated according to the line A-A ' of Fig. 1 F.
Please be simultaneously with reference to Fig. 1 F and Fig. 2 F, thin-film transistor 100 can comprise: source S, drain D, patterning oxide semiconductor layer 122, pattern etched barrier layer 130, lock insulating barrier 140, gate G and pixel electrode 124a.Patterning oxide semiconductor layer 122 is between source S and drain D, and patterning oxide semiconductor layer 122 has two ohmic contact layer 122a.Pattern etched barrier layer 130 is positioned on the patterning oxide semiconductor layer 122 and exposes ohmic contact layer 122a.Lock insulating barrier 140 overlay pattern etch stop layers 130 and patterning oxide semiconductor layer 122.Gate G is positioned on the lock insulating barrier 140 of patterning oxide semiconductor layer 122 tops.Pixel electrode 124a electrically connects drain D via ohmic contact layer 122a, wherein, pixel electrode 124a, patterning oxide semiconductor layer 122 are the identical rete in position with ohmic contact layer 122a, and pixel electrode 124a is identical with the material of ohmic contact layer 122a.
In addition, thin-film transistor 100 can further comprise data wire DL and scan line SL.Data wire DL and source S electrically connect.Scan line SL and gate G electrically connect.Thin-film transistor 100 more can comprise patterning protective layer 150, and patterning protective layer 150 covers whole thin-film transistor, and patterning protective layer 150 has a plurality of contact window H, and contact window H exposes the end SL of the scan line SL of thin-film transistor
TEnd DL with data line DL
T, provide source PS so that scan line SL and data wire DL are electrically connected to the external drive signal via contact window H.
Material about each assembly of thin-film transistor 100 was narrated in above-mentioned method of manufacturing thin film transistor, was not repeated at this.Above-mentioned thin-film transistor 100 has simple structure, cost of manufacture is low and splendid electrical characteristic.
In sum, thin-film transistor of the present invention and manufacture method thereof have the following advantages at least:
In the time of by formation lock insulating barrier, carry out hydrogen doping and formed ohmic contact layer and pixel electrode in the lump for patterning oxide semiconductor layer and picture element semiconductor layer, therefore, do not need extra processing procedure can reduce the resistance value of patterning oxide semiconductor layer and picture element semiconductor layer, make the processing procedure simplification of thin-film transistor and have splendid electrical characteristic.And for the light shield processing procedure of known oxide semiconductor thin-film transistor, the quantity of the light shield processing procedure of the manufacture method of above-mentioned thin-film transistor can reduce.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (14)
1. a method of manufacturing thin film transistor is characterized in that, comprising:
On a substrate, form an one source pole and a drain that is electrically insulated each other;
Form a patterning oxide semiconductor layer and a picture element semiconductor layer on this substrate simultaneously, wherein, this patterning oxide semiconductor layer is between this source electrode and this drain, and this picture element semiconductor layer is positioned at a pixel electrode presumptive area;
On this patterning oxide semiconductor layer, form a pattern etched barrier layer, expose this patterning oxide semiconductor layer of the part that is positioned at these both sides, pattern etched barrier layer;
On this substrate, form a lock insulating barrier, in the process that forms this lock insulating barrier, make this patterning oxide semiconductor layer of part that is exposed by this pattern etched barrier layer form two ohmic contact layers simultaneously and make this picture element semiconductor layer that is positioned at this picture element presumptive area form a pixel electrode, this pixel electrode and this drain electrically connect, and two those ohmic contact layers electrically connect with this source electrode and this drain respectively; And
On this lock insulating barrier of this patterning oxide semiconductor layer top, form a gate.
2. method of manufacturing thin film transistor according to claim 1 is characterized in that: the material of described picture element semiconductor layer and this patterning oxide semiconductor layer is identical and be selected from: indium oxide gallium zinc, indium zinc oxide, indium oxide gallium, tin oxide, cadmium oxide, germanium oxide, cobalt nickel oxide and combination thereof.
3. method of manufacturing thin film transistor according to claim 1 is characterized in that: the method that forms those ohmic contact layers and this pixel electrode comprises:
When forming this lock insulating barrier, carry out a hydrogen doping for this patterning oxide semiconductor layer and this picture element semiconductor.
4. thin-film transistor according to claim 1 is characterized in that: the material of those ohmic contact layers and this pixel electrode is to be selected from hydrogeneous indium oxide gallium zinc, indium zinc oxide, indium oxide gallium, tin oxide, cadmium oxide, germanium oxide, cobalt nickel oxide and combination thereof.
5. method of manufacturing thin film transistor according to claim 1, it is characterized in that: when forming this source electrode be electrically insulated each other and this drain on this substrate, more comprise: on this substrate, form a data wire, and this data wire and the electric connection of this source electrode.
6. method of manufacturing thin film transistor according to claim 1, it is characterized in that: when forming this gate on this lock insulating barrier of this patterning oxide semiconductor layer top, more comprise: on this substrate, form the one scan line, and this scan line and the electric connection of this gate.
7. method of manufacturing thin film transistor according to claim 1 is characterized in that: form this gate on this lock insulating barrier of this patterning oxide semiconductor layer top after, more comprise:
On this substrate, form a patterning protective layer; have a plurality of contact windows; expose the end of one scan line of this thin-film transistor and the end of a data line, provide the source so that this scan line and this data wire are electrically connected to an external drive signal via those contact windows.
8. method of manufacturing thin film transistor according to claim 1 is characterized in that: the material of described source electrode, this drain and this gate comprises: the metal of single rete or the metal of composite film.
9. a thin-film transistor is characterized in that, comprising:
An one source pole and a drain;
One patterning oxide semiconductor layer, between this source electrode and this drain, this patterning oxide semiconductor layer has two ohmic contact layers;
One pattern etched barrier layer is positioned on this patterning oxide semiconductor layer, exposes those ohmic contact layers;
One lock insulating barrier covers this pattern etched barrier layer and this patterning oxide semiconductor layer;
One gate is positioned on this lock insulating barrier of this patterning oxide semiconductor layer top; And
One pixel electrode electrically connects this drain via this ohmic contact layer, and wherein, this pixel electrode, this patterning oxide semiconductor layer are the identical rete in position with those ohmic contact layers, and this pixel electrode is identical with the material of those ohmic contact layers.
10. thin-film transistor according to claim 9 is characterized in that: the material of described patterning oxide semiconductor layer is to be selected from: indium oxide gallium zinc, indium zinc oxide, indium oxide gallium, tin oxide, cadmium oxide, germanium oxide, cobalt nickel oxide and combination thereof.
11. thin-film transistor according to claim 9 is characterized in that: the material of described ohmic contact layer and this pixel electrode is to be selected from hydrogeneous indium oxide gallium zinc, indium zinc oxide, indium oxide gallium, tin oxide, cadmium oxide, germanium oxide, cobalt nickel oxide and combination thereof.
12. thin-film transistor according to claim 9 is characterized in that, more comprises: a data wire electrically connects with this source electrode.
13. thin-film transistor according to claim 9 is characterized in that, more comprises: the one scan line electrically connects with this gate.
14. thin-film transistor according to claim 9; it is characterized in that; more comprise: a patterning protective layer; cover whole this thin-film transistor; this patterning protective layer has a plurality of contact windows; expose the end of one scan line of this thin-film transistor and the end of a data line, provide the source so that this scan line and this data wire are electrically connected to an external drive signal via those contact windows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110095235 CN102184865B (en) | 2011-04-15 | 2011-04-15 | Thin film transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110095235 CN102184865B (en) | 2011-04-15 | 2011-04-15 | Thin film transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102184865A true CN102184865A (en) | 2011-09-14 |
| CN102184865B CN102184865B (en) | 2013-06-05 |
Family
ID=44571019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110095235 Expired - Fee Related CN102184865B (en) | 2011-04-15 | 2011-04-15 | Thin film transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102184865B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013104228A1 (en) * | 2012-01-13 | 2013-07-18 | 京东方科技集团股份有限公司 | Method for manufacturing tft array substrate |
| WO2014166176A1 (en) * | 2013-04-07 | 2014-10-16 | 京东方科技集团股份有限公司 | Thin-film transistor and manufacturing method thereof, array base plate and display apparatus |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006019527A (en) * | 2004-07-01 | 2006-01-19 | Dainippon Printing Co Ltd | Manufacturing method for polycrystalline silicon thin film, manufacturing method for thin film transistor, and substrate with silicon thin film |
| JP2006237310A (en) * | 2005-02-25 | 2006-09-07 | Mitsui Eng & Shipbuild Co Ltd | Mos transistor and its manufacturing method |
| JP2008072025A (en) * | 2006-09-15 | 2008-03-27 | Canon Inc | Field effect transistor and its manufacturing method |
| CN101645462A (en) * | 2008-08-08 | 2010-02-10 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
| WO2010071034A1 (en) * | 2008-12-19 | 2010-06-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing transistor |
| CN101794818A (en) * | 2008-12-25 | 2010-08-04 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
-
2011
- 2011-04-15 CN CN 201110095235 patent/CN102184865B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006019527A (en) * | 2004-07-01 | 2006-01-19 | Dainippon Printing Co Ltd | Manufacturing method for polycrystalline silicon thin film, manufacturing method for thin film transistor, and substrate with silicon thin film |
| JP2006237310A (en) * | 2005-02-25 | 2006-09-07 | Mitsui Eng & Shipbuild Co Ltd | Mos transistor and its manufacturing method |
| JP2008072025A (en) * | 2006-09-15 | 2008-03-27 | Canon Inc | Field effect transistor and its manufacturing method |
| CN101645462A (en) * | 2008-08-08 | 2010-02-10 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
| WO2010071034A1 (en) * | 2008-12-19 | 2010-06-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing transistor |
| CN101794818A (en) * | 2008-12-25 | 2010-08-04 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013104228A1 (en) * | 2012-01-13 | 2013-07-18 | 京东方科技集团股份有限公司 | Method for manufacturing tft array substrate |
| EP2804207A4 (en) * | 2012-01-13 | 2015-10-14 | Boe Technology Group Co Ltd | Method for manufacturing tft array substrate |
| US9202892B2 (en) | 2012-01-13 | 2015-12-01 | Boe Technology Group Co., Ltd. | Manufacturing method of TFT array substrate |
| KR101620674B1 (en) * | 2012-01-13 | 2016-05-12 | 보에 테크놀로지 그룹 컴퍼니 리미티드 | Manufacturing method of tft array substrate |
| WO2014166176A1 (en) * | 2013-04-07 | 2014-10-16 | 京东方科技集团股份有限公司 | Thin-film transistor and manufacturing method thereof, array base plate and display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102184865B (en) | 2013-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8759832B2 (en) | Semiconductor device and electroluminescent device and method of making the same | |
| CN102169907B (en) | Thin film transistor and method of manufacturing the same | |
| TWI438868B (en) | Complementary metal oxide semiconductor transistor and fabricating method thereof | |
| CN102468341B (en) | Oxide semiconductor thin-film transistor and manufacture method thereof | |
| KR20200003288A (en) | Semiconductor device | |
| CN102664194B (en) | Thin-film transistor | |
| CN106684155A (en) | Dual-gate thin film transistor and preparation method therefor, array substrate and display apparatus | |
| CN108538860A (en) | The production method of top gate type amorphous-silicon TFT substrate | |
| CN102403365A (en) | Thin film transistor and method of manufacturing the same | |
| US20210082963A1 (en) | Electrostatic protection circuit and manufacturing method thereof, array substrate and display apparatus | |
| CN103500738A (en) | Semiconductor device containing etching barrier layer as well as manufacturing method and application of semiconductor device | |
| CN103578984B (en) | Semiconductor element and manufacture method thereof | |
| CN103094205A (en) | Prepared method of thin film transistor and thin film transistor driving back panel and thin film transistor driving back panel | |
| CN101976650B (en) | Thin film transistor and manufacture method thereof | |
| CN108305879A (en) | Thin-film transistor array base-plate and production method and display device | |
| CN108269856A (en) | A kind of oxide semiconductor thin-film transistor and preparation method thereof, array substrate | |
| CN102496621B (en) | Semiconductor component, electroluminescent component and manufacturing method thereof | |
| CN102184865B (en) | Thin film transistor and manufacturing method thereof | |
| CN103021942B (en) | Array base palte and manufacture method, display unit | |
| CN102437195B (en) | Thin film transistor and method of manufacturing the same | |
| CN101937875B (en) | Complementary metal-oxide-semiconductor (CMOS) transistor and manufacturing method thereof | |
| CN104637872A (en) | Method for manufacturing oxide semiconductor thin film transistor array substrate | |
| CN102569413A (en) | Thin film transistor and manufacturing method thereof | |
| CN101997037B (en) | Semiconductor structure and manufacturing method thereof | |
| CN102184866B (en) | Thin-film transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130605 Termination date: 20200415 |