CN102184709A - Display control method and device - Google Patents

Abstract

The embodiment of the invention discloses a display control method, which comprises the following steps that: a preset brightness set value Mi is acquired and is input into a data gating device to be used as gating data, a base clock enters a counter, a periodic digital signal Qi is output, an Ai is output after the periodic digital signal Qi is processed by a logic arithmetic unit and enters the data gating device to be used as grated data, and the data gating device outputs a Di; after the Di output by the data gating device enters a logic combiner, a pulse-width modulation (PWM) signal OUT is output; and the PWM signal OUT drives a light-emitting diode (LED) to carry out display control. In the scheme disclosed by the invention, on the premise of not influencing the accuracy of the original data, the PWM signal is generated under higher frequency, the display control with high refresh frequency is realized and an output mode of a PWM signal duty ratio is properly regulated so as to ensure the driving effect of an output port. The scheme disclosed by the invention is implemented by carrying out logic combination on an output of the counter in a data gating mode. The scheme is simply and efficiently implemented.

Description

The method and the device that show control

Technical field

The present invention relates to digital communicating field, particularly, the present invention relates to show the method and the device of control.

Background technology

How to control the brightness of LED, simulation dimming mode till now the width-modulation pulse dimming mode of technical development from beginning, even simulation light modulation and width-modulation pulse light modulation can be used in combination in a lot of now the application.The simulation light modulation is meant, by the data that write, regulates the size of current that flows through LED, makes LED brightness change.The width-modulation pulse light modulation is meant, by in a period of time, regulates the time width that LED is bright or go out.In the time of the LED conducting, be that fixed current drives, can set by external resistance; When LED turn-offs, there is not electric current to pass through.Like this, the display effect in the regular hour is that variation has taken place for the brightness of lamp.And in this set time, bright time of lamp is long more, and general effect is that lamp is just bright more.Can reach within a certain period of time like this, LED be carried out the purpose of brightness regulation.

The shortcoming of simulation light modulation mainly contains following 2 points: 1, change the electric current through LED, can change the photochromic of LED, can make the look of pixel add like this and add a lot of uncertainties; 2 if the gray shade scale of increase LED needs high-precision DAC, and its linearity and precision are restricted.

The shortcoming of above-mentioned simulation light modulation has then been evaded in the width-modulation pulse light modulation fully.When lamp was lighted, what flow through was the electric current of fixing, and light wavelength can not change.Increase gray shade scale if desired, will be used for the fundamental clock speed-raising of width-modulation pulse, in original cycle regular time, the dutycycle selection meeting of allowing is more; Perhaps, use original fundamental clock, also have more dutycycle and select the original time cycle lengthening.

So the mode that substantially all adopts the width-modulation pulse light modulation in the industry is to the LED light modulation.But, the width-modulation pulse light modulation also has the defective of self.Because this kind light-dimming method need be average within a certain period of time with brightness, so when the gray shade scale of LED was higher, the cycle was longer.Like this, LED is bright or when going out, perhaps the time of Bu Zhuoing too short, to such an extent as to the light on and off ratio that should receive in the time, the very original light on and off ratio of true embodiment.During digital vedio recording product shooting picture such as video camera, pull-in time is far smaller than the pull-in time of human eye to picture.Like this, the people glances up picture more clearly, and during by video camera or camera shooting, picture may cause flickering, produces striped in other words.

In existing width-modulation pulse frequency-doubling method, mostly there is the frequency multiplication minor cycle that constitutes by MSB (Most SignificantBit, highest significant position) and LSB (Least Significant Bit, least significant bit (LSB)).MSB is the high word bit in width-modulation pulse data normal period, though slightly distortion can reflect the width-modulation pulse dutycycle of normal period preferably; LSB is the low word bit in width-modulation pulse data normal period, only is at a width-modulation pulse in normal period (cycle before being frequency multiplication), whole show undistorted.So exist: during near capturing LSB moment, can cause comparatively significantly local repressentation distortion.

In addition, also have some frequency-doubling methods, for example, with very average the breaing up of width-modulation pulse signal, when 1/2 dutycycle, the time of high level is a fundamental clock width.Yet in actual device was used, the frequency of fundamental clock was very fast, and the cycle reached for 33 nanoseconds, because the driving force of output driving port is limited, made dutycycle that distortion take place like this, shown in figure A.

Therefore, be necessary to propose a kind of otherwise effective technique scheme, under the prerequisite of precision that does not influence legacy data and output duty cycle, can effectively improve the refreshing frequency of demonstration, and can keep the driving force of output port.

Summary of the invention

Purpose of the present invention is intended to solve at least one of above-mentioned technological deficiency, and is special under the prerequisite of the precision that does not influence legacy data, generates the width-modulation pulse signal with higher frequency, realizes the demonstration control of high refreshing frequency.

In order to achieve the above object, embodiments of the invention have proposed a kind of method that shows control on the one hand, may further comprise the steps:

Obtain default brightness settings M _i, the input data strobe device is as gated data, and fundamental clock enters counter, output periodicity digital signal Q _i, through exporting A after the logical-arithmetic unit _iEnter described data strobe device conduct by the gating data, described data strobe device output D _i

The D of described data strobe device output _iEnter through behind the logic combiner, output pulse width modulating pulse PMW signal OUT, wherein:

Described brightness settings M _iEqual to comprise the number of fundamental clock at the high level time of a complete counter described width-modulation pulse pwm signal OUT in the cycle, and the high level time of described width-modulation pulse pwm signal OUT is divided into a plurality of brightness control signals, a complete counter cycle in respectively occur thereafter, thereby raising display refresh rates, 0≤i＜n, n is the figure place length of described counter, and high level time is meant effective demonstration time;

Described width-modulation pulse PMW signal OUT driven for emitting lights diode (LED) shows control.

The embodiment of the invention has proposed a kind of device that shows control on the other hand, comprises counter, logical-arithmetic unit, data strobe device, logic combiner and LED,

Described counter is used to receive fundamental clock, and output is digital signal Q periodically _i

Described logical-arithmetic unit is used to receive described periodicity digital signal Q _iBack output A _iEnter described data strobe device conduct by the gating data;

Described data strobe device is used to receive A _iAnd obtain default brightness settings M _iAs gated data, described data strobe device output D _i

Described logic combiner is used to receive D _iAfter, output pulse width modulating pulse PMW signal OUT, wherein:

Described brightness settings M _iEqual to comprise the number of fundamental clock at the high level time of a complete counter described width-modulation pulse pwm signal OUT in the cycle, and the high level time of described width-modulation pulse pwm signal OUT is divided into a plurality of brightness control signals, during identical time respectively occur thereafter, thereby raising display refresh rates, 0≤i＜n, n are the figure place length of described counter;

Described LED is used to receive described width-modulation pulse PMW signal OUT as driving, realizes showing control.

The such scheme that the present invention proposes, by under the prerequisite of the precision that does not influence legacy data, generate the width-modulation pulse signal with higher frequency, realize the demonstration control of high refreshing frequency, suitably regulate the width-modulation pulse PMW signal dutyfactor way of output simultaneously, to guarantee the driving effect of output port.。The such scheme that the present invention proposes carries out logical combination by the output to counter, and comes the mode of gating to realize by data, and implementation is simple, efficient.

Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.

Description of drawings

Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:

Fig. 1 is the synoptic diagram of the higher time output driving force of PWM output frequency deficiency;

Fig. 2 is that traditional width-modulation pulse is realized synoptic diagram;

Fig. 3 is the method flow diagram that shows control according to the embodiment of the invention;

Fig. 4 realizes synoptic diagram according to embodiment of the invention width-modulation pulse;

Fig. 5 is the synoptic diagram with asynchronous counter;

Fig. 6 is the synoptic diagram with synchronous counter;

Fig. 7 is the logical-arithmetic unit synoptic diagram;

Fig. 8 is the data strobe device synoptic diagram;

Fig. 9 is the logic combiner synoptic diagram;

Logical combination waveform and the PWM output waveform synoptic diagram of Figure 10 for producing;

Figure 11 is the apparatus structure synoptic diagram that shows control according to the embodiment of the invention;

Figure 12 is width-modulation pulse technology contrast synoptic diagram.

Embodiment

Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.

People require display frame more and more clear now, and image content becomes increasingly complex.That is to say that the data volume of picture is increasing, and needs higher flat pannel display refreshing frequency simultaneously.Therefore need the flat pannel display chip to generate the width-modulation pulse signal, and do not influence the precision of legacy data with higher frequency.The implementation of tradition width-modulation pulse is: fundamental clock (CLK) is input to a counter, and counter begins counting, and is for example complete 0 from initial data, and for example complete 1 until end data, so the cycle is reciprocal.If the output of counter is less than the value of data DATA, output is high level just so, otherwise output is low level just.Like this, data are with the form output of dutycycle.As shown in Figure 2.

Sharpness requirement to picture is more and more higher, and meaning needs pixel can comprise more information, and just gray shade scale is more and more higher, and under the situation that fundamental clock is determined, width-modulation pulse normal period can be more and more longer.Concerning traditional width-modulation pulse mode, during with the shooting of video camera or camera, long more width-modulation pulse can bring more obvious flickering or striped sense normal period.This solves a problem with regard to needs: when promoting clearness, need to avoid allowing digital product such as camera capture striped again.

Usually, when the refreshing frequency of data reaches 60Hz when above, human eye does not just have flickering or striped sense to the perception of image; And the shutter of camera can reach 4000Hz.That is to say that human eye allows width-modulation pulse normal period is 16.7 milliseconds, camera then only allows 0.25 millisecond.For example the Data Update cycle of present general screen is 4 milliseconds.The people glances up very clear, but when taking with video camera, because 0.25 millisecond can not capture whole width-modulation pulse normal period, and the dutycycle that captures in 0.25 millisecond of time can not embody the data that this need represent constantly.So the striped sense is obvious.

Therefore, need to propose a kind of new pulse-length modulation agreement, can allow the interior dutycycle of being caught of the short aperture time of video camera, can reflect the dutycycle of whole width-modulation pulse in normal period again preferably, have enough output driving forces simultaneously.

In order to realize the present invention's purpose, the present invention proposes a kind of method that shows control, may further comprise the steps: obtain default brightness settings M _i, the input data strobe device is as gated data, and fundamental clock enters counter, output periodicity digital signal Q _i, enter described data strobe device conduct by the gating data, described data strobe device output D through exporting Ai after the logical-arithmetic unit _iThe D of described data strobe device output _iEnter through behind the logic combiner, output pulse width modulating pulse PMW signal OUT, wherein: described brightness settings M _iEqual to comprise the number of fundamental clock at the high level time of a complete counter described width-modulation pulse pwm signal OUT in the cycle, and the high level time of described width-modulation pulse pwm signal OUT is divided into a plurality of brightness control signals, a complete counter cycle in respectively occur thereafter, thereby raising display refresh rates, 0≤i＜n, n are the figure place length of described counter; Described width-modulation pulse PMW signal OUT driven for emitting lights diode (LED) shows control.In an embodiment of the present invention, for example high level time is meant effective demonstration time.

As shown in Figure 3, for show the method flow diagram of control according to the embodiment of the invention, may further comprise the steps:

S110: gated data and by outputting data signals behind the gating data inputs data strobe device

In step S110, the fundamental clock enter counter, counter output is digital signal Q periodically _i, through exporting A after the logical-arithmetic unit _iEnter described data strobe device conduct by the gating data,

As shown in Figure 4, for realizing synoptic diagram according to embodiment of the invention width-modulation pulse.

Particularly, fundamental clock (CLK) is input to the counter of a n position, and counter begins counting, and from initial data, for example n 0, until end data, for example n 1, and so the cycle is reciprocal.

Particularly, counter comprises asynchronous counter or synchronous counter.As embodiments of the invention, the high level time of n output has lap, and dutycycle is 1/2, the number that high-order output high impulse comprises fundamental clock is 2 times of the output high impulse of the adjacent low level number that comprises fundamental clock, low bit frequency is 2 times of high bit frequency, and institute's output signal is followed successively by Q from a high position to the low level _(n-1), Q _(n-2)..., Q ₀

As shown in Figure 5, for synoptic diagram, form by the d type flip flop string with asynchronous counter.The QB termination D end of the d type flip flop of each grade.The Q end of previous stage d type flip flop connects the CLKB end of back one-level d type flip flop, and the QB end connects the CLK end of back one-level d type flip flop.As shown in Figure 6, be synoptic diagram with synchronous counter.When all low levels are output as entirely 1, this high position is output as at 0 o'clock, changes this high-order state, becomes 1 from 0, perhaps becomes 0 from 1.

The periodicity digital signal Q of counter output _iComprise through logical-arithmetic unit:

Periodicity digital signal Q _iObtain n output by logical combination, the high level time of n output is not overlapping, the number that high-order output high impulse comprises fundamental clock is 2 times of the output high impulse of the adjacent low level number that comprises fundamental clock, and the high impulse quantity of each output is evenly distributed in width-modulation pulse in normal period.

Furthermore, the periodicity digital signal Q of counter output _iThrough described logic combiner output A _i, from a high position to the low level, be output as A successively _(n-1), A _(n-2)..., A ₀, A _iMeet the following conditions:

$\mathrm{Ai}=\left\{\begin{array}{c}\mathrm{Qk}...............................................................i=n-1\\ \stackrel{\&OverBar;}{\mathrm{Qk}}*...*\stackrel{\&OverBar;}{Q_{[k-(n-1-i)-1]}}*Q_{[k-(n-1-i)]}..................n-k-1\&le;i<n-1\\ \stackrel{\&OverBar;}{Q0}*...*\stackrel{\&OverBar;}{Q_{[n-2-i]}}*Q_{[n-1-i]}..............................0\&le;i<n-k-1\end{array}\right.$

Wherein k is 0 or less than the positive integer of n; Thereby do not overlap after making the high impulse that overlaps originally by computing, to be fixed as 1/2 be 2 times of low level dutycycle through computing rear high-lying dutycycle to dutycycle originally.

As shown in Figure 7, be the logical-arithmetic unit synoptic diagram, corresponding n input and n output.Drive the effect situation according to output, after the k in the selected above-mentioned formula, will import Qk as output most significant digit A _(n-1), in the present embodiment, choose with the BUF impact damper and increase driving force, do not influence the transmission of data.Accordingly, inferior high-order A _(n-2)Be output as: as Qk when the data after the INV phase inverter are 1 during for low level, Q _(k-1)As output, otherwise remain low level; Same, all the other positions are the utilogic gate circuit all, according to above-mentioned formula simple realization output.

Simultaneously, in step S110, obtain default brightness settings M _i, the input data strobe device is as gated data.Thereafter, data strobe device is according to gated data with by the gating data, outputting data signals D _i

As shown in Figure 8, be the data strobe device synoptic diagram.Present embodiment has adopted with the mode of door and has carried out, and promptly Y=A*B if normally export B, then need necessary A=1, otherwise output is maintained 0.In actual applications, also can adopt similar circuit realizations such as transmission gate, but its purpose is normally done data strobe usefulness.

When this position of gating data is to be " very ", then gating mutually should the position by the gating data; When this position of gating data is " vacation ", then shielding mutually should the position by the gating data.For example, if this position of data is 1, with regard to the corresponding logical combination of gating position; If this position of data is 0, just shield corresponding logical combination position, then logical OR is carried out in their output.

As embodiments of the invention, following formula is satisfied in the output of data strobe device:

D _i＝M _i*A _i，

From a high position to the low level, be output as A successively by the gating data _(n-1), A _(n-2)..., A ₀, gated data is output as M successively from a high position to the low level _(n-1), M _(n-2)..., M ₀, output signal is output as D successively from a high position to the low level _(n-1), D _(n-2)..., D ₀When the figure place length of described gated data during less than n, the output D of gated data _iAdd spot patch and be the n position together.

S120: the data-signal of data strobe device output is through output pulse width modulating pulse pwm signal behind the logic combiner.

In step S120, logic combiner comprises:

With the output of data strobe device, carry out logical OR, and output pulse width modulating pulse pwm signal.

As shown in Figure 9, be the synoptic diagram of logic combiner.Present embodiment has adopted the mode of logic sum gate to realize, also can adopt other circuit to realize the function of this module: if promptly some high level that is input as, output is high level so.Wherein high level time is and exports effective time.During if certain practices, adopt low level time for exporting effective time, can adopt the mode of logical AND gate so herein.In a word, this module is that gathered with the effective time of n input.

As embodiments of the invention, width-modulation pulse PMW signal OUT satisfies following formula:

$\mathrm{OUT}=\underset{i=0}{\overset{i=n-1}{\mathrm{\&Sigma;}}}{D}_i.$

By the way, then originally 2 ⁿThe complete counter of individual fundamental clock number is in the cycle, and continuous high-pulse widths is cut into a plurality of discontinuous high impulses.Output signal has following feature: the size of brightness settings equals to comprise at the high level time of a complete counter described a series of width-modulation pulse pwm signals in the cycle number of fundamental clock; And described a series of width-modulation pulse pwm signal high level time is divided into a plurality of brightness control signals, via showing respectively in the identical time, forms higher refresh rate.

By above-mentioned steps, can realize width-modulation pulse output frequency multiplication and not influence the requirement of precision, as shown in figure 10, be the logical combination waveform and the PWM output waveform synoptic diagram of generation.

S130:PWM signal driven for emitting lights diode (LED) shows control.

In step S130, the pulse signal that utilizes step S120 to obtain, the driven for emitting lights diode (LED) realizes showing control.

As shown in figure 11, for show the structural representation of the device 100 of control according to the embodiment of the invention, comprise counter 110, logical-arithmetic unit 120, data strobe device 130, logic combiner 140 and LED 150.

Wherein, counter 110 is used to receive fundamental clock, and output is digital signal Q periodically _i

Logical-arithmetic unit 120 is used for receiving cycle digital signal Q _iBack output A _iEnter data strobe device 130 conducts by the gating data.

Counter 110 comprises asynchronous counter or synchronous counter, the high level time of n output has lap, and dutycycle is 1/2, the number that high-order output high impulse comprises fundamental clock is 2 times of the output high impulse of the adjacent low level number that comprises fundamental clock, low bit frequency is 2 times of high bit frequency, and institute's output signal is followed successively by Q from a high position to the low level _(n-1), Q _(n-2)..., Q ₀

The periodicity digital signal Q of counter 110 outputs _iComprise through logical-arithmetic unit 120:

Periodicity digital signal Q _iObtain n output by logical combination, the high level time of n output is not overlapping, the number that high-order output high impulse comprises fundamental clock is 2 times of the output high impulse of the adjacent low level number that comprises fundamental clock, and the high impulse quantity of each output is evenly distributed in width-modulation pulse in normal period.

The periodicity digital signal Q of counter 110 outputs _iThrough logic combiner 140 output A _i, from a high position to the low level, be output as A successively _(n-1), A _(n-2)..., A ₀, A _iMeet the following conditions:

$\mathrm{Ai}=\left\{\begin{array}{c}\mathrm{Qk}...............................................................i=n-1\\ \stackrel{\&OverBar;}{\mathrm{Qk}}*...*\stackrel{\&OverBar;}{Q_{[k-(n-1-i)-1]}}*Q_{[k-(n-1-i)]}..................n-k-1\&le;i<n-1\\ \stackrel{\&OverBar;}{Q0}*...*\stackrel{\&OverBar;}{Q_{[n-2-i]}}*Q_{[n-1-i]}..............................0\&le;i<n-k-1\end{array}\right.$

Wherein k is 0 or less than the positive integer of n; Thereby do not overlap after making the high impulse that overlaps originally by computing, to be fixed as 1/2 be 2 times of low level dutycycle through computing rear high-lying dutycycle to dutycycle originally.

Data strobe device 130 is used to receive A _iAnd obtain default brightness settings M _iAs gated data, data strobe device 130 output D _i

Data strobe device 130 comprises:

When this position of gating data is to be " very ", then gating mutually should the position by the gating data; When this position of gating data is " vacation ", then shielding mutually should the position by the gating data.

Following formula is satisfied in the output of data strobe device 130:

D _i＝M _i*A _i，

From a high position to the low level, be output as A successively by the gating data _(n-1), A _(n-2)..., A ₀, gated data is output as M successively from a high position to the low level _(n-1), M _(n-2)..., M ₀, output signal is output as D successively from a high position to the low level _(n-1), D _(n-2)..., D ₀When the figure place length of gating data during less than n, the output D of gated data _iAdd spot patch and be the n position together.

Logic combiner 140 is used to receive D _iAfter, output pulse width modulating pulse PMW signal OUT, wherein:

Brightness settings M _iEqual to comprise the number of fundamental clock at the high level time of complete counter width-modulation pulse pwm signal OUT in 110 cycles, and the high level time of width-modulation pulse pwm signal OUT is divided into a plurality of brightness control signals, a complete counter cycle in respectively occur thereafter, thereby promoted display refresh rates, 0≤i＜n, n are the figure place length of counter 110.

Logic combiner 140 comprises:

With the output of data strobe device 130, carry out logical OR, and output pulse width modulating pulse pwm signal.

The width-modulation pulse PMW signal OUT of logic combiner 140 outputs satisfies following formula:

$\mathrm{OUT}=\underset{i=0}{\overset{i=n-1}{\mathrm{\&Sigma;}}}{D}_i.$

LED 150 is used to receive width-modulation pulse PMW signal OUT as driving, realizes showing control.

In order further to set forth the present invention,, be that the present invention will be described for example with the width-modulation pulse signal of one 8 bit data (8 ' b0110_0011) below in conjunction with further embodiment.

Tradition width-modulation pulse method is: one 8 counter.This counter is the fundamental clock cycle with the time T, progressively adds one to 8 ' b1111_1111 from 8 ' b0000_0000, and then to 8 ' b0000_0000.And so forth.Gradation data is updated in the data-carrier store, if the output numerical value of counter less than 8 ' b0110_0011, width-modulation pulse output is exactly 1 (promptly allow LED bright) so, otherwise output is exactly 0 (promptly allowing LED go out).The bright time of LED lamp is 2 so ⁰+ 2 ¹+ 2 ⁵+ 2 ⁶=99T, the time of going out is 256T-99T=157T.Dutycycle is 99T/256T.And in normal period, only once bright at a big width-modulation pulse, go out once, refresh rate is: 1/256T.

The width-modulation pulse method that the present invention proposes is: one 8 counter.This counter is the fundamental clock cycle with the time T, progressively adds one to 8 ' b1111_1111 from 8 ' b0000_0000, and then to 8 ' b0000_0000.And so forth.

8 outputs of counter, Q7 ..., Q0, by logical-arithmetic unit, so according to the logical-arithmetic unit formula:

$\mathrm{Ai}=\left\{\begin{array}{c}\mathrm{Qk}...............................................................i=n-1\\ \stackrel{\&OverBar;}{\mathrm{Qk}}*...*\stackrel{\&OverBar;}{Q_{[k-(n-1-i)-1]}}*Q_{[k-(n-1-i)]}..................n-k-1\&le;i<n-1\\ \stackrel{\&OverBar;}{Q0}*...*\stackrel{\&OverBar;}{Q_{[n-2-i]}}*Q_{[n-1-i]}..............................0\&le;i<n-k-1\end{array}\right.$

According to the requirement of refresh rate and port driver, choose k=5, output is respectively:

A ₇＝Q5；

$A_6=\stackrel{\&OverBar;}{Q5}*Q4;$

$A_5=\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3;$

$A_4=\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3}*\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}2;$

$A_3=\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}2}*\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}1;$

$A_2=\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}2}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}1}*Q0;$

$A_1=\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}2}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}1}*\stackrel{\&OverBar;}{Q0}*Q6;$

$A_0=\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}2}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}1}*\stackrel{\&OverBar;}{Q0}*\stackrel{\&OverBar;}{Q6}*Q7$

The n of logical-arithmetic unit output, through data strobe device, gated data is M _iBe respectively: 8 ' b0110_0011, by gating data A _iAs mentioned above.Obtain output data D _iAs follows:

D ₇＝M ₇*A ₇＝0*A ₇＝0；

$D_6=M_6*A_6=1*A_6=\stackrel{\&OverBar;}{Q5}*Q4;$

$D_5=M_5*A_5=1*A_5=\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3;$

D ₄＝M ₄*A ₄＝0*A ₄＝0；

D ₃＝M ₃*A ₃＝0*A ₃＝0；

D ₂＝M ₂*A ₂＝0*A ₂＝0；

${\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">D</figure-callout>}}_1={\mathrm{<figure-callout\; id="1"\; label="M"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">M</figure-callout>}}_1*A_1=1*A_1=\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}2}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}1}*\stackrel{\&OverBar;}{Q0}*Q6;$

${D_0=M_0*A}_0=1*A_0=\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}2}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}1}*\stackrel{\&OverBar;}{Q0}*\stackrel{\&OverBar;}{Q6}*Q7;$

The n of data strobe device output, as n input of logic combiner, according to the logic combiner formula, PWM is output as:

$\mathrm{OUT}=\underset{i=0}{\overset{i=n-1}{\mathrm{\&Sigma;}}}{D}_i$

$=\stackrel{\&OverBar;}{Q5}*Q4+\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3+\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}2}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}1}*\stackrel{\&OverBar;}{Q0}*Q6$

$+\stackrel{\&OverBar;}{Q5}*\stackrel{\&OverBar;}{Q4}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="HDA0000052407080000031.png"\; state="\{\{state\}\}">Q</figure-callout>}3}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}2}*\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="HDA0000052407080000031.png,HDA0000052407080000032.png"\; state="\{\{state\}\}">Q</figure-callout>}1}*\stackrel{\&OverBar;}{Q0}*\stackrel{\&OverBar;}{Q6}*Q7$

OUT is the time that LED lights.

The time that LED lights is:

$\frac{256T}{4}+\frac{256T}{8}+\frac{256T}{128}+\frac{256T}{256}=64T+32T+2T+T=99T$

Dutycycle is 99T/256T.Dutycycle is the same with traditional width-modulation pulse method.But because

Pulse be the high impulse that 16 continuous fundamental clocks are arranged in per 64 fundamental clocks, Pulse be the high impulse that 8 continuous fundamental clocks are arranged in per 64 fundamental clocks, Pulse be the high impulse that 2 independences is arranged in per 256 fundamental clocks and be evenly distributed on the fundamental clock among the 256T, and

It is the high impulse that 1 fundamental clock is arranged in the middle of this 256T.

So new width-modulation pulse method can correctly show dutycycle, and because its light on and off time dispersion, so improved refresh rate.That is, new width-modulation pulse method can guarantee under the high-precision situation, improves refresh rate.As shown in figure 12, be the waveform synoptic diagram of various PWM.With respect to output frequency too highly cause easily that dutycycle is untrue, the not enough situation of driving force output, the scheme that the present invention proposes is all taken into account (diagram deliberately reduces refresh rate in order obviously to contrast, and actual conditions can suitably improve output frequency) to refresh rate and dutycycle.

Said method or equipment that the present invention proposes, by under the prerequisite of the precision that does not influence legacy data, generate the width-modulation pulse signal with higher frequency, realize the demonstration control of high refreshing frequency, suitably regulate the width-modulation pulse PMW signal dutyfactor way of output simultaneously, to guarantee the driving effect of output port.。Said method or equipment that the present invention proposes carry out logical combination by the output to counter, and come the mode of gating to realize by data, and implementation is simple, efficient.

One of ordinary skill in the art will appreciate that and realize that all or part of step that the foregoing description method is carried is to instruct relevant hardware to finish by program, described program can be stored in a kind of computer-readable recording medium, this program comprises one of step or its combination of method embodiment when carrying out.

In addition, each functional unit in each embodiment of the present invention can be integrated in the processing module, also can be that the independent physics in each unit exists, and also can be integrated in the module two or more unit.Above-mentioned integrated module both can adopt the form of hardware to realize, also can adopt the form of software function module to realize.If described integrated module realizes with the form of software function module and during as independently production marketing or use, also can be stored in the computer read/write memory medium.

The above-mentioned storage medium of mentioning can be a ROM (read-only memory), disk or CD etc.

The above only is embodiments of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (16)

1. a method that shows control is characterized in that, may further comprise the steps:

Obtain default brightness settings M _i, the input data strobe device is as gated data, and fundamental clock enters counter, output periodicity digital signal Q _i, enter described data strobe device conduct by the gating data, described data strobe device output D through exporting Ai after the logical-arithmetic unit _i

The D of described data strobe device output _iEnter through behind the logic combiner, output pulse width modulating pulse PMW signal OUT, wherein:

Described brightness settings M _iEqual to comprise the number of fundamental clock at the high level time of a complete counter described width-modulation pulse pwm signal OUT in the cycle, and the high level time of described width-modulation pulse pwm signal OUT is divided into a plurality of brightness control signals, a complete counter cycle in respectively occur thereafter, thereby raising display refresh rates, 0≤i＜n, n are the figure place length of described counter;

Described width-modulation pulse PMW signal OUT driven for emitting lights diode (LED) shows control.

2. the method for demonstration control as claimed in claim 1, it is characterized in that, described counter comprises asynchronous counter or synchronous counter, the high level time of described n output has lap, and dutycycle is 1/2, the number that high-order output high impulse comprises fundamental clock is 2 times of the output high impulse of the adjacent low level number that comprises fundamental clock, and low bit frequency is 2 times of high bit frequency, and institute's output signal is followed successively by Q from a high position to the low level _(n-1), Q _(n-2)..., Q ₀

3. the method for demonstration control as claimed in claim 2 is characterized in that, the periodicity digital signal Q of described counter output _iComprise through described logical-arithmetic unit:

Described periodicity digital signal Q _iObtain n output by logical combination, the high level time of described n output is not overlapping, the number that high-order output high impulse comprises fundamental clock is 2 times of the output high impulse of the adjacent low level number that comprises fundamental clock, and the high impulse quantity of each output is evenly distributed in width-modulation pulse in normal period.

4. the method for demonstration control as claimed in claim 3 is characterized in that, the periodicity digital signal Q of described counter output _iThrough described logic combiner output A _i, from a high position to the low level, be output as A successively _(n-1), A _(n-2)..., A ₀, A _iMeet the following conditions:

$\mathrm{Ai}=\left\{\begin{array}{c}\mathrm{Qk}...............................................................i=n-1\\ \stackrel{\&OverBar;}{\mathrm{Qk}}*...*\stackrel{\&OverBar;}{Q_{[k-(n-1-i)-1]}}*Q_{[k-(n-1-i)]}..................n-k-1\&le;i<n-1\\ \stackrel{\&OverBar;}{Q0}*...*\stackrel{\&OverBar;}{Q_{[n-2-i]}}*Q_{[n-1-i]}..............................0\&le;i<n-k-1\end{array}\right.$

Wherein k is 0 or less than the positive integer of n; Thereby do not overlap after making the high impulse that overlaps originally by computing, to be fixed as 1/2 be 2 times of low level dutycycle through computing rear high-lying dutycycle to dutycycle originally.

5. the method for demonstration control as claimed in claim 4 is characterized in that described data strobe device comprises:

When this position of gating data is to be " very ", then gating mutually should the position by the gating data; When this position of gating data is " vacation ", then shielding mutually should the position by the gating data.

6. the method for demonstration control as claimed in claim 5 is characterized in that following formula is satisfied in the output of described data strobe device:

D _i＝M _i*A _i，

From a high position to the low level, be output as A successively by the gating data _(n-1), A _(n-2)..., A ₀, gated data is output as M successively from a high position to the low level _(n-1), M _(n-2)..., M ₀, output signal is output as D successively from a high position to the low level _(n-1), D _(n-2)..., D ₀When the figure place length of described gated data during less than n, the output D of described gated data _iAdd spot patch and be the n position together.

7. the method for demonstration control as claimed in claim 6 is characterized in that described logic combiner comprises:

With the output of data strobe device, carry out logical OR, and output pulse width modulating pulse pwm signal.

8. the method for demonstration control as claimed in claim 7 is characterized in that described width-modulation pulse PMW signal OUT satisfies following formula:

$\mathrm{OUT}=\underset{i=0}{\overset{i=n-1}{\mathrm{\&Sigma;}}}{D}_i.$

9. a device that shows control is characterized in that, comprises counter, logical-arithmetic unit, data strobe device, logic combiner and LED,

Described counter is used to receive fundamental clock, and output is digital signal Q periodically _i

Described logical-arithmetic unit is used to receive described periodicity digital signal Q _iBack output A _iEnter described data strobe device conduct by the gating data;

Described data strobe device is used to receive A _iAnd obtain default brightness settings M _iAs gated data, described data strobe device output D _i

Described logic combiner is used to receive D _iAfter, output pulse width modulating pulse PMW signal OUT, wherein:

Described brightness settings M _iEqual to comprise the number of fundamental clock at the high level time of a complete counter described width-modulation pulse pwm signal OUT in the cycle, and the high level time of described width-modulation pulse pwm signal OUT is divided into a plurality of brightness control signals, during identical time respectively occur thereafter, thereby raising display refresh rates, 0≤i＜n, n are the figure place length of described counter;

Described LED is used to receive described width-modulation pulse PMW signal OUT as driving, realizes showing control.

10. the device of demonstration control as claimed in claim 9, it is characterized in that, described counter comprises asynchronous counter or synchronous counter, the high level time of described n output has lap, and dutycycle is 1/2, the number that high-order output high impulse comprises fundamental clock is 2 times of the output high impulse of the adjacent low level number that comprises fundamental clock, and low bit frequency is 2 times of high bit frequency, and institute's output signal is followed successively by Q from a high position to the low level _(n-1), Q _(n-2)..., Q ₀

11. the device of demonstration control as claimed in claim 10 is characterized in that, the periodicity digital signal Q of described counter output _iComprise through described logical-arithmetic unit:

Described periodicity digital signal Q _iObtain n output by logical combination, the high level time of described n output is not overlapping, the number that high-order output high impulse comprises fundamental clock is 2 times of the output high impulse of the adjacent low level number that comprises fundamental clock, and the high impulse quantity of each output is evenly distributed in width-modulation pulse in normal period.

12. the device of demonstration control as claimed in claim 11 is characterized in that, the periodicity digital signal Q of described counter output _iThrough described logic combiner output A _i, from a high position to the low level, be output as A successively _(n-1), A _(n-2)..., A ₀, A _iMeet the following conditions:

$\mathrm{Ai}=\left\{\begin{array}{c}\mathrm{Qk}...............................................................i=n-1\\ \stackrel{\&OverBar;}{\mathrm{Qk}}*...*\stackrel{\&OverBar;}{Q_{[k-(n-1-i)-1]}}*Q_{[k-(n-1-i)]}..................n-k-1\&le;i<n-1\\ \stackrel{\&OverBar;}{Q0}*...*\stackrel{\&OverBar;}{Q_{[n-2-i]}}*Q_{[n-1-i]}..............................0\&le;i<n-k-1\end{array}\right.$

Wherein k is 0 or less than the positive integer of n; Thereby do not overlap after making the high impulse that overlaps originally by computing, to be fixed as 1/2 be 2 times of low level dutycycle through computing rear high-lying dutycycle to dutycycle originally.

13. the device of demonstration control as claimed in claim 12 is characterized in that described data strobe device comprises:

When this position of gating data is to be " very ", then gating mutually should the position by the gating data; When this position of gating data is " vacation ", then shielding mutually should the position by the gating data.

14. the device of demonstration control as claimed in claim 13 is characterized in that following formula is satisfied in the output of described data strobe device:

D _i＝M _i*A _i，

From a high position to the low level, be output as A successively by the gating data _(n-1), A _(n-2)..., A ₀, gated data is output as M successively from a high position to the low level _(n-1), M _(n-2)..., M ₀, output signal is output as D successively from a high position to the low level _(n-1), D _(n-2)..., D ₀When the figure place length of described gated data during less than n, the output D of described gated data _iAdd spot patch and be the n position together.

15. the device of demonstration control as claimed in claim 14 is characterized in that described logic combiner comprises:

With the output of data strobe device, carry out logical OR, and output pulse width modulating pulse pwm signal.

16. the device of demonstration control as claimed in claim 15 is characterized in that, the described width-modulation pulse PMW signal OUT of described logic combiner output satisfies following formula:

$\mathrm{OUT}=\underset{i=0}{\overset{i=n-1}{\mathrm{\&Sigma;}}}{D}_i.$

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