CN102176100B - Liquid crystal display device and forming method thereof - Google Patents

Liquid crystal display device and forming method thereof Download PDF

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CN102176100B
CN102176100B CN201110081985A CN201110081985A CN102176100B CN 102176100 B CN102176100 B CN 102176100B CN 201110081985 A CN201110081985 A CN 201110081985A CN 201110081985 A CN201110081985 A CN 201110081985A CN 102176100 B CN102176100 B CN 102176100B
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gate line
line
active layers
drain
overlapping region
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CN102176100A (en
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姚启文
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AU Optronics Corp
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AU Optronics Corp
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Abstract

The invention discloses a liquid crystal display device and a forming method thereof. The device comprises a gate line, an active layer, a pixel electrode, a source line and a drain line, wherein the gate line is formed on an insulating substrate; one side of a section of the gate line is raised to form a raised area, and the section is provided with a sunken area dead against the raised area; the active layer is formed on the section; the pixel electrode is formed on the raised side of the gate line; the source line crosses an overlapped area of the active layer and the gate line substantially vertically to the extension direction of the gate line to be extended out of the boundary of the active layer; and the drain line is coupled to the pixel electrode, and crosses the overlapped area of the active layer and the gate line substantially in parallel with the extension direction of the source line. In the liquid crystal display device and the forming method thereof, the deviation of gate-drain capacitors caused by the inaccurate alignment of a bench can be avoided, so the luminance non-uniformity of different areas of the liquid crystal display device can be prevented.

Description

Liquid crystal indicator and forming method thereof
The present invention is to be that Dec 26, application number in 2005 are 200510023091.1, denomination of invention is divided an application for " liquid crystal indicator and forming method thereof " the applying date.
Technical field
The invention relates to LCD (Liquid Crystal Display; And be particularly to a kind of thin film transistor (TFT) (Thin Film Transistor that avoids the gate-to-drain capacitance deviation LCD); TFT)-structure of LCD device.
Background technology
In recent years, flat-panel screens development replaces traditional crt display unit rapidly gradually, LCD especially, and range of application is contained to the large scale screen by mobile phone.In the middle of LCD, use the active matrix liquid crystal display of thin film transistor (TFT) to account for exhausted vast scale, reason is because its display effect is better than the passive matrix liquid crystal display.Therefore active matrix liquid crystal display is the research and development emphasis of current LCD.
Fig. 1 is the planimetric map that shows the central pixel cell of a typical thin film transistor-liquid crystal indicator (TFT-LCD).The pixel cell 10 of this TFT-LCD device comprises that a gate line 11 along continuous straight runs are arranged on the insulated substrate, and this gate line 11 has an outburst area as a grid 12.One active layers 13 is formed on the said grid 12, for example, is to be made up of amorphous silicon (amorphous silicon).One source pole line 14 extends with vertical direction and crosses over said gate line 11, and has an outburst area with as one source pole 15.One drain line 16 couples the bearing of trend of the said gate line 11 of a pixel electrode 18 and edge across grid 12, and has a drain electrode 17.Normally transparent by the one and conductive material that have conducted well power of pixel electrode 18 constitutes, and is tin indium oxide (indium-tin-oxide for example; ITO) or indium zinc oxide (indium-zinc-oxide; IZO).
In little shadow (photolithography) manufacture craft, board variation so that light shield when skew takes place in the forming process of TFT, the overlapping region between source electrode 15/ drain electrode 17 and the grid 12 can change.Fig. 2 shows that deviation takes place in exposure, and makes in the pixel cell of TFT-LCD device 10 source electrode 15/ drain electrode 17 planimetric map of skew to the right.Compare Fig. 1, the overlapping region increase of source electrode 15 and 12 of grids in Fig. 2, and drain 17 and the overlapping region of 12 of grids dwindle.Therefore, gate-to-source electric capacity (is designated hereinafter simply as C GS) increase, and gate-to-drain electric capacity (C GD) reduce.Otherwise, make source electrode 15 when exposure process generation deviation and drain 17 when squinting (not shown) left, C GSReduce, and C GDIncrease.
Fig. 3 is the equivalent circuit diagram of a pixel cell in the middle of the TFT-LCD, in order to explanation C GDInfluence for brightness.G representes grid among the figure, and S representes source electrode, and D represents drain electrode, C LCBe liquid crystal capacitance, C SBe storage capacitors, and these two electric capacity all are and are connected in a pixel electrode P and and share between the electrode C.When TFT-LCD opened, grid voltage equaled a relative high voltage V GH, and total electrical charge Q in the TFT-LCD 1With pixel electrode voltage V P1Between relational expression can be expressed as:
Q 1=C GD(V P1-V GH)+(C LC+C S)(V P1-V COM)...(1)
V wherein COMBe the voltage of shared electrode.
Otherwise when TFT-LCD closed, grid voltage equaled a relative low-voltage V GL, and total electrical charge Q in the TFT-LCD 2With pixel electrode voltage V P2Between relational expression can be expressed as:
Q 2=C GD(V P2-V GL)+(C LC+C S)(V P2-V COM)…(2)
Because the total electrical charge conservation, i.e. Q1=Q2, therefore can be known by (1) (2):
ΔV P=V P1-V P2=(V GH-V GL)(C GD/(C CL+C CS+C GD))…(3)
Can know Δ V by (3) P(being so-called returning (Kickback) voltage) is to receive C GDInfluence.Because the brightness of LCD is to be controlled by pixel electrode voltage, therefore if in little shadow manufacture craft the C of board variation so that zones of different TFT GDWhen deviation took place, the phenomenon of brightness irregularities will appear everywhere in LCD as a result, and was serious, just produces so-called " Mura ".Yet because the exposure accuracy of exposure machine is subject to certain limit so that can't be very accurate, the phenomenon of brightness irregularities everywhere appears in LCD at large.
Summary of the invention
It is in view of this, a kind of that to avoid thin film transistor (TFT)-LCD (TFT-LCD) device of gate-to-drain capacitance deviation be that those skilled in the art yearn for.
The present invention also provides a kind of liquid crystal indicator, comprising: a gate line is formed on the insulated substrate; Wherein one side of a section protrusion and form a raised zones in the middle of this gate line, and this section has a hole region and is right against said raised zones, and said hole region forms the zone of caving in; One pixel electrode is formed on the said insulated substrate; One active layers is formed on this gate line of said section, and this active layers and this gate line overlap to form an overlapping region; The one source pole line; According to substantially perpendicular to the bearing of trend of said gate line; Extend beyond the border of said active layers across the overlapping region of said active layers and said gate line, the edge of this source electrode line and said overlapping region in the distance of gate line direction greater than the precision variable quantity of exposure machine in the gate line direction; An and drain line; Couple said pixel electrode; Electrically connect with said pixel electrode; And according to the bearing of trend that is parallel to said source electrode line substantially, across and extend beyond overlapping region to this hole region of said active layers and said gate line and do not exceed the border of said active layers, the edge of this drain line and said overlapping region the gate line direction, perpendicular to the distance of gate line direction respectively greater than exposure machine in the gate line direction, perpendicular to the precision variable quantity of gate line direction.
The present invention is and a kind of formation method of liquid crystal indicator is provided; Comprise: on an insulated substrate, form a gate line; One side of a section protrusion in the middle of the wherein said gate line and form a raised zones; And have a hole region and be right against said raised zones, said hole region forms the zone of caving in; On this gate line of said section, form an active layers, this active layers and this gate line overlap to form an overlapping region; A definition one source pole line and a drain line on said active layers and insulated substrate; Making said source electrode line according to the border of coming to extend beyond said active layers substantially perpendicular to the bearing of trend of said gate line across the overlapping region of said active layers and said gate line, the edge of this source electrode line and said overlapping region in the distance of gate line direction greater than the precision variable quantity of exposure machine in the gate line direction; And make said drain line according to the bearing of trend that is parallel to said source electrode line substantially, by the said gate line protrusion side one predetermined zone that forms a pixel electrode, across and extend beyond the overlapping region of said active layers and said gate line To this hole region and do not exceed said master The border of moving layer, the edge of this drain line and said overlapping region the gate line direction, perpendicular to the distance of gate line direction respectively greater than exposure machine in the gate line direction, perpendicular to the precision variable quantity of gate line direction; And form a pixel electrode in said pixel electrode area, electrically connect with said drain line.
Show (TFT-LCD) device and forming method thereof through the tft liquid crystal that the present invention disclosed, can avoid gate-to-drain electric capacity deviation not to take place on time, thereby can take precautions against the phenomenon of LCD zones of different brightness irregularities in the board contraposition.
Yet structure of the present invention and its formation method together with its additional objects and advantage, need the description through following specific embodiment, and when reading with reference to the additional icon, can obtain the understanding of the best.
Description of drawings
Fig. 1 is the planimetric map of a pixel cell in the middle of the traditional TFT-LCD device;
Fig. 2 is the central pixel cell of traditional TFT-LCD device of Fig. 1 planimetric map that source/drain squints to the right when exposure;
Fig. 3 is the equivalent circuit diagram of a pixel cell in the middle of the TFT-LCD;
Fig. 4 A and Fig. 4 B are the planimetric maps that shows the embodiment of a pixel cell in the middle of the LCD device of the present invention, and near TFT, have different gate line width and have the different zones of caving in;
Fig. 5 A to Fig. 5 E is the sectional view that presents a pixel cell forming process in the middle of the LCD device of Fig. 4 A;
Fig. 6 A to Fig. 6 E is the planimetric map that presents a pixel cell forming process in the middle of the LCD device of Fig. 4 A;
Fig. 7 is the planimetric map that shows the embodiment of the central pixel cell of another LCD device of the present invention; And
Fig. 8 A to Fig. 8 E is the planimetric map that presents a pixel cell forming process in the middle of the LCD device of Fig. 7.
Symbol description:
One pixel cell of 10 ~ conventional thin film transistor-liquid crystal indicator
11 ~ gate line
12 ~ grid, 13 ~ active layers
14 ~ source electrode line, 15 ~ source electrode
16 ~ drain line 17 ~ drain electrode
18 ~ pixel electrode
40, a pixel cell of 40 ' ~ LCD device of the present invention
41 ~ gate line/conductive film 41a ~ raised zones
41b ~ zone 42 ~ grid caves in
43 ~ semiconductor layer/active layers 44 ~ source electrode line
45 ~ source electrode, 46 ~ drain line
47 ~ drain electrode, 48 ~ pixel electrode
52 ~ grid insulating film, 55 ~ passivation film
One pixel cell of 66 ~ contact hole 70 ~ LCD device of the present invention
71~gate line 71a 1~the first raised zones
71a 2~ the second raised zones 71b ~ zone of caving in
72 1~first grid 72 2~ second grid
73 1~ the first active layers 73 2~ the second active layers
74 1~ the first source electrode 74 2~ the second source electrode
76 1~the first drain line 76 2~ the second drain line
77 1~ the first drain electrode 77 2~ the second drain electrode
78 1~the first pixel electrode 78 2~ the second pixel electrode
86 1~ the first contact hole 86 2~ the second contact hole
Embodiment
The icon of this place reference does not reduce with equal proportion.The relative size of the different assemblies of describing not is in order to represent the ratio characteristic of these assembly physical sizes among the figure; And only in order to assist a ruler in governing a country those of ordinary skill in the art; Make it can clearly learn how to make and use the present invention, and understand and to contain the inventive concept could in the present invention.
With reference to figure 4A, it is the planimetric map that shows the embodiment of the central pixel cell of a LCD device of the present invention.As shown in the figure; In a pixel cell 40; One gate line 41 is formed on the insulated substrate (not shown); Wherein one side of a section protrusion and form a raised zones 41a in the middle of this gate line, and opposite side indent and form the regional 41b that caves in, it is right against said raised zones 41a.This section is as a grid 42.One active layers 43 is formed on the grid 42.One source pole line 44, has one source pole 45 across said active layers 43 on active layers 43 with the overlapping region of said gate line 41, and extends beyond the border of said active layers 43 perpendicular to the bearing of trend of said gate line 41 according to substantially.One drain line 46 couples a pixel electrode 48; And according to the bearing of trend that is parallel to said source electrode line 44 substantially; Raised zones 41a by said gate line 41 comes across the overlapping region of said active layers 43 with said gate line 41 toward the regional 41b that caves in, and has a drain electrode 47 on active layers 43.In said active layers 43, define passage area between said source electrode 45 and the drain electrode 47.Note that source electrode line 44 slightly bends towards drain line 46 on TFT, yet source electrode line also can be straight line, or extend perpendicular to the bearing of trend of said gate line 41 substantially with other and to get final product.
Obviously can know, cooperate under the variation of manufacture craft precision C in physical dimension GDCan not change because the manufacture craft precision changes thereupon.As shown in the figure, the bearing of trend of parallel gate polar curve 41 is called directions X, and the bearing of trend of vertical gate polar curve 41 is called the Y direction.If exposure machine has at directions X ± D XThe precision variable quantity, and the edge of source electrode line 44 and active layers 43 and the overlapping region of gate line 41 is L in the distance of directions X X1, drain line 46 is L with the edge of the overlapping region of active layers 43 and gate line 41 in the distance of directions X X2, so L X1With L X2Must be designed to greater than D XIn like manner, if exposure machine has ± D in the Y direction YThe precision variable quantity, drain line 46 and active layers 43 are L with the edge of the overlapping region of gate line 41 in the distance of Y direction Y, so L YMust be designed to greater than D YWhen reaching this designing requirement, if the exposure accuracy generation deviation of exposure machine, source electrode 45/ drain electrode 47 all keeps fixing with the overlapping area of grid 42, thus C GDChange little.
In addition, in order to reach gate line 41 low-resistance requirements, pixel cell 40 ' that can be shown in Fig. 4 B, gate line is to increase live width, and has a void space 41b over against said outburst area 41a.
Fig. 5 A to Fig. 5 E is that the LCD device with Fig. 4 A is an example, presents the sectional view of a pixel cell forming process in the middle of the LCD device of the present invention.Fig. 6 A to Fig. 6 E is that the LCD device with Fig. 4 A is an example, presents the planimetric map of a pixel cell forming process in the middle of the LCD device of the present invention, and Fig. 5 A to Fig. 5 E respectively among displayed map 6A to Fig. 6 E along the sectional view of straight line AA '.
At first, referring to Fig. 5 A, form a conductive film 41 on an insulated substrate 50 (a for example glass substrate), the material of wherein said conductive film 41 for example is aluminium (Aluminum; Al) or chromium (chromium; Cr) and so on low resistive metal or its alloy form with the single or multiple lift structure, and the formation method for example are to spatter the conventional deposition program of crossing (sputtering).Then, utilize an exposure imaging and etched program (photolithography-etching process) to be said conductive film 41 pattern-makings (patternning) again, to form a gate line 41 and grid 42 on insulated substrate 50.Shown in Fig. 6 A, one side of sections protrusion and form a raised zones 41a in the middle of the gate line 41, and this section has the regional 41b that caves in and is right against said raised zones 41a, and said section is as grid 42.
Next; Shown in Fig. 5 B and Fig. 6 B; Form a grid insulating film (for example being the mononitride layer) 52; And one the semiconductor layer 43 (for example being the amorphous silicon layer that comprises a doped N-type impurity) that constitutes by amorphous silicon (amorphous silicon) on the surface of structure that above-mentioned steps produces, and the formation method for example is to utilize electric pulp gas phase (plasma enhanced Chemical Vapor Deposition; PECVD) conventional deposition program, and be that said semiconductor layer 43 pattern-makings are to form an active layers 43 on grid 42 (with grid insulating film 52) subsequently.
Next, shown in Fig. 5 C and Fig. 6 C, form a conductive film on the whole surface of structure that above-mentioned steps produces, the material of wherein said conductive film for example is aluminium (Aluminum; Al) or chromium (chromium; Cr) and so on low resistive metal or its alloy; Form with the single or multiple lift structure; And the formation method for example is to utilize to spatter the conventional deposition program of crossing (sputtering) and so on; And utilize then exposure imaging and etched program come for said conductive film pattern-making forming an one source pole line 44 and a drain line 46, wherein said source electrode line 44 and drain line 46 have one source pole 45 and drain electrode 47 respectively on this active layers 43.Shown in Fig. 5 C; The program of this pattern-making be make source electrode line 44 according to substantially perpendicular to the bearing of trend of said gate line 41 across the overlapping region of said active layers 43 with said gate line 41; And said drain line 46 protrudes the zone that sides one preboarding becomes pixel electrode according to the bearing of trend that is parallel to said source electrode line 44 substantially by said gate line 41, next overlapping region across said active layers 43 and said gate line 41.
Next; Shown in Fig. 5 D and Fig. 6 D; Form a passivation film (passivation film) 55 on the whole surface of structure that above-mentioned steps produces; Wherein this passivation film 55 for example is the mononitride film, and the conventional deposition program of formation method utilization electricity slurry CVD, in said passivation film 55, utilizes exposure imaging and etched program to form a contact hole (contact hole) 61 subsequently and (is not shown in Fig. 5 D; And be shown in Fig. 6 D) so that outside a part of zone of said drain line 46 is exposed to.
Next; Shown in Fig. 5 E and Fig. 6 E; Forming a transparent conductive material on the whole surface of structure that above-mentioned steps produces, is tin indium oxide or indium zinc oxide for example, and to utilize an etching program be said conductive material pattern-making; So that this conductive material is connected to the exposed surface of said drain line 46; And form a pixel electrode 48, wherein this pixel electrode 48 is to be formed on a part of zone and contact hole 61 of drain line 46, and is formed on the contiguous passivation film 55 of said active layers 43 and TFT.Said pixel electrode 48 is to be connected to drain line 46 through the contact hole 61 in the passivation film 55.
It should be noted that structure of the present invention extendible be a double tft structure, to increase the conducting electric current.Fig. 7 is the planimetric map that shows the embodiment of the central pixel cell of another LCD device of the present invention, and it is the thin film transistor (TFT) that comprises two parallel connections.
As shown in Figure 7, in a pixel cell 70, a gate line 71 along continuous straight runs are arranged on the insulated substrate.The both sides of sections protrusion in the middle of the said gate line 71 and form the first raised zones 71a respectively 1And the second raised zones 71a 2, and have a hole region 71b in the said first raised zones 71a 1And the second raised zones 71a 2The centre, and this section is separated into first and second portion.Said first and second portion be not as first grid 72 1With second grid 72 2One first active layers 73 1And second active layers 73 2Be formed at said first grid 72 respectively 1With second grid 72 2On.One source pole line 74 is along substantially perpendicular to the bearing of trend of said gate line 71, across said first active layers 73 1The overlapping region and second active layers 73 with gate line first 2With the overlapping region of gate line 71 second portions, and on said overlapping region, has one first source electrode 75 respectively 1And second source electrode 75 2One first drain line 76 1According to the bearing of trend that is parallel to said source electrode line 74 substantially, by one first pixel electrode 78 1Across said first active layers 73 1With the overlapping region of said gate line 71 firsts, and on this overlapping region, has one first drain electrode 77 1Similarly, one second drain line 76 2According to the bearing of trend that is parallel to said source electrode line 74 substantially, by one second pixel electrode 78 2Across said second active layers 73 2With the overlapping region of said gate line 71 second portions, and on this overlapping region, has one second drain electrode 77 2First source electrode 75 1With first drain electrode 77 1Between, and second source electrode 75 2With second drain electrode 77 2Between, be respectively in said first active layers 73 1And second active layers 73 2In define a passage area.
This structure is a double tft structure, and it comprises the first film transistor and second thin film transistor (TFT) of two parallel connections.The first film transistor comprises first grid 72 1, first active layers 73 1, first source electrode 75 1, and first drain electrode 77 1And second thin film transistor (TFT) comprises second grid 72 2, second active layers 73 2, second source electrode 75 2, and second drain electrode 77 2In addition, note, slightly bend towards first and second drain line 76 when source electrode line 74 is through first and second thin film transistor (TFT) among the figure 1And 76 2Yet source electrode line 74 also can be a straight line, promptly extends perpendicular to the bearing of trend of said gate line 71 substantially along one to get final product.
The LCD device of this embodiment matches down C in physical dimension and the variation of manufacture craft precision GDPromptly can not change because the manufacture craft precision changes thereupon.As shown in the figure, the edge of source electrode line 74 and two active layers 73 1/ 73 2Be respectively L with the edge of the overlapping region of gate line 71 in the distance of directions X X11And L X12, and two drain lines 76 1And 76 2The edge respectively with two active layers 73 1, 73 2With the edge of the overlapping region of gate line 71 be L in the distance of directions X X21And L X22, and be L in the distance of Y direction Y1And L Y2If exposure machine has respectively ± D at X and Y direction XAnd ± D YThe precision variable quantity, then work as L X11, L X12, L X21, L X22Be designed to greater than D X, and L Y1With L Y2Be designed to greater than D YThe time, even the exposure accuracy generation deviation of exposure machine, source electrode line 74, first drain line 76 1With the overlapping area of gate line 71, and source electrode line 74, second drain line 76 2Can both keep fixing with the overlapping area of gate line 71, thus the C of first and second thin film transistor (TFT) GDChange all little.
The forming process of the LCD device of this double thin-film transistors be with Fig. 4 A in the forming process of LCD device of tool single-film transistor arrangement similar.For the purpose of simple, present the planimetric map of a pixel cell forming process in the middle of the LCD device of Fig. 7 at Fig. 8 A to Fig. 8 E, and omit illustrating and related description of sectional view.Forming process may further comprise the steps.
At first; Form a conductive film on an insulated substrate (a for example glass substrate); The material of wherein said conductive film for example is low resistive metal or its alloy of aluminium or chromium and so on, form with the single or multiple lift structure, and the formation method for example is to spatter the conventional deposition program of crossing.Then, utilizing an exposure imaging and etched program again is said conductive film pattern-making, to form a gate line 71 on this insulated substrate.Shown in Fig. 8 A, the both sides of sections protrusion in the middle of the said gate line 71 and form the first raised zones 71a respectively 1And the second raised zones 71a 2, and have a hole region 71b and said section is separated into first grid 72 1With second grid 72 2
Next, on the surface of structure that above-mentioned steps produces, form a grid insulating film (for example being the mononitride layer), and the semiconductor layer (analogy is the amorphous silicon layer that comprises a doped N-type impurity) of amorphous silicon formation.And the analogy of formation method is a conventional deposition program of utilizing electric pulp gas phase.Afterwards, be said amorphous silicon pattern-making again with at said first grid 72 1On (grid insulating film adjacent thereto), and second grid 72 2On (grid insulating film adjacent thereto), form one first active layers 73 respectively 1And second active layers 73 2, shown in Fig. 8 B.
Next, form a conductive film on the whole surface of structure that above-mentioned steps produces.The material of this conductive film is low resistive metal or its alloy of aluminium or chromium and so on for example, form with the single or multiple lift structure, and the formation method for example is to utilize to spatter the conventional deposition program of crossing.Then, utilize an exposure imaging and etched program to come to be said conductive film pattern-making again, to form one source pole line 74, first drain line 76 1, and second drain line 76 2Referring to Fig. 8 C, the program of this pattern-making be make source electrode line 74 according to substantially perpendicular to the bearing of trend of gate line 71 across first active layers 73 1And second active layers 73 2With the overlapping region of said gate line 71, and make first drain line 76 1And second drain line 76 2According to the bearing of trend that is parallel to said source electrode line 74 substantially, wherein come across first active layers 73 in a side one predetermined zone that forms first and second electrode by said gate line respectively 1And second active layers 73 2Overlapping region with this gate line 71.
Next, form a passivation film on the whole surface of structure that above-mentioned steps produces.This passivation film is the mononitride film for example.And the formation method for example is the conventional deposition program of electricity slurry CVD.Subsequently, in said passivation film, carry out an exposure imaging and etched program, to form one first contact hole 86 1And second contact hole 86 2, and make first drain line 76 1And second drain line 76 2A part of zone be exposed to outside, shown in Fig. 8 D.
Next, form a transparent conductive material on the whole surface of structure that above-mentioned steps produces, be tin indium oxide or indium zinc oxide for example, and utilize an etching program to come to be said conductive material pattern-making, so that said conductive material is connected to first drain line 76 1And second drain line 76 2Exposed surface, and form first pixel electrode 78 1And second pixel electrode 78 2Referring to Fig. 8 E, the process of pattern-making is to make first pixel electrode 78 1Be formed at first drain line 76 1A part of zone and first contact hole 86 1Go up and the transistorized contiguous passivation film of the first film on; And make second pixel electrode 78 2Be formed at second drain line 76 2A part of zone and second contact hole 86 2Go up and the contiguous passivation film of second thin film transistor (TFT) on.Thus, first pixel electrode 78 1Can pass through first contact hole 86 1Be connected to first drain line 76 1, and second pixel electrode 78 2Can pass through second contact hole 86 2Be connected to second drain line 76 2
Though the present invention discloses as above with preferred embodiment; Right its is not that any people who has the knack of this skill is not breaking away from the spirit and scope of the present invention in order to qualification the present invention; When can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that claim defines.

Claims (2)

1. liquid crystal indicator is characterized in that comprising:
One gate line is formed on the insulated substrate;
Wherein one side of a section protrusion and form a raised zones in the middle of this gate line, and this section has a hole region and is right against said raised zones, and said hole region forms the zone of caving in;
One pixel electrode is formed on the said insulated substrate;
One active layers is formed on this gate line of said section, and this active layers and this gate line overlap to form an overlapping region;
The one source pole line; According to substantially perpendicular to the bearing of trend of said gate line; Extend beyond the border of said active layers across the overlapping region of said active layers and said gate line, the edge of this source electrode line and said overlapping region in the distance of gate line direction greater than the precision variable quantity of exposure machine in the gate line direction; And
One drain line; Couple said pixel electrode; Electrically connect with said pixel electrode; And according to the bearing of trend that is parallel to said source electrode line substantially, across and extend beyond overlapping region to this hole region of said active layers and said gate line and do not exceed the border of said active layers, the edge of this drain line and said overlapping region the gate line direction, perpendicular to the distance of gate line direction respectively greater than exposure machine in the gate line direction, perpendicular to the precision variable quantity of gate line direction.
2. the formation method of a liquid crystal indicator is characterized in that comprising:
On an insulated substrate, form a gate line,
One side of a section protrusion and form a raised zones in the middle of the wherein said gate line, and have a hole region and be right against said raised zones, said hole region forms the zone of caving in;
On this gate line of said section, form an active layers, this active layers and this gate line overlap to form an overlapping region;
A definition one source pole line and a drain line on said active layers and insulated substrate; Making said source electrode line according to the border of coming to extend beyond said active layers substantially perpendicular to the bearing of trend of said gate line across the overlapping region of said active layers and said gate line, the edge of this source electrode line and said overlapping region in the distance of gate line direction greater than the precision variable quantity of exposure machine in the gate line direction; And make said drain line according to the bearing of trend that is parallel to said source electrode line substantially; By the said gate line protrusion side one predetermined zone that forms a pixel electrode; Across and extend beyond overlapping region to this hole region of said active layers and said gate line and do not exceed the border of said active layers, the edge of this drain line and said overlapping region the gate line direction, perpendicular to the distance of gate line direction respectively greater than exposure machine in the gate line direction, perpendicular to the precision variable quantity of gate line direction; And
Form a pixel electrode in said pixel electrode area, electrically connect with said drain line.
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CN1492273A (en) * 2002-10-21 2004-04-28 Lg.������Lcd���޹�˾ Liquid crystal display array substrate and its producing method

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