CN102169861A - Semiconductor structure with passive component structure and manufacture method thereof - Google Patents
Semiconductor structure with passive component structure and manufacture method thereof Download PDFInfo
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- CN102169861A CN102169861A CN2011100374824A CN201110037482A CN102169861A CN 102169861 A CN102169861 A CN 102169861A CN 2011100374824 A CN2011100374824 A CN 2011100374824A CN 201110037482 A CN201110037482 A CN 201110037482A CN 102169861 A CN102169861 A CN 102169861A
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- H01—ELECTRIC ELEMENTS
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Abstract
The invention discloses a semiconductor structure with a passive component structure and a manufacture method thereof. The semiconductor structure comprises an insulation substrate, a passive component structure layer, an electric contact and a dielectric layer, wherein the passive component structure layer is formed on the insulation substrate; the electric contact is formed on the passive component structure layer; and the dielectric layer covers one part of the electric contact, and the other part of the electric contact is exposed from an opening of the dielectric layer.
Description
Technical field
The invention relates to a kind of semiconductor structure and manufacture method thereof, and particularly relevant for a kind of semiconductor structure and manufacture method thereof with passive component.
Background technology
Traditional interposer substrate (interposer) comprises a silicon substrate, an insulating barrier and a line layer.Insulating barrier is formed on the silicon substrate, and line layer is formed on the insulating barrier.Because silicon substrate do not have insulating properties, therefore need to isolate line layer and silicon substrate via insulating barrier, make line layer and unlikely the electrically conducting of silicon substrate and cause short circuit.
Yet derive at least one light shield technology cost of the formation of insulating barrier causes technology cost and process complexity to increase.
Summary of the invention
The present invention is relevant for a kind of semiconductor structure and manufacture method thereof, and semiconductor structure adopts the substrate of tool insulating properties, can reduce the formation of insulating barrier, to reduce manufacturing cost, to save the process time.
According to an aspect of the present invention, a kind of semiconductor structure is proposed.Semiconductor structure comprises an insulated substrate, a passive component structure layer, one first electrical contact and one first dielectric layer.The passive component structure layer is formed at insulated substrate.First electrical contact is formed at the passive component structure layer.First dielectric layer covers the part of first electrical contact, and wherein, first dielectric layer has one first perforate, and another part of first electrical contact exposes from first perforate.
A kind of manufacture method of semiconductor structure is proposed according to a further aspect in the invention.Manufacture method may further comprise the steps.One insulated substrate is provided; Form a passive component structure layer in insulated substrate; Form one first electrical contact in the passive component structure layer; And, form the part that one first dielectric layer covers first electrical contact, wherein first dielectric layer has one first perforate, and another part of first electrical contact exposes from first perforate.
For there is better understanding above-mentioned and other aspect of the present invention, at least one embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Figure 1A illustrates the cutaway view according to the semiconductor structure of one embodiment of the invention.
Figure 1B illustrates the enlarged diagram of local 1B ' among Figure 1A.
Fig. 2 illustrates the top view of resistance among Fig. 1, electric capacity and induction structure.
Fig. 3 illustrates the cutaway view according to the semiconductor structure of yet another embodiment of the invention.
Fig. 4 illustrates the cutaway view according to the semiconductor structure of other embodiment of the present invention.
Fig. 5 illustrates the cutaway view according to the semiconductor structure of another embodiment of the present invention.
Fig. 6 A illustrates the cutaway view according to the semiconductor structure of further embodiment of this invention.
Fig. 6 B illustrates the enlarged diagram of local 6B ' among Fig. 6 A.
Fig. 7 A to 7G illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 1.
Fig. 8 illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 3.
Fig. 9 illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 4.
Figure 10 illustrates the top view of the circulus of Fig. 9.
Figure 11 illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 5.
Figure 12 A to 12D illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 6 A.
The primary clustering symbol description:
100,200,300,400,500: semiconductor structure
102,302: insulated substrate
102a, 112b, 302a: first
102b, 302b: second
104,204,304: the passive component structure layer
106,206,306: the first electrical contact
106a: the part of first electrical contact
106a1,106b1,108b: upper surface
106b: another part of first electrical contact
108,208,308: the first dielectric layers
108a: first perforate
110: the first line layers
110a: first conductive layer
110b: second conductive layer
110c: capacitance dielectric layer
110d: the 3rd conductive layer
112,312: the second dielectric layers
112a: second perforation
112c: the second perforation madial wall
114: the second Seed Layer
114a: another part of second Seed Layer
114s, 320s: side
116,216: the second line layers
116a, 216a: expose upper surface
116a1 a: part of exposing upper surface
116a2: the another part that exposes upper surface
122,124: the patterning photoresist layer
122a: form the district
302c: first perforation
302d: the first perforation madial wall
318: the second electrical contact
318a: the part of second electrical contact
318b: another part of second electrical contact
320: the first Seed Layer
326: support plate
428,528: circulus
530: organic polymer material
C: capacitance structure
L: induction structure
P: Cutting Road
R: electric resistance structure
RP: cellular zone
Embodiment
Used herein " vicinity " expression near or link together.Adjacent assembly can separated from each other or directly be connected to each other.In some instances, adjacent assembly can refer to be connected to each other or integrated to each other assembly.
Please refer to Figure 1A and Figure 1B, Figure 1A illustrates the cutaway view according to the semiconductor structure of one embodiment of the invention, and Figure 1B illustrates the enlarged diagram of local 1B ' among Figure 1A.Shown in Figure 1A, semiconductor structure 100 comprises insulated substrate 102, passive component structure layer 104, first electrical contact 106 and first dielectric layer 108.
The passive component structure layer is formed on the insulated substrate, and first electrical contact is formed on the passive component structure layer.For example, insulated substrate 102 has relative first 102a and second 102b.Passive component structure layer 104 is formed on first 102a of insulated substrate 102, and first electrical contact 106 is formed on the passive component structure layer 104.First 102a and second 102b are respectively the upper surface and the lower surface of insulated substrate 102 in the present embodiment.
First electrical contact 106 can be single layer structure or sandwich construction, and its material is comprising tin (immersion Sn), change silver (immersion Ag), chemical nickel and gold (ENIG), copper facing, plating iron, nickel plating or organic weldering film (OSP) at least; Perhaps, first electrical contact 106 also can be made up of the group that copper (Cu), nickel (Ni), palladium (Pd) and gold (Au) are constituted; Perhaps, and bump metal bottom first electrical contact 106 also can be (Under Bump Metallization, UBM).
First dielectric layer is suppressed first electrical contact, and first electrical contact firmly is formed on the passive component structure layer.For example, first dielectric layer 108 covers a part of 106a of first electrical contact 106, for example be the upper surface 106a1 that covers a part of 106a of first electrical contact 106, and another part 106b of first electrical contact 106 exposes.This part 106a of first dielectric layer, 108 compactings, first electrical contact 106 more securely is formed on the passive component structure layer 104 first electrical contact 106.
First dielectric layer 108 has at least one first perforate 108a, and another part 106b of first electrical contact 106 exposes from the first perforate 108a.Say further, first electrical contact 106 does not protrude in the upper surface 108b of first dielectric layer 108, but expose from the first perforate 108a, the upper surface 106b1 of another part 106b that makes the upper surface 108b of first dielectric layer 108 and first electrical contact 106 is at a distance of a distance.
The passive component structure layer comprises in resistance, inductance and the capacitance structure at least one.For example, please be simultaneously with reference to 1A, 1B and Fig. 2, Fig. 2 illustrates the top view of resistance among Fig. 1, electric capacity and induction structure, and the first conductive layer 110a, the second conductive layer 110b and the 3rd conductive layer 110d will be in follow-up (Fig. 5 A) explanations among Fig. 2.Shown in Figure 1A, passive component structure layer 104 comprises first line layer 110, second dielectric layer 112, second Seed Layer 114 and second line layer 116.First line layer 110 constitutes at least one electric resistance structure R and at least one capacitance structure C, and second line layer 116 constitutes at least one induction structure L.Specifically, first line layer 110 is formed on first 102a of insulated substrate 102, second dielectric layer 112 covers first line layer 110, wherein second dielectric layer 112 has at least one second perforation 112a, first 112b and the second perforation madial wall 112c, the second perforation 112a extends to first line layer 110 from first 112b, the second perforation madial wall 112c is corresponding to the second perforation 112a, and the part of first line layer 110 is exposed from the second perforation 112a.Second Seed Layer 114 is formed between second line layer 116 and second dielectric layer 112.
First electrical contact 106 is formed on second line layer 116 of passive component structure layer 104.First electrical contact 106 can be used as the electrode of the external electric connection of passive component structure layer 104.
First electrical contact only covers the part of second line layer.For example, second line layer 116 has an exposing surface, for example is to expose upper surface 116a.First electrical contact 106 only covers a part of 116a1 that exposes upper surface 116a of second line layer 116, and another part 116a2 that exposes upper surface 116a is not covered by first electrical contact 106.
Semiconductor structure can more comprise a circulus, and it defines Cutting Road, can avoid in the cutting technique, and the electric resistance structure of passive component structure layer, capacitance structure and induction structure are cut.For example, please refer to Fig. 3, it illustrates the cutaway view according to the semiconductor structure of yet another embodiment of the invention.Semiconductor structure 400 more comprises circulus 428, and first 102a of its contiguous insulated substrate 102 forms, and second dielectric layer 112 coats circulus 428.Circulus 428 is around electric resistance structure R, capacitance structure C and the induction structure L of passive component structure layer 104, and can not be electrically connected at any circuit unit.Again for example, please refer to Fig. 4, it illustrates the cutaway view according to the semiconductor structure of other embodiment of the present invention.The circulus 528 of semiconductor structure 500 comprises circulus 428 and organic polymer material 530, and first 102a of its contiguous insulated substrate 102 forms, and is positioned at outside second dielectric layer 112.Again for example, in the semiconductor structure 500 of an enforcement aspect, also can omit circulus 428.Perhaps, in the semiconductor structure 500 of another enforcement aspect, also can omit organic polymer material 530.
In addition, circulus 428 and 528 material can be selected from the group that metal, organic polymer material (organicpolymer) and combination thereof are constituted.Wherein, metal for example is the single or multiple lift structure of electro-coppering, nickel, palladium or sputtering aluminum etc., and organic polymer material for example is polyimides (PI) or benzocyclobutene (BCB) or other organic polymer material.For example, the circulus 428 of Fig. 3 can be a metal.Again for example, the combination of circulus 528 circuluses 428 (can be metal) of Fig. 4 and organic polymer material 530.
In another embodiment, first electrical contact can cover whole second line layer, for example, please refer to Fig. 5, and it illustrates the cutaway view according to the semiconductor structure of another embodiment of the present invention.Semiconductor structure 200 comprises insulated substrate 102, passive component structure layer 204, first electrical contact 206 and first dielectric layer 208.The passive component structure layer 204 and first dielectric layer 208 hold this and repeat no more similar in appearance to the above-mentioned passive component structure layer 104 and first dielectric layer 108.First electrical contact 206 of semiconductor structure 200 covers the whole upper surface 216a that exposes of second line layer 216 fully.Wherein, the material of first electrical contact 206 is same as first electrical contact 106, holds this and repeats no more.In the semiconductor structure 200 of present embodiment, the part of first dielectric layer, 208 compactings, first electrical contact 206, this feature similarity first dielectric layer 108 in semiconductor structure 100 is suppressed feature on first electrical contact 106 with first electrical contact 106, holds this and repeats no more.
In addition, in the enforcement aspect, semiconductor structure 200 more comprises circulus 428 or 528.
Above-mentioned semiconductor structure 100,200,400 and 500 one-sided structures with electrical contact, in the semiconductor structure of right another embodiment, many sides of semiconductor structure can have electrical contact respectively.For example, please refer to Fig. 6 A and 6B, Fig. 6 A illustrates the cutaway view according to the semiconductor structure of further embodiment of this invention, and Fig. 6 B illustrates the enlarged diagram of local 6B ' among Fig. 6 A.Semiconductor structure 300 comprises insulated substrate 302, passive component structure layer 304, first electrical contact 306, first dielectric layer 308, second electrical contact 318 and first Seed Layer 320.
The structure of first dielectric layer 308, first electrical contact 306 and passive component structure layer 304 and material are held this and are repeated no more respectively similar in appearance to said first dielectric layer 208, first electrical contact 206 and passive component structure layer 204.
First electrical contact 306 and second electrical contact 318 are respectively the electrical contact of relative two sides of semiconductor structure.Insulated substrate 302 has relative first 302a and second 302b.Passive component structure layer 304 is formed on first 302a, and first electrical contact 306 is formed on the passive component structure layer 304 electrically to be contacted with passive component structure layer 304, becomes the electrical contact of a side of semiconductor structure 300.Insulated substrate 302 has at least one first perforation 302c, and second electrical contact 318 is formed at the first perforation 302c and electrically is contacted with passive component structure layer 304, becomes the electrical contact of a relative side of semiconductor structure 300.
At least a portion of second electrical contact is formed in first perforation of insulated substrate, to be electrically connected at the passive component structure layer.For example, a part of 318a of second electrical contact 318 is positioned at the first perforation 302c, second 302b that another part 318b of second electrical contact 318 can be close to insulated substrate 302 forms, for example be to be formed on first Seed Layer 320 of contiguous second 302b, make another part 318b of second electrical contact 318 protrude in second 302b, to contact with the electrical electrical component in outside.
Shown in Fig. 6 B, insulated substrate 302 has more the first perforation madial wall 302d of the corresponding first perforation 302c.First Seed Layer 320 is formed between the first perforation madial wall 302d and second electrical contact 318 of insulated substrate 302.First line layer covers at least a portion of first Seed Layer, and for example, first Seed Layer 320 is covered by second electrical contact 318 fully and only exposes the side 320s of first Seed Layer 320.
In addition, in the enforcement aspect, semiconductor structure 300 more comprises circulus 428 or 528.
Below explanation is according to the manufacture process of the semiconductor structure of one embodiment of the invention.Semiconductor structure 100 with Fig. 1 is the example explanation, please refer to Fig. 7 A to 7G, and it illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 1.
At first, provide insulated substrate 102 shown in Fig. 7 A.
Then, form passive component structure layer 104 on first 102a of insulated substrate 102.In this step, there is several different methods to form passive component structure layer 104, below enumerates wherein a kind of explanation.
At first, shown in Fig. 7 A, form first line layer 110 on first 102a of insulated substrate 102.Wherein, first line layer 110 has at least one electricity group structure R and at least one capacitance structure C.
Form in the step of first line layer 110, any that can use several materials formation method forms an electric conducting material, for example is that the mode with chemical vapour deposition (CVD), electroless plating method (electroless plating), metallide (electrolyticplating), printing, spin coating, spraying, sputter (sputtering) or vacuum deposition method (vacuum deposition) forms electric conducting material; Then, form first line layer 110 in the application patterning techniques.Patterning techniques for example is lithography process (photolithography), chemical etching (chemical etching), laser drill (laserdrilling) or machine drilling (mechanical drilling).
The first line layer sandwich construction is to constitute passive component structure.For example, first line layer 110 comprises the first conductive layer 110a, the second conductive layer 110b, capacitance dielectric layer 110c and the 3rd conductive layer 110d, the first conductive layer 110a is formed on first 102a of insulated substrate 102, and the second conductive layer 110b is formed on the first conductive layer 110a, and capacitance dielectric layer 110c is between the second conductive layer 110b and the 3rd conductive layer 110d.
The first conductive layer 110a can be used as electric resistance structure.The material high resistance material of the first conductive layer 110a for example is tantalum nitride (TaN), PbTiO
3, ruthenic oxide (RuO
2), nickel phosphide (NiP), chromaking nickel (NiCr) and NCAlSi.
The second conductive layer 110b and the 3rd conductive layer 110d can be by the good materials of conductivity, for example be aluminium (Al) and copper (Cu) at least one form.
Then, shown in Fig. 7 B, form second dielectric layer 112 and cover first line layer 110.Wherein, second dielectric layer 112 has at least one second perforation 112a, first 112b and the second perforation madial wall 112c, and the second perforation 112a extends to first line layer, 110, the second perforation madial wall 112c corresponding to the second perforation 112a from first 112b.The part of first line layer 110 is exposed from the second perforation 112a, and wherein, this part that first line layer 110 exposes for example is at least one electrical contact, a plus or minus electrode among electricity group structure R and the capacitance structure C.
The material of second dielectric layer 112 is made up of polyimides (PI) or benzocyclobutene (BCB).The mode that forms second dielectric layer 112 comprises coating technique, for example is printing (printing), spin coating (spinning) or spraying (spraying).In addition, the generation type of second dielectric layer 112 also can comprise above-mentioned patterning techniques.
Then, form second Seed Layer in the second perforation madial wall and second dielectric layer.For example, shown in Fig. 7 C,, form whole first 112b that second Seed Layer 114 covers the whole second perforation madial wall 112c and second dielectric layer 112 with electroless plating method or sputtering method.
Then, shown in Fig. 7 D, electrically connect, form second line layer 116 on second Seed Layer 114 via the electrode (not illustrating) of second Seed Layer 114 with electroplating device.Second line layer 116 has induction structure L.So far, form passive component structure layer 104.Wherein, the material of second line layer 116 can be a metal, for example is that copper is formed.
Before forming second line layer 116, can form a patterning photoresist layer 122 on second Seed Layer 114.Wherein, patterning photoresist layer 122 for example is the eurymeric photoresistance, the formation district 122a (being the vacancy section of the patterning photoresist layer 122 of Fig. 7 D) of patterning photoresist layer 122 definition second line layer 116.Afterwards, use electro-plating method again and form second line layer 116 in forming district 122a.Above-mentioned exposing in upper surface 116a second line layer 116 from forming the surface that district 122a exposes.
The method that forms patterning photoresist layer 122 has several.For example, form a photoresist (not illustrating) with above-mentioned material formation method or coating process earlier, and then with above-mentioned patterning method, this photoresist of patterning is to form patterning photoresist layer 122.
After second line layer 116 forms,, remove patterning photoresist layer 122 for example to be to peel off (strip) or etching (etching) technology.
Then, shown in Fig. 7 E, form at least one first electrical contact 106 on passive component structure layer 104.Wherein, the formation of first electrical contact 106 for example to be electroplating technology, forms first electrical contact 106 via second Seed Layer 114 on second line layer 116.Say further, electrically connect with electroplating device via formed second Seed Layer 114 of preceding step, and form first electrical contact 106 shown in Fig. 7 E, so can shorten the process time, reduce cost and enhance productivity.
Before forming first electrical contact 106,, form a patterning photoresist layer 124 on second Seed Layer 114 with formation method similar in appearance to patterning photoresist layer 122.Wherein, patterning photoresist layer 124 for example is the eurymeric photoresistance, the formation district of patterning photoresist layer 124 definition first electrical contact 106.Afterwards, for example being that electroplating technology forms at least one first electrical contact 106 in this formation district.
After first electrical contact 106 forms,, remove patterning photoresist layer 124 for example to be to peel off or etching technique.
In the present embodiment, first electrical contact 106 is formed on the part of second line layer 116, for example is the part of exposing upper surface 116a of second line layer 116.
Then, shown in Fig. 7 F,, remove the part of second Seed Layer 114, keep another part 114a of second Seed Layer 114 for example to be etching technique.Wherein, the part that this part that is removed in second Seed Layer 114 is not covered by second line layer 116, and the part that another part 114a of second Seed Layer 114 is covered by second line layer 116.
After removing the step of this part of second Seed Layer 114, but application examples plasma process and acid cleaning process in this way remove or clean the residual patterning photoresist layer 124 and second Seed Layer 114.
Then, form a part of 106a of first dielectric layer, 108 coverings, first electrical contact 106 shown in Fig. 7 G.Wherein, first dielectric layer 108 has the first perforate 108a, and another part 106b of first electrical contact 106 exposes from the first perforate 108a.
The mode that forms first dielectric layer 108 is held this and is repeated no more similar in appearance to the mode that forms second dielectric layer 112.
Afterwards, shown in Fig. 7 G, but application examples cutter or laser cutting technique in this way cut first dielectric layer 108, second dielectric layer 112 and insulated substrate 102 at least, to form at least just like semiconductor structure shown in Figure 1 100.
The manufacture process of the semiconductor structure 400 of following key diagram 3.Please refer to Fig. 8, it illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 3.Form circulus 428, wherein circulus 428 is around the passive component (electric resistance structure R, capacitance structure C and induction structure L (induction structure L is illustrated in Fig. 7 F)) of passive component structure layer 104.Circulus 428 can form in same technology in the lump with first line layer 110, for example, and the part of circulus 428 first conductive layer 110a.So, circulus 428 also can form respectively with first line layer 110.Second dielectric layer 112 of follow-up formation can coat whole circulus 428, as shown in Figure 3.
The manufacture process of the semiconductor structure 500 of following key diagram 4.Please refer to Fig. 9, it illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 4.After second dielectric layer 112 forms, form circulus 528.The organic polymer material 530 of circulus 528 can form in same technology in the lump with second dielectric layer 112; Perhaps, the organic polymer material 530 and second dielectric layer 112 form respectively.Please refer to Figure 10 (illustrating a plurality of cellular zone RP), it illustrates the top view of the circulus of Fig. 9.Circulus 528 defines at least one Cutting Road P, therefore in cutting step, can avoid cutting to the passive component structure layer 104 that is positioned at cellular zone RP, for example is electric resistance structure R, capacitance structure C and induction structure L (not being illustrated in Figure 10).
The manufacture process of the semiconductor structure 200 of following key diagram 3.In the manufacture method of semiconductor structure 200, form step before first electrical contact 206, hold this and repeat no more, below begin explanation from the step that forms first electrical contact 206 haply similar in appearance to the manufacture method of semiconductor structure 100.
Please refer to Figure 11, it illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 3.Form first electrical contact 206 on passive component structure layer 204.For example, the whole of second line layer 216 of first electrical contact, 206 covering passive component structure layers 204 exposes on the upper surface 216a.Say further, in the step that forms first electrical contact 206, use to form the employed patterning photoresist layer 122 of second line layer 116 (as Fig. 7 D), therefore make first electrical contact 206 cover the whole upper surface 216a that exposes.In the case, the step that forms second line layer is used with light shield (being the patterning photoresist layer 124 that can omit Fig. 7 E in the manufacture process of semiconductor structure 200) with the step that forms first electrical contact, can save the technology cost, reduces the process time and improve process efficiency.
Forming after first electrical contact 206, can for example be to peel off or etching technique, removes the patterning photoresist layer 122 of Figure 11.
Below with the manufacture process of the semiconductor structure 300 of Figure 12 A to 12D key diagram 6A.Figure 12 A to 12D illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 6 A.In the manufacture method of semiconductor structure 300, form step before first dielectric layer, hold this and repeat no more, below after the step that forms first dielectric layer 308, begin explanation haply similar in appearance to the step of making semiconductor structure 100 or 200.
After the step that forms first dielectric layer 308, the passive component structure layer is set on support plate.For example, shown in Figure 12 A, passive component structure layer 304 is set on support plate 326, wherein, support plate 326 has adhesive layer (not illustrating), passive component structure layer 304 sticks on this adhesive layer, and second 302b that makes insulated substrate 302 for example is down toward the outer side, so this is non-in order to restriction the present invention, in other enforcement aspect, second 302b of insulated substrate 302 can for example be up towards the direction of convenient working.
Then, form at least one first perforation and run through insulated substrate.For example, shown in Figure 12 B,, form at least one first perforation 302c and run through insulated substrate 302 for example to be laser processing technology, Machining Technology or chemical etch technique.Wherein, the first perforation 302c extends to second 302b from first 302a of insulated substrate 302.After the first perforation 302c formed, insulated substrate 302 formed the first perforation madial wall 302d of the corresponding first perforation 302c.
In other enforcement aspect, form before the first perforation 302c, can be from second 302b grinding insulated substrate 302 of insulated substrate 302, to reduce the thickness of insulated substrate 302.
Then, form first Seed Layer second in the first perforation madial wall and insulated substrate.For example, shown in Figure 12 C,, form whole second 302b that first Seed Layer 320 covers whole first perforation madial wall 302d and insulated substrate 302 for example to be electroless plating (Electro-less) method or sputtering method.
Then, form second electrical contact in first perforation.For example, shown in Figure 12 D, form second electrical contact 318 on first Seed Layer 320, a part of 318a of second electrical contact 318 is positioned at the first perforation 302c, and second 302b of the contiguous insulated substrate 302 of another part 318b of second electrical contact 318 forms, and for example is to be formed on first Seed Layer 320 of contiguous second 302b.
Then, for example to be cutter or laser cutting technique, first dielectric layer 308, second dielectric layer 312 and the insulated substrate 302 of cutting drawing 12D at least are to form at least just like the semiconductor structure 300 shown in Fig. 6 A.
Semiconductor structure of the above embodiment of the present invention and manufacture method thereof have multinomial feature, and it is as follows to enumerate the part feature description:
(1). semiconductor structure adopts the substrate of tool insulating properties, can reduce the formation of insulating barrier, to reduce manufacturing cost, to save the process time.
(2). first dielectric layer is suppressed first electrical contact, and first electrical contact firmly is formed on the passive component structure layer.
(3). same patterning photoresist layer is shared in the formation of second line layer and first electrical contact, can save technology cost and time.
In sum, though the present invention discloses as above with several embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (20)
1. semiconductor structure with passive component structure comprises:
One insulated substrate;
One passive component structure layer is formed at this insulated substrate;
One first electrical contact is formed at this passive component structure layer; And
One first dielectric layer covers the part of this first electrical contact, and wherein this first dielectric layer has one first perforate, and another part of this first electrical contact exposes from this first perforate.
2. semiconductor structure as claimed in claim 1, wherein this insulated substrate has one first perforation, and this semiconductor structure more comprises:
One second electrical contact is formed at this first perforation.
3. semiconductor structure as claimed in claim 2, wherein this insulated substrate has relative one first and one second, this passive component structure layer is formed at this first of this insulated substrate, the part of this second electrical contact is positioned at this first perforation, this second formation of contiguous this insulated substrate of another part of this second electrical contact.
4. semiconductor structure as claimed in claim 2 more comprises:
One first Seed Layer is formed between this insulated substrate and this second electrical contact.
5. semiconductor structure as claimed in claim 1, wherein this passive component structure layer comprises:
One first line layer is formed on this insulated substrate;
One second dielectric layer, cover this first line layer, wherein this second dielectric layer has one second perforation, one first and one second perforation madial wall, this second perforation extends to this first line layer from this first face of this second dielectric layer, this second perforation madial wall is corresponding to this second perforation, and this first line layer exposes from this second perforation;
One second line layer;
One second Seed Layer is formed between this second line layer and this second dielectric layer; And
Wherein, this first electrical contact is formed on this second line layer of this passive component structure layer.
6. semiconductor structure as claimed in claim 5, wherein this second line layer has an exposing surface, and this first electrical contact covers whole this exposing surface of this second line layer.
7. semiconductor structure as claimed in claim 5, wherein this second line layer has an exposing surface, and this first electrical contact only covers the part of this exposing surface of this second line layer.
8. semiconductor structure as claimed in claim 1, wherein this insulated substrate glass substrate or ceramic substrate.
9. semiconductor structure as claimed in claim 1 more comprises:
One circulus is around the passive component of this passive component structure layer.
10. manufacture method with semiconductor structure of passive component structure comprises:
One insulated substrate is provided;
Form a passive component structure layer in this insulated substrate;
Form one first electrical contact in this passive component structure layer; And
Form the part that one first dielectric layer covers this first electrical contact, wherein this first dielectric layer has one first perforate, and another part of this first electrical contact exposes from this first perforate.
11. manufacture method as claimed in claim 10 more comprises:
Form one first perforation and run through this insulated substrate; And
Form one second electrical contact in this first perforation.
12. manufacture method as claimed in claim 11 wherein provides in this step of this insulated substrate in this, this insulated substrate has relative one first and one second; In this step that forms the passive component structure layer, this passive component structure layer is formed at this first of this insulated substrate; In this step that forms this second electrical contact, the part of this second electrical contact is positioned at this first perforation, this second formation of contiguous this insulated substrate of another part of this second electrical contact.
13. manufacture method as claimed in claim 11, wherein in this step that forms this first perforation, this insulated substrate has one first perforation madial wall that should first perforation, and before this step that forms this second electrical contact, this manufacture method more comprises:
Form one first Seed Layer in this first perforation madial wall;
In this step that forms this second electrical contact, this second electrical contact is formed on this first Seed Layer.
14. manufacture method as claimed in claim 13 more comprises:
Remove the part of this first Seed Layer, wherein this part of this first Seed Layer is not covered by this second electrical contact.
15. manufacture method as claimed in claim 10, wherein in this step that forms this first electrical contact, this first electrical contact is by at least one is formed in nickel dam, palladium layer and the gold layer.
16. manufacture method as claimed in claim 10 wherein comprises in this step that forms this passive component structure layer:
Form one first line layer on this insulated substrate;
Form one second dielectric layer and cover this first line layer, wherein this second dielectric layer has one second perforation, one first and one second perforation madial wall, this second perforation extends to this first line layer from this first face of this second dielectric layer, this second perforation madial wall is corresponding to this second perforation, and this first line layer exposes from this second perforation;
Form one second Seed Layer this first in this second perforation madial wall and this second dielectric layer; And
Form one second line layer on this second Seed Layer; And in this step that forms this first electrical contact, more comprise:
Via this second Seed Layer, form this first electrical contact on this second line layer.
17. manufacture method as claimed in claim 16 more comprises:
Remove the part of this second Seed Layer, wherein this part is not covered by this second line layer.
18. manufacture method as claimed in claim 16, wherein before this step that forms this second line layer, this manufacture method more comprises:
Form a patterning photoresist layer on this second Seed Layer, wherein this patterning photoresist layer definition one forms the district;
In this step that forms this second line layer, this second line layer is formed in this formation district of this patterning photoresist layer, and this second line layer also has an exposing surface;
In this step that forms this first electrical contact, more comprise:
Form this first electrical contact in this formation district, to cover whole this exposing surface of this second line layer.
19. manufacture method as claimed in claim 16, wherein in this step that forms this second line layer, this second line layer has an exposing surface; In this step that forms this first electrical contact, more comprise:
Form the part that this first electrical contact covers this exposing surface of this second line layer.
20. manufacture method as claimed in claim 10 more comprises:
Form a circulus, wherein this circulus is around the passive component of this passive component structure layer.
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Application publication date: 20110831 |