CN102164002B - Lock detection method for bit synchronization of all-digital receiver - Google Patents
Lock detection method for bit synchronization of all-digital receiver Download PDFInfo
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- CN102164002B CN102164002B CN 201110095059 CN201110095059A CN102164002B CN 102164002 B CN102164002 B CN 102164002B CN 201110095059 CN201110095059 CN 201110095059 CN 201110095059 A CN201110095059 A CN 201110095059A CN 102164002 B CN102164002 B CN 102164002B
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Abstract
The invention discloses a lock detection method for the bit synchronization of an all-digital receiver, which is characterized in that a bit synchronization loop of the all-digital receiver comprises an error detection module and a lock judgment module, wherein the error detection module is implemented by using a Gardner algorithm; the baseband input data of the error detection module comprise in-phase input data (namely, I-route data) and orthogonal input data (namely, Q-route data), the front sample points of the I/Q-route data are named as integral symbol points, and the rear sample points of the I/Q-route data are named as semi-symbol points; the integral symbol points and semi-symbol points of the two-route data are respectively subjected to squaring and addition, then the obtained results are respectively subjected to subtraction and addition; the obtained addition result is divided by the obtained subtraction result so as to obtain a lock detection quantity e (n); the lock detection quantity e (n) is weighted so as to obtain an e'(n); the e'(n) is subjected to accumulation, the obtained accumulated values are averaged so as to obtain a mean value E (k); the E (k) is compared with a lock threshold; if the E (k) is greater than the threshold, the bit synchronization loop is judged to be in a locked state; and if the E (k) is less than the threshold, the bit synchronization loop is judged to be in an unlocked state. The method disclosed by the invention can be performed without being affected by signal amplitude fading, timing phase deviation and carrier frequency offset, meanwhile, by using the method, the SNR (signal to noise ratio) is easy to estimate, and the requirements for automatic gain control are reduced.
Description
Technical field
The invention belongs to digital communication technology field, relate to the all-digital receiver in the communication system, be a kind of bit synchronization lock detecting method of QPSK all-digital receiver.
Background technology
Two synchronous ring are arranged at work---carrier synchronization ring and bit synchronization ring in the all-digital receiver.The realization of bit synchronization ring is extracted by interpolation, error-detecting, and the position is upgraded and lock-in detection consists of.Error-detecting module normal operation Gardner algorithm, each symbol needs two sampled points, tries to achieve timing offset with three continuous sampled points.
Lock detecting method has many kinds, but in real system, realize and still have various limitation when using, such as document [1] " Lock Detectors for Timing Recovery " (GKaram, V.Paxal, andM.Moeneclaey.Lock Detectors for Timing Recovery[J] Proc.ICC.pp:1281-1285, June1996.) in, Detector A realizes comparatively complicated, each symbol needs 4 sampled points, the sample frequency of receiver must be very high, cause operand large, the realization cost is high, although each symbol of Detector B is only required 2 sampled points, but it is larger that lock-in detection output is affected by input signal amplitude, the automatic gain of receiver controlled (AGC) proposed very high request.Document [2] " A Self-Normalizing Symbol Synchronization Lock Detector for QPSK and BPSK " (Yair Linn.A Self-Normalizing Symbol Synchronization Lock Detector for QPSK andBPSK[J] .IEEE Transactions on Wireless Communications, Vol.5, No.2, pp:347～353.February2006) shortcoming for Detector B proposes to improve, make it not affected by input signal amplitude, but brought another problem---it is larger affected by carrier wave frequency deviation, this algorithm is only applicable to synchronous situation of carrier wave, but the genlocing of practical application meta is often prior to the carrier synchronization locking, so there is certain limitation in actual applications in traditional lock-in detection algorithm.
Summary of the invention
The problem to be solved in the present invention is: in the existing all-digital receiver, the error-detecting of bit synchronization ring and lock-in detection are affected by signal amplitude fading, timing phase deviation and carrier wave frequency deviation, have in actual applications limitation.
Technical scheme of the present invention is: a kind of bit synchronization lock detecting method of all-digital receiver, the bit synchronization ring comprises error-detecting and locking judgement, adopt the Gardner algorithm to carry out the bit synchronization error-detecting, it is the I circuit-switched data that the base band input data of error-detecting are divided into homophase input data, inputting data with quadrature is the Q circuit-switched data, and the front sampling point of I/Q two paths of data is called the integral symbol point, is designated as respectively I (n), Q (n), n=1,2,3, + ∞, rear sampling point are half symbolic point, are designated as respectively I (n-1/2), Q (n-1/2), press the respectively computing of following formula to the integral symbol point of I/Q two paths of data and half symbolic point:
p(n)＝I
2(n)+Q
2(n)，p(n-1/2)＝I
2(n-1/2)+Q
2(n-1/2)
The data obtained p (n) and p (n-1/2) are subtracted each other respectively and addition, subtract each other the result and be lock-in detection amount e (n) divided by addition result; Weighting obtains e ' (n) to lock-in detection amount e (n), (n) cumulative and ask its mean value E (k) to e ', E (k) is compared with the lock-in threshold of setting, and it is locked to be judged to be the bit synchronization ring greater than threshold value, is judged to be bit synchronization ring non-locking less than threshold value.
Preferably lock-in detection amount e (n) is added temporary, obtain after the weighting detection limit e ' (n).
Further, described lock-in detection amount e ' (n) adds up by accumulator and averager and is averaging, and comes then the accumulator zero clearing at the zero clearing rising edge clock of accumulator, the simultaneously accumulation result of accumulator input averager is done on average, obtains E (k).
The zero clearing clock of preferred accumulator is produced by the M counter of a mould M=512, and the rising edge counting of the data clock of synchronous ring in place once.
In the such scheme, preferably getting the lock door limit value is 2
13
The present invention is by lock indicator output lock-in detection result, and the bit synchronization ring lock is fixed, lock indicator output 1, non-locking, lock indicator output 0.
All-digital receiver of the present invention is QPSK all-digital receiver, BPSK all-digital receiver or QAM all-digital receiver.
The present invention is directed to the characteristics of error detecting algorithm in the existing all-digital receiver, a kind of new lock-in detection algorithm has been proposed, this algorithm uses two sampling points in the Gardner algorithm, do not change whole bit synchronization structure of rings, and inherited the advantage of prior art, and improved for its deficiency.The key point of lock detecting method of the present invention is in the extraction to lock-in detection amount e (n) that namely in the processing to integral symbol point and half symbolic point, this method makes the lock-in detection performance not be subjected to the impact of signal amplitude fading owing to adopted normalized; The quadratic sum of inphase quadrature branch road has been eliminated carrier wave frequency deviation and timing phase deviation simultaneously, makes the lock-in detection performance not be subjected to carrier wave frequency deviation and timing phase deviation effects, and it is fixed prior in the fixed system of carrier wave ring lock to be applicable to the bit synchronization ring lock.
Description of drawings
Fig. 1 is the realization block diagram of the embodiment of the invention.
Fig. 2 is the specific implementation schematic diagram of the embodiment of the invention.
Fig. 3 is the lock-in detection curve of output of Detector B in lock-in detection curve of output of the present invention, the document " Lock Detectors for Timing Recovery " and the comparison of Gardner algorithm Timing Error Detection curve of output, abscissa is normalized timing error, and ordinate is the average detected output valve of each detector.
Embodiment
The present invention is a kind of bit synchronization lock detecting method of all-digital receiver, and such as Fig. 1, the data after the demodulation are directly sent into the bit synchronization ring and carried out sign synchronization, and what will obtain at last is exactly to sign synchronization whether indication.The bit synchronization ring adopts the Gardner algorithm to carry out the bit synchronization error-detecting, then the amount of sign is extracted, it is the I circuit-switched data that the base band of error-detecting input data are divided into homophase input data, inputting data with quadrature is the Q circuit-switched data, the front sampling point of I/Q two paths of data is called the integral symbol point, be designated as respectively I (n), Q (n), n=1,2,3 ... ,+∞, rear sampling point is half symbolic point, be designated as respectively I (n-1/2), Q (n-1/2), press the respectively computing of following formula to the integral symbol point of I/Q two paths of data and half symbolic point:
p(n)＝I
2(n)+Q
2(n)，p(n-1/2)＝I
2(n-1/2)+Q
2(n-1/2)
The data obtained p (n) and p (n-1/2) are subtracted each other respectively and addition, subtract each other the result and be lock-in detection amount e (n) divided by addition result, this can regard a kind of normalized processing as; Lock-in detection amount e (n) is added a suitable weight so that the result is comparatively obvious, and preferred weighted value is 2
16Obtain e ' (n), then (n) cumulative and ask its mean value E (k) to detection limit e ', the zero clearing clock of accumulator is obtained by a M counter, and the figure place of counter is more, and the E that obtains (k) is more accurate, but detection sensitivity step-down, take into account accuracy and the sensitivity of detection, getting counter is mould M=512 counter, and the rising edge counting of the data clock of synchronous ring in place once.The bit signal to noise ratio of general communication system can not be lower than 3dB, guaranteeing proper communication, the bit signal to noise ratio is during greater than 3dB, according to simulation result, observe the value of E (k) when locking and non-locking, take into account the bit synchronization lock-in detection of each bit signal to noise ratio, threshold value is got 213, E (k) and thresholding are compared, if it is locked that E (k) then is considered as the bit synchronization ring greater than threshold value, lock indicator output 1, otherwise be non-locking, lock indicator output 0.Weighted value 2
16The time can be so that the lock-in threshold during low symbol signal to noise ratio improves, so just can be with 2
13As the lock-in detection threshold value under the various input bit signal to noise ratios (greater than 3dB).
This method is not only applicable to the QPSK all-digital receiver, can also be used for BPSK, in the all-digital receivers such as QAM.Below introduce embodiment, take the QPSK all-digital receiver as example, validity of the present invention and practicality are described.
Specific implementation block diagram is as shown in Figure 2 sent into respectively adder and multiplier to the integral symbol point of in-phase branch and quadrature branch two paths of data and half symbolic point, calculates the quadratic sum of input value, obtains the quadratic sum p (n) of integral symbol point=I
2(n)+Q
2(n) and the quadratic sum p of half symbolic point (n-1/2)=I
2(n-1/2)+Q
2(n-1/2).Amount of calculation is larger during actual the realization, and computation delay is larger during high-frequency clock, so the available special quadratic sum device of asking can call IP kernel when realizing with FPGA and directly calculate increase result's accuracy.
Obtain e (n) by adder, subtracter and divider: the difference with the quadratic sum p (n-1/2) of the quadratic sum p (n) of integral symbol point, half symbolic point obtains lock-in detection amount e (n) divided by both sums, namely
This of lock-in detection amount e (n) followed the example of owing to adopted normalized, makes the lock-in detection performance not be subjected to the impact of signal amplitude fading; The quadratic sum of inphase quadrature branch road has been eliminated carrier wave frequency deviation and timing phase deviation simultaneously, makes the lock-in detection performance not be subjected to carrier wave frequency deviation and timing phase deviation effects.
To lock-in detection amount e (n) weighting, weighted value gets 216, so that it is better to detect performance, obtain e ' (n), detection limit e ' (n) is sent into accumulator and averager to add up respectively and is averaging, the zero clearing clock of accumulator is obtained by the M counter of a mould M=512, and the rising edge counting of the data clock of synchronous ring in place once.
Rising edge at the zero clearing clock comes then, the accumulator zero clearing, and the value that averager is sent accumulator does on average, obtains E (k).The bit signal to noise ratio is greater than 3dB, under the different bit signal to noise ratios, observes the value of E (k) when locking and the non-locking by emulation, takes into account at last the situation of various bit signal to noise ratios, and getting threshold value is 2
13
E (k) and thresholding are compared, and lock indicator judges according to the output valve of threshold compataror, output locking signal or non-locking signal, if it is locked that E (k) then is considered as the bit synchronization ring greater than threshold value, lock indicator output 1, otherwise be non-locking, lock indicator output 0.
The timing of bit synchronization ring lock, the mean value of Gardner Timing Error Detection output is zero, and this moment, lock-in detection output should maximum.As seen from Figure 3, the lock-in detection curve of output of Detector B is very close in lock-in detection curve of output of the present invention and the document [2] " Lock Detectors forTiming Recovery ", and when the mean value of Gardner Timing Error Detection output is zero, reach maximum, so Fig. 3 also can illustrate validity of the present invention.
Specific implementation of the present invention is comparatively simple, its key is in the extraction of lock-in detection amount, has than conventional method not to be subjected to the signal amplitude fading, the advantage of the impact of timing phase deviation and carrier wave frequency deviation, and can detect comparatively accurately bit synchronous locking, have very strong practicality.
Claims (9)
1. the bit synchronization lock detecting method of an all-digital receiver, the bit synchronization ring comprises error-detecting and lock-in detection, it is characterized in that adopting the Gardner algorithm to carry out the bit synchronization error-detecting, it is the I circuit-switched data that the base band input data of error-detecting are divided into homophase input data, inputting data with quadrature is the Q circuit-switched data, and the front sampling point of I/Q two paths of data is called the integral symbol point, is designated as respectively I (n), Q (n), n=1,2,3, + ∞, rear sampling point are half symbolic point, are designated as respectively I (n-1/2), Q (n-1/2), press the respectively computing of following formula to the integral symbol point of I/Q two paths of data and half symbolic point:
The data obtained p (n) and p (n-1/2) are subtracted each other respectively and addition, subtract each other the result and be lock-in detection amount e (n) divided by addition result; Weighting obtains e'(n to lock-in detection amount e (n)), to e'(n) cumulative and ask its mean value E (k), E (k) is compared with the lock-in threshold of setting, and it is locked to be judged to be the bit synchronization ring greater than threshold value, is judged to be bit synchronization ring non-locking less than threshold value.
2. the bit synchronization lock detecting method of a kind of all-digital receiver according to claim 1 is characterized in that lock-in detection amount e (n) is added temporary, and weighted value gets 2
16, obtain the detection limit e'(n after the weighting).
3. the bit synchronization lock detecting method of a kind of all-digital receiver according to claim 2, it is characterized in that described lock-in detection amount e'(n) add up and be averaging by accumulator and averager, zero clearing rising edge clock at accumulator comes then, the accumulator zero clearing, the simultaneously accumulation result of accumulator input averager is done on average, obtains E (k).
4. the bit synchronization lock detecting method of a kind of all-digital receiver according to claim 3 is characterized in that the zero clearing clock of accumulator by the M counter generation of a mould M=512, and the rising edge counting of the data clock of synchronous ring in place once.
5. according to claim 2 or the bit synchronization lock detecting method of 3 or 4 described a kind of all-digital receivers, it is characterized in that the lock door limit value is 2
13
6. the bit synchronization lock detecting method of a kind of all-digital receiver according to claim 1 is characterized in that the bit synchronization ring lock is fixed by lock indicator output lock-in detection result, lock indicator output 1, non-locking, lock indicator output 0.
7. the bit synchronization lock detecting method of each described all-digital receiver is characterized in that all-digital receiver is QPSK all-digital receiver, BPSK all-digital receiver or QAM all-digital receiver according to claim 1-4.
8. the bit synchronization lock detecting method of all-digital receiver according to claim 5 is characterized in that all-digital receiver is QPSK all-digital receiver, BPSK all-digital receiver or QAM all-digital receiver.
9. the bit synchronization lock detecting method of all-digital receiver according to claim 6 is characterized in that all-digital receiver is QPSK all-digital receiver, BPSK all-digital receiver or QAM all-digital receiver.
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| CN102447517B (en) * | 2011-10-12 | 2014-09-17 | 中国电子科技集团公司第十研究所 | Lock detection method suitable for various modulation modes |
| CN103457680B (en) * | 2013-08-20 | 2016-05-11 | 重庆邮电大学 | Timing Synchronization error detection method based on digital reception in satellite communication |
| CN108055224B (en) * | 2017-12-07 | 2020-07-21 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Synchronous locking detection method for 16QAM carrier synchronization loop |
| CN108989260B (en) * | 2018-08-01 | 2020-08-04 | 清华大学 | Improved all-digital timing synchronization method and device based on Gardner |
| CN110401609B (en) * | 2018-11-07 | 2020-06-09 | 西安电子科技大学 | Gardner symbol timing recovery method and device for accelerating convergence |
| CN110098881B (en) * | 2019-05-07 | 2020-12-11 | 中国人民解放军32039部队 | Wide-narrow beam signal transmission method and device and electronic equipment |
| CN112180409B (en) * | 2020-09-28 | 2024-02-02 | 和芯星通科技(北京)有限公司 | Bit synchronization method in GNSS, storage medium and electronic device |
| CN113765649B (en) * | 2021-09-30 | 2024-07-26 | 陕西长岭电子科技有限责任公司 | Bit synchronization method of digital communication data transmission system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1209229A (en) * | 1996-12-24 | 1999-02-24 | 三星电子株式会社 | Device for synchronising digital receiver |
| CN1614961A (en) * | 2004-09-03 | 2005-05-11 | 杭州国芯科技有限公司 | Timing recovering method |
| CN1614963A (en) * | 2004-09-03 | 2005-05-11 | 杭州国芯科技有限公司 | Timing locking test method for QAM and PSK signal |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1209229A (en) * | 1996-12-24 | 1999-02-24 | 三星电子株式会社 | Device for synchronising digital receiver |
| CN1614961A (en) * | 2004-09-03 | 2005-05-11 | 杭州国芯科技有限公司 | Timing recovering method |
| CN1614963A (en) * | 2004-09-03 | 2005-05-11 | 杭州国芯科技有限公司 | Timing locking test method for QAM and PSK signal |
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