CN1021604C - Apparatus and method for recovering from missing page faults in vector data processing operation - Google Patents

Abstract

In a data processing system employing virtual memory techniques and capable of performing a plurality of overlapping scalar and vector data processing operations, apparatus and method are provided to allow continuation of program execution after one or more vector load/store instructions, which refer to data values that are not currently in memory, receive page faults. At the occurrence of such a page fault, all instructions currently in execution are allowed to be completed, whereupon information summarizing the page fault condition is recorded in memory for use by the operating system software and a vector exception is generated. Operating system software responds to this exception, examines the fault information, causes the missing pages to be read into the main memory unit from the mass storage media, re-executes the exception producing vector instruction(s) and continues with the program execution.

Description

Apparatus and method for recovering from missing page faults in vector data processing operation

The present invention is the relevant data disposal system generally speaking, specifically, and the relevant data handling system that can under virtual memory environment, realize vector operation.

In order to improve the performance of some type repetitive operation, developed the vector data processing operation technology at present.For example, the respective element of two data arrays is carried out addition availability vector sum operation, again leaving in one the 3rd array the result with number.This process can compare with the scalar instruction of carrying out identical calculations, and the latter will require repeatedly to carry out a loop routine.Vector Processing has to be stipulated mass data is dealt with and need not to send many instructions or carries out the advantages that loop iteration is controlled in once-through operation.In addition, because every group of operand applied identical computing, can use pipelining to improve performance effectively.In general, that uses at present has two kinds of Vector Processing models, based on the model of register with based on the model of memory.

In the model based on register, each is organized operand and transmits (packing into) from main memory, and deposits in the special register that is called vector registor.Each vector registor can be stored a plurality of operands, and each operand has a predetermined length.When the portion's storage within it of one or more vector registors has required operand, the all operations number that then is stored in the vector registor is handled by a common arithmetical operation, handles the resulting operand of computing thus and is stored in the object vector register again.Because all operations to vector registor counts up to into identical computing, manage a plurality of operands so only need to send an instruction to the processing execution device.After groups of operands being finished all required computings, operand is sent back in (or being stored in) main memory unit.

In the model based on memory, operand directly is sent to performance element from the main memory unit, and the resulting operand of computing is also directly sent back to the main memory unit.In theory, owing to do not need information storage in vector registor before the beginning computing, finishing does not need to send back to memory after the computing yet, and this model based on memory provides imitates high performance.But when vector operation began, first operand arrives from memory needed the regular hour, therefore, when can share during a very long vector operation this start-up time, the most effective based on the vector model of memory.

In general, have very short start-up time, therefore short vector is had preferable performance based on the vector model of register.Operand is loaded into along with the vector operation of reality and stores, therefore, the advantage of short start-up time is combined with maximum memory utilization factor, thereby obtains the speed with the vector operation of the identical maximum that just can obtain when the vector operation of growing in based on the vector model of memory.

In the modern data processing system, very generally use virtual memory, this has become a requirement to the data disposal system, in the virtual memory data handling system, a large amount of is stored in the high capacity memory cell (or being called the reinforcement memory) for the required logical signal group of processor.When data handling system needs the instruction and data element, data handling system can think that needed instruction or data element are stored in the main memory unit, therefore, data handling system will attempt required instruction or data element are sent to that data processing unit that requires instruction or data element from the main memory unit.Confirm in the main memory unit, do not have required instruction or data element when data handling system, then produce a page fault.The page is for being stored in the magnanimity memory by data handling system information of managing unit.Page fault makes data handling system equipment be stored as the page fault information necessary that responds, and transfers control to operating system then, so that page fault is responded.

In order to respond to producing page fault, data handling system is transferred to control the corresponding module of operating system, it will determine the required instruction or the position of data element, again one " page or leaf " instruction or the data element that comprise desired instruction and/or data element will be sent to the main memory unit.In addition, operating system module will be set up the table that the main memory address and the position of instruction required in the magnanimity memory or data element are linked mutually.

In scalar (scalar) working method, the memory access instruction is that order is carried out successively, can only visit individual data.When one of visit in memory during non-existent data, necessary information is just stored, and produces a page fault exception information.Operating system is taken over control, and the desired page is read in memory, and then the recovery routine counter makes continuation execution command sequence and rerun routine.

In contrast, vector is packed into or is stored computing and can read or write the data element operand that is stored in an entire quantity in the vector registor.Pack into when carrying out a vector/when storing computing, it is favourable continuing to send further vector and/or scalar instruction.Like this, the computing of packing into scalar/store is different, after vector instruction, but before the generation of skipping leaf, can send several instructions that add.When required data element was not present in the main memory unit, several information must be stored, with box lunch skip leaf be sent to the main memory unit after, can restart or finish the execution of this instruction.

When the execute vector computing, the performance of data handling system is subjected to memory speed, can carry out simultaneously what vectors pack into and store computing and when finishing vector operation what functions or performance element can work concurrently limit.Clearly, realize the repeatedly degree of overlapping according to the scalar sum vector operation, the efficient of data handling system can further improve.

But, increased the degree of difficulty of recovering from the page fault (promptly when required data do not exist) that forms owing to vector instruction the main memory unit in the overlapping scalar sum vector instruction of execution under the virtual memory environment.In fact, finish between the order period of current execution, it is identified to have a more than vector operation to have a page fault, and this further makes resetting of Vector Processing computing complicated.For the scalar computing (only visiting individual data) of packing into/store, can detect a memory management problem immediately, therefore do not send further instruction.Concerning a vector instruction,, before detecting the memory management problem, still continue to send instruction for making best performanceization.The instruction that this reeve comes may change the state of information of the operand that once was original vector instruction, thereby the recovery of the retrieval of skipping leaf, programmable counter and re-execute instruction correct response to page fault may no longer be provided.Therefore, need a kind of technology, it can recover from page fault or other vectorial abnormality in an employing repeatedly overlaps the data handling system of vector operation based on the execution of the vector model of register.

The purpose of this invention is to provide a kind of improvement properties data disposal system.

Characteristics of the present invention provide a kind of data processing equipment that can improve vector data processing operation.

Another characteristics of the present invention are to be recovered from page fault by the CPU (central processing unit) that can carry out a plurality of overlapping instructions.

Another characteristics of the present invention provide a kind of technology, and it is recovered from page fault by the data handling system that can carry out a plurality of overlapping vector sum scalar operations instructions.

Last characteristic of the present invention provide a kind of like this technology, and it can recover from the page fault that vector operation causes in a data handling system with virtual memory ability.

According to the present invention, above-mentioned and its its feature are by in the data handling system that has vector operation ability and a virtual memory environment at, provide a kind of to since equipment that the vectorial abnormal signal (as the page fault signal) that vector operation instruction causes responds realize.A plurality of (vector) computing of master register unit at any time all can conduct interviews.When producing a vectorial abnormal signal, the instruction sending unit of CPU (central processing unit) stops to send instruction, and the current instruction of carrying out then is allowed to continue to finish.When all instructions are finished, sign is stored on the kernel stack by the information of the virtual memory problem that each vector instruction ran into, they comprise the Exception Type sign indicating number that identifies fault, vector length, initial base address, initial span (stride), cause the virtual address of the instruction that the current state of virtual address, vector instruction itself, processor of virtual memory problem and the next one are to be sent.(address of next instruction not necessarily is used for the sequential instructions after the vector instruction).This information is enough to determine the problem of virtual memory.For a page fault, skipping leaf is transferred into main memory, causes that the instruction of page fault is re-executed, and program continues to carry out an instruction (next instruction not necessarily produces the instruction after the vector instruction of page fault).

After the explanation and accompanying drawing below reading, just can better be understood these and other characteristic of the present invention.

Figure 1A and 1B are for using the example of data handling system embodiment of the present invention.

Fig. 2 is the example that possible use the data processing unit of data handling system of the present invention.

Fig. 3 illustrates the use of virtual memory in data handling system.

Fig. 4 resets the example of frame for the vector that recovers usefulness from a page fault according to the present invention.

Fig. 5 is the process flow diagram of an explanation job of the present invention.

1. the detailed description of accompanying drawing

Being two and typically can using data handling system embodiment of the present invention shown in Figure 1A and Figure 1B.In Figure 1A, CPU (central processing unit) (#1) 11 is connected to system bus 19.Other CPU (central processing unit) (as #N) 12 also can be connected to this system.CPU (central processing unit) 11(to 12) according to the structure and the central processing unit controls program processing data of CPU (central processing unit), control program is by the packing of orders that resides in the main memory unit 15.Non-resident data and instruction usually are stored in one or more magnanimity memory units, come and go by system bus 19 and 15 of main memory unit and transmit data.I/O unit (#1) 16(is to (#M) 17) be connected to data handling system by 19 of system buss such as magnanimity memory unit, subscriber terminal equipment and communication facilities.The magnanimity memory unit is stored as required data of data processing unit and instruction.Data and/or instruction group (general page representation with data and/or instruction) are the work institute requirement of CPU (central processing unit) 11 to 12, and they are to transmit to the main memory unit of CPU (central processing unit) energy quick access from the relatively low magnanimity memory unit of access speed.An advantage of bus-oriented system is to be convenient to reconfigure system, but its shortcoming is each system's ingredient all need opertaing device with provide and system bus between interface.In the data handling system shown in Figure 1B, CPU (central processing unit) 11(to 12) and I/O unit 16(to 17) be connected to main memory unit 15 by a memory control module 14, the control function that memory control module 14 has replaced system bus 19 in the configuration of the bus-oriented data handling system shown in Figure 1A and each building block of data handling system to be finished.Memory control module 14 provides centralized control and the monitoring for data and instruction transmission, and it is more effective than the bus-oriented configuration of Figure 1A, but has lost dirigibility.

Referring to Fig. 2, it illustrates a kind of principle calcspar that can use typical CPU (central processing unit) of the present invention effectively.Instruction sending unit 22 is responsible for performance element (comprising that scalar operation address-generation unit 24, at least one performance element (#1) 25(are to performance element (#Q) 26) and the vector operation unit 28 to various special uses) instruction of (decoding) is provided, vector operation unit 28 comprises vector operation processing unit 28A, vector operation address-generation unit 28B and vector operation register 28C.Generally take out by the performance element data processed from scalar register 23 or vector registor 28C.The result data that performance element draws is stored in scalar register 23, vector registor 28C or the data high-speed buffer storage unit 27.Data high-speed buffer storage unit 27 can be regarded the cache memory unit that an interface is provided as between main memory unit 15 and CPU (central processing unit) 11.(in Fig. 2, data high-speed buffer storage unit 27 is depicted as and is connected directly to the main memory unit.Shown as Figure 1A and Figure 1B, the data processing equipment in the middle of actual connection can comprise).Instruction sending unit 22 comprises: be used for definite which performance element and will handle selected data and be used to determine when that this selected performance element can be used for the equipment of data processing.The characteristic in back also comprises confirms that the target stored position will can be used for storing data processed.Command high speed buffer memory unit 21 is stored instruction, and this instruction is sent to relevant performance element through the decoding back by instruction sending unit.Instruction sending unit 22 contains the processing operational ton that makes performance element and is maximum equipment.Therefore, instruction sending unit 22 contains pre-taking-up equipment and guarantees that corresponding instruction (comprising any transfer instruction) can be the used algorithm routine of instruction sending unit 22 when needed.Various performance elements (as directed scalar operation address-generation unit 24 and vector operation unit 28) are the dedicated treatment facility that is used to carry out the particular type computing.For example, a performance element can be configured to carry out floating-point operation or integer arithmetic computing etc.Scalar register 23 can be stored data of using for executive routine or the record that data processing operation is provided.For example, a register is a program counter register, and it stores (virtual) address of instruction next pending in the program instruction sequence of carrying out.It is the physical location of main memory unit 15 that scalar operation address-generation unit 24 is used for virtual address translation.When each performance element instructed with different rate processing, instruction sending unit 22 also was responsible for rearranging from the next data of performance element with correct order.

Mention as top institute, vector operation unit 28 contains a vector operation processing unit 28A, vector operation address generating unit 28B and vector operation register 28C.The activity of vector operation processing unit can be controlled to performance element 25～26 distribute data and the wherein execution of instruction.According to another embodiment (not shown), the performance element that is exclusively used in execution command for vector operation unit 28 can be used for data handling system.When performance element can be used for the vector sum scalar operation, total system's control of instruction sending unit 22 was depended in control, by the resource of its distribute data processing unit.

Shown in Fig. 3 is the explanation of the virtual addressing mechanism in the preferred embodiment.Instruction 301 in instruction sending unit has a corresponding virtual address 302, and its sign instruction is to they data of operating.Instruction sending unit is delivered to scalar address-generation unit 24(or vector address generation unit 28B to virtual address 302).At address-generation unit 24(or 28B) in, the part of virtual address is used for sign (by the equipment 303 of address-generation unit) frame table entry 304 in main memory unit 15.Frame table entry 304 is sent to address-generation unit 24(or 28B), the field that equipment 305 tests are selected in frame table entry is to determine whether the access of data element is allowed.When not allowing access, then identify an access violation 306, call a corresponding operating process to determine how this access violation is responded.Confirming access to data element 312 when test 305 is when allowing, then frame table entry 304 is tested 307, to determine whether the required data element of this instruction exists in main memory unit 15, when test 307 shows that data element does not exist, produce a page fault 308, the program of an operating system is sent to main memory 15(to data element in the position 312), upgrade relevant frame table entry 304, the notification instruction transmitting element can restart the required data element of retrieval from the main memory position.Confirm that when test 307 required data element element is stored in the main memory unit, test 309 pairs of frame table entries 304 and test whether be denoted as the result with the activity of determining the desired data element of relevant instruction and break down.When determined this activity of this instruction is denoted as malfunction, fault when then reading, when writing fault or when carrying out fault (depending on the circumstances) will call an operating system program so that this malfunction is responded.Show that if test 309 the activity of the instruction relevant with relevant data element is not denoted as malfunction, then address-generation unit 24(or 28B) determine that reservoir in main memory unit 15 needs the physical address 311 of data element.Data element 312 on this address be transferred into scalar register 23, vector operation register 28C or command high speed buffer memory device 21(promptly when data element be an instruction) in a memory position 313.By this way, can be by the required data element that virtual address identified for instruction 301 usefulness that deal with.

Shown in Figure 4 is to reset frame according to a vector of the present invention.Remove outside the bit position 0～2, sets of signals 401 all is a logical zero.On 0～2 bit position, indicating has the unusual of following type: access violation, fault when reading, fault when writing, conversion are invalid, vector is aimed at and instruction suspends.The vector that instruction suspends code character and instruction transmitting element the sends instruction of packing into/store is relevant, but the unactual beginning of its operation.The length of sets of signals 402 expression vector or in vector operations the quantity of relevant data element.The initial base address of sets of signals 403 expressions.Initial span or the displacement of sets of signals 404 indications between adjacent data element.Sets of signals 405 is relevant virtual address in the page that causes unusual missing data element, and sets of signals 406 is to cause the instruction of packing into/store of unusual vector.Sets of signals 407 is a processor state.For purposes of the invention, bit position 2(VRF) this field is even more important, and it shows that the vector before keeping resets frame.408 virtual addresses of storing next instruction of sets of signals.

Figure 5 shows that the process flow diagram of the data processing unit of an execute vector computing from the page fault recovery.In the step 501, during carrying out a vector operation, identified page fault.In the step 502, instruction sending unit ends to send further instruction, and in the step 503, all instructions that allow to carry out when page fault continue to finish or form page fault (or some other abnormal movement).In the step 504, the parameter (as shown in Figure 4) of each page fault is stored, so that recover from page fault.In the step 505, fail to finish execution and cause the skipping leaf of each instruction of page fault to be transferred into the main memory unit, after missing data is admitted to the main memory unit, cause each instruction of fault to be performed (step 506).After responding to all instructions of display page fault with to all anomalous events, program recovery is normally carried out (step 507).

2. the operation of preferred embodiment

In a preferred embodiment, the enforcement that has as the CPU (central processing unit) of the performance element of the pipeline system of Fig. 2 is subjected to some restrictions; But other design proposal also can adopt the present invention.CPU (central processing unit) comprises a plurality of performance elements, and each unit is used to carry out the instruction of a type.For example, a performance element is a scalar address-generation unit 24, and the scalar instruction of packing into/store is promptly carried out in the transmission of logical signal group between its control CPU (central processing unit) and main memory unit.A performance element is used to carry out the data shifting function, and a performance element is used for the computing of floating-point added/subtracted, and performance element is used for integer and floating-point multiplication mutually, and performance element is used for integer and floating-point division operation mutually.Special-purpose performance element can be implemented in a pipeline configuration (but also not necessarily).Other characteristic of CPU (central processing unit) is as described below.The instruction that is in the instruction sequence of carrying out is sent to instruction sending unit 22 from command high speed buffer memory unit 21.In instruction sending unit, instruction is broken down into its each ingredient, produces control signal and the address signal relevant with data thus.But, before an instruction can begin to carry out (before promptly being issued), must satisfy several restrictive conditions.All source-registers and the destination register of instruction must be available, and promptly neither one write operation that required register is carried out can be uncompleted, and register is write the path should provide use in following cycle of the amount of handling is stored in this instruction.The term of execution be used for the required performance element of processing instruction must be available to finish computing.For the vector operation unit, a vector operation keeps a performance element during vector operation, when a cache memory unit disappearance appears in the instruction of packing into/store of a memory, pack into/the busy sign of memory cell will make the instruction delay of packing into/store subsequently, till cache memory disappearance response end.When an instruction is sent, the destination register that its result uses and write the path cycle and be retained.During operand is set up, produce the irrelevant register address of all and instructions, operand will be read out and store, and produce the control signal relevant with data.Instruction operands and control signal are sent to corresponding performance element for carrying out.The result that performance element produced correspondingly is stored in register file or the data high-speed buffer storage unit 27.When an instruction was sent, result may can not draw during several machine cycles.Simultaneously, during the next machine cycle, next instruction may be decoded, and be issued when the required condition of sending satisfies.Therefore, instruction is decoded and send with normal instruction sequences, but because the different instruction time of performance element, the order that its result can be different is stored.It is complicated that the instruction that the storage of this out-of-order makes mistakes abnormality processing and retry becomes.But because this incident is less generation, thereby out-of-order is provided by the advantage that provides at execution and hardware aspect.

In Fig. 3, the virtual addressing technology is implemented widely, and this technology can make the programmer need not consider the physical location of data and order element.The address produces mechanism will provide an interface between data in program address and the data processing unit and order element, by using the data and the order element page, accelerated from the data of high capacity or magnanimity storage media and the transmission of order element, it need not to transmit single data and order element.In addition, program is usually write with such form, makes to be that required data and the order element of execution command in proper order stored more closely mutually in program or file.Therefore, page data and order element generally will comprise a plurality of relevant datas and the order element of program execution usefulness.But, page scheme has a kind of like this result (especially when execute vector instructs) to the relative severity of subregion (granularity), be that relevant data and order element group may expand page boundary and be in the main memory unit of data handling system on the non-existent page, in a preferred embodiment, address generation mechanism 34 includes and carries out address translation, and when not being present in the main memory unit 15, required information page can produce the environment division of unusual (testing a 307) usefulness, also comprise a software program, so that between high capacity memory unit and main memory unit, transmit information page as an operating system part.When the data of a page and order element are transferred into main memory unit 15, the address produces mechanism 34 and is provided at corresponding frame table entry in the main memory unit 15, at this, the current program of carrying out can identify all data that are stored in the main memory unit 15 and the page (relevant with virtual address) of order element, therefore when accessed data or instruct when not being present in the main memory unit 15, can send a page fault signal.As shown in Figure 3, data processing unit generally comprises the process relevant with the virtual addressing technology, as be used for when desired information page is not present in the main memory unit, sending signalling arrangement, and the program that page fault is responded by the retrieval information that skips leaf.

Generally provided by a program under the operating system control from the recovery of vectorial page fault, this operating system program has vector to be reset frame and can use, to identify the program part that causes page fault.Such program will guarantee that being designated the data element that skips leaf by vectorial page fault can be sent to the main memory storage unit.The execution of the instruction of being interrupted by vectorial page fault is promptly finished.After the instruction of all interruptions was re-executed, program recovery was carried out normally then.Under present this vector mode, can require 64 data elements, each element may be in the different pages.Therefore, may need 64 page table and pages that are used to instruct about each page.Therefore, operating system software must remain carry out vector instruction required may be quite a large amount of the page for use.

CPU (central processing unit) design of the present invention can provide the executed in parallel to vector instruction and scalar instruction.Therefore, when detecting a unusual or interruption status, instruction is sent process and is stopped, and uncompleted instruction is done.Clearly, may there be the multiple unusual and state that interrupts.In this preferred embodiment, arithmetic trap (arithmetic traps) has the highest priority, is that vector is unusual then, all other unusual (fault), is the interruption of limit priority at last.

Above-mentioned illustrative purposes is the work of this preferred embodiment of elaboration rather than limits the scope of the invention that scope of the present invention only is subjected to the restriction of claim.According to the above description, for those skilled in the art that, the many schemes that comprise thinking of the present invention and scope are conspicuous.

Claims (32)

1, a kind of digital data processing equipment that is connected to main storage unit, this main storage unit comprises a plurality of memory locations, be used to store vector operand and vector instruction, each described memory location is identified by a physical address, one type described vector instruction is the computations that is used to start calculating operation, the described vector instruction of another kind of type is the transfer vector instruction that is used to start jump operation and sign virtual address, it is characterized in that described digital data processing equipment comprises:

A. vector registor is used to store vector operand;

B. vectorial performance element is used for the execute vector operation, and described vector operations is identified by the vector instruction of the compute type relevant with the vector operand in the described vector registor;

C. vector address generation unit, the instruction of the transfer vector instruction type that its response receives, so that executive address map function, thereby: (1) is according to corresponding to the physical address in the described main storage unit, the virtual address that is identified by transfer vector instruction, produce physical address, to allow vector operand between memory location that identifies by described physical address and described vector registor, to shift, (2) if not corresponding, then produce the page fault indication with physical address in the described main storage unit by the described virtual address of described transfer vector command identification; With

D. instruction sending unit, be used for retrieving vector instruction and execution command transmit operation repeatedly from described main storage unit, so that the instruction of described computations type is transferred to described vectorial performance element and described vector address generation unit is transferred in the instruction of described transfer vector instruction type, thereby allow this vector address generation unit executive address map function, described instruction sending unit is in response to indicating from the page fault of described vector address generation unit and stopping the execution command transmit operation and produce restart information, so that discern the vector instruction that causes the page fault indication.

2, digital data processing equipment as claimed in claim 1, it is characterized in that, described primary memory comprises the frame table entry corresponding to described virtual address, and described vector address generation unit comprises and is used for retrieving the device of described frame table entry and is used to test described frame table entry so that the described virtual address of determining to be identified by the described transfer instruction physical address of corresponding described main storage unit whether.

3, digital data processing equipment as claimed in claim 2, it is characterized in that, described frame table entry comprises access right information, described vector address generation unit comprises a kind of device, this device is used to test described access right information so that the virtual address that determines whether to allow access to be identified by described frame table entry, and is used for starting under the situation that above-mentioned access is not allowed to a predetermined operation.

4, digital data processing equipment as claimed in claim 2, it is characterized in that, described frame table entry comprises operation power information, described vector address generation unit comprises a kind of device, whether this device is used to test described operation power information can carry out so that determine a predetermined operation, carry out this operation and be associated with the information that the virtual address identified that is identified by described frame table entry, this device also is used for starting a predetermined operation under the situation that can not carry out aforesaid operations.

5, digital data processing equipment as claimed in claim 1 is characterized in that comprising:

Program module is used for allowing the physical address of foundation corresponding to the virtual address at described main storage unit, and this virtual address produces described page fault indication; With

Fault instruction processing unit module is used for allow using described restart information so that handle vector instruction, and this vector instruction has caused utilizing the page fault indication of the physical address of foundation.

6, digital data processing equipment as claimed in claim 5, it is characterized in that, described instruction sending unit is set up described restart information according to a form that restarts frame on core stack, described fault instruction processing unit module allows to handle described restart information frame on described core stack.

7, digital data processing equipment as claimed in claim 6, it is characterized in that, described instruction sending unit is set up a designator in described restart information frame, in order to indicate whether to have set up the previous information frame that restarts on described core stack, described fault command process module is utilized this designator so that allow to handle described previous restart information frame.

8, digital data processing equipment as claimed in claim 1, it is characterized in that, described main storage unit is stored scalar operands and scalar instruction in described memory location, wherein one type described scalar instruction is the computations that is used to start calculating operation, the described scalar instruction of another kind of type is the transfer scalar instruction that is used to start jump operation and sign second virtual address, and described digital data processing unit also comprises:

A. scalar register is used to store scalar operands;

B. the scalar performance element is used to carry out the scalar operation that is identified by the compute type scalar instruction, and it is relevant with the scalar operands in the described scalar register to carry out this scalar operation;

C. the scalar address-generation unit responds the instruction of the transfer scalar instruction type that receives, thereby carries out the scalar map function, so that:

(1) thus according to primary memory in physical address corresponding, be transferred second virtual address that scalar instruction identifies and produce second physical address, so that allow scalar operands between by the memory location of described second physical address and described scalar register sign, to shift; With

(2) if not corresponding with physical address in the described main storage unit, then produce second page fault and indicate by described second virtual address of described transfer scalar instruction sign;

D. described instruction sending unit is retrieved scalar instruction repeatedly from described main storage unit, and carry out the scalar instruction transmit operation, so that the scalar instruction of described computations type is transferred to described scalar performance element and the instruction of described transfer scalar instruction type is transferred to described scalar address-generation unit, thereby allow its to carry out scalar map function; Described instruction sending unit is in response to second page fault indication from described scalar address-generation unit, thereby decision execution command transmit operation and generation scalar restart information are so that identify scalar instruction, and this scalar instruction has caused second page fault indication from described scalar address-generation unit.

9, digital data processing equipment as claimed in claim 8 is characterized in that, described primary memory comprises the frame table entry corresponding to described second virtual address, and described scalar address-generation unit comprises:

A kind of device is used to retrieve described frame table entry; With

A kind of device is used to test described frame table entry, so that whether described second virtual address of determining to be identified by described transfer scalar instruction is corresponding to the physical address in the described main storage unit.

10, digital data processing equipment as claimed in claim 9, it is characterized in that, described frame table entry comprises access right information, described scalar address-generation unit comprises a kind of device, this device is used to test described access right information so that determine whether second virtual address that access is identified by described frame table entry, and this device also is used for starting a predetermined operation under the situation that above-mentioned access is not allowed to.

11, digital data processing equipment as claimed in claim 9, it is characterized in that, described frame table entry comprises operation power information, described scalar address-generation unit comprises a kind of device, this device is used to test described operation power information, can carry out predetermined operation so that determine whether, the execution of operation that should be predetermined is associated with the information that second virtual address that is identified by described frame table entry is identified, and this device also is used for starting a predetermined operation under the situation that above-mentioned predetermined operation can not be carried out.

12, digital data processing equipment as claimed in claim 8 is characterized in that comprising:

Program module is used for allowing the physical address of foundation corresponding to the virtual address at described main storage unit, and this virtual address produces described second page fault indication; With

Fault instruction processing unit module, thereby be used for allowing to use described scalar restart information to handle scalar instruction, this scalar instruction causes the indication of second page fault to be used and the virtual address physical address corresponding, and this virtual address produces described second page fault indication.

13, digital data processing equipment as claimed in claim 12, it is characterized in that, described instruction sending unit is set up described scalar restart information with the form of restart information frame on core stack, this fault instruction processing unit module allows to handle this scalar restart information frame on described core stack.

14, digital data processing equipment as claimed in claim 13, it is characterized in that, described instruction sending unit is set up a designator in described restart information frame, indicate it whether to push away in described core and set up an original restart information frame on the stack, thereby this fault instruction processing unit module uses this designator to allow to handle described original restart information frame.

15, digital data processing equipment as claimed in claim 1 is characterized in that comprising the digital data processing unit that is connected to described main storage unit.

16, digital data processing equipment as claimed in claim 15 is characterized in that, described main storage unit comprises the frame table entry corresponding to described virtual address,

Described vector address generation unit comprises: a kind of device, be used to retrieve described frame table entry, also comprise a kind of device, be used for testing described frame table entry so that determine: whether corresponding with the physical address of described main storage unit by the described virtual address of described transfer vector command identification.

17, digital data processing equipment as claimed in claim 16, it is characterized in that, described vector address generation unit comprises a kind of device, this device is used to test described access right information, so that determine: whether the access to the virtual address discerned by described frame table entry is allowed to, and this device also is used for predetermined operation of startup under the situation that above-mentioned access is not allowed to.

18, digital data processing equipment as claimed in claim 16, it is characterized in that, described frame table entry comprises operation power information, described vector address generation unit comprises: a kind of device, this device is in order to test described operation power information, thereby determine whether to carry out a predetermined operation, this operation is associated with the information that the virtual address identified that is identified by described frame table entry, and this device also is used for starting a predetermined operation under the situation that aforesaid operations can not be carried out.

19, digital data processing equipment as claimed in claim 15 is characterized in that comprising:

Program module, this module are used for allowing to set up physical address in described main storage unit, and this physical address is corresponding with the virtual address that produces described page fault indication;

Fault instruction processing unit module, thus this module is used for allowing to use described restart information to handle vector instruction, and this vector instruction has caused the page fault indication to use the physical address of having set up.

20, digital data processing equipment as claimed in claim 19, it is characterized in that, described instruction sending unit is set up described restart information according to the form of restart information frame on core stack, described exception handles module allows to handle this restart information frame on described core stack.

21, digital data processing equipment as claimed in claim 20, it is characterized in that, described instruction sending unit is set up a designator in described restart information frame, whether this designator indication it set up an original restart information frame on described core stack, thereby this fault instruction processing unit module uses this designator to allow to handle described original restart information frame.

22, digital data processing equipment as claimed in claim 15, it is characterized in that, described main storage unit is stored scalar operands and scalar instruction in described memory location, one type described scalar instruction is the computations that is used to start calculating operation, another kind of type be the transfer scalar instruction that is used to start jump operation and is used to identify second virtual address do scalar instruction, described digital data processing equipment comprises:

A. scalar register is used to store scalar instruction;

B. scalar performance element is used to carry out the scalar operation by the scalar instruction of compute type sign, and the execution of this operation is associated with scalar operands in the described scalar register;

C. the scalar address-generation unit is used for carrying out the scalar map function according to the transfer scalar instruction type instruction that receives, so that:

(1) according to being identified second virtual address by the transfer scalar instruction corresponding with physical address in the main storage unit, thereby produce second physical address, so that allow scalar operands between by the memory location of described second physical address sign and described scalar register, to shift;

(2) if not corresponding, then produce the indication of second page fault with the physical address in the described main storage unit by described second virtual address of described transfer scalar instruction sign; With

D. described instruction sending unit is retrieved the scalar instruction from described main storage unit repeatedly, and carry out the scalar instruction transmit operation, so that: the scalar instruction of described computations type is transferred to described scalar performance element, and the instruction of described transfer scalar instruction type is transferred to described scalar address-generation unit, thereby allow it to carry out the scalar map function, described instruction sending unit is according to determining the execution command transmit operation and produce the scalar restart information from second page fault indication of described scalar address-generation unit, so that identification scalar instruction, this scalar instruction cause second page fault indication from described scalar address-generation unit.

23, digital data processing equipment as claimed in claim 22 is characterized in that, described main storage unit comprises and the described second virtual address corresponding page table entry that described scalar address-generation unit comprises:

A kind of device is used to retrieve described frame table entry; With

A kind of device is used to test described frame table entry so that determine: by described second virtual address of described transfer scalar instruction sign whether corresponding to the physical address in the described main storage unit.

24, digital data processing equipment as claimed in claim 23, it is characterized in that, described frame table entry comprises access right information, described scalar address-generation unit comprises a kind of device, thereby this device is used to test described access right information to be determined: whether the access to second virtual address that identified by described frame table entry is allowed to, and this device also is used for predetermined operation of startup when above-mentioned access is not allowed to.

25, digital data processing equipment as claimed in claim 23, it is characterized in that, described frame table entry comprises operation power information, described scalar address-generation unit comprises a kind of device, this device is used to test described operation power information, so that determine: whether a predetermined operation can be carried out, and the execution of this operation is associated with the information that second virtual address that is identified by described frame table entry is identified, this device also is used for starting a predetermined operation when described operation can not be carried out.

26, digital data processing equipment as claimed in claim 22 is characterized in that comprising:

Program module is used for allowing the physical address of foundation corresponding to the virtual address at described main storage unit, and this virtual address produces described second page fault indication; With

Fault instruction processing unit module, be used for allowing to use described scalar restart information so that handle scalar instruction, this scalar instruction has caused the physical address of second page fault indication use corresponding to the virtual address, and this virtual address produces described second page fault indication.

27, digital data processing equipment as claimed in claim 26, it is characterized in that, described instruction sending unit is set up described scalar restart information according to the form of restart information frame on core stack, this fault instruction processing unit module allows to handle this scalar restart information frame on described core stack.

28, digital data processing equipment as claimed in claim 22, it is characterized in that, described instruction sending unit is set up a designator in described restart information frame, it has set up an original restart information frame this designator indication on described core stack, this fault instruction processing unit module is used this designator so that allow to handle described original restart information frame.

29, digital data processing equipment as claimed in claim 1 is characterized in that, described main storage unit comprises and described virtual address corresponding page table entry that described frame table entry comprises access right information and operation power information,

Described vector address generation unit comprises:

ⅰ. a kind of device, retrieve described frame table entry according to the transfer vector indication type instruction that receives;

ⅱ. the page fault proving installation, thereby be used for using the frame table entry that is retrieved to determine: whether corresponding with the physical address of described main storage unit by the described virtual address that described transfer vector instruction is identified, if and not corresponding between them, then this device is used to produce the page fault indication;

ⅲ. the access right proving installation, be used for testing the access right information of the frame table entry that is retrieved, so that determine: whether the access to the virtual address that identified by described frame table entry is allowed to, and this device is used for starting a predetermined operation when above-mentioned access is not allowed to;

ⅳ. operation power proving installation, be used to test the operation power information in the frame table entry that is retrieved, so that whether determine predetermined operation can carry out, the execution of this operation is associated with the information that the virtual address identified that is identified by described frame table entry, also is used for starting when described operation can not be carried out a predetermined operation; With

ⅴ. a kind of device, be used for the executive address map function, so that according to being produced physical address by virtual address corresponding to the transfer vector command identification of the physical address in the described main storage unit, thereby allow vector operand between memory location that is identified by described physical address and described vector registor, to shift, if it is corresponding with the physical address in this main storage unit that described page fault proving installation is determined this virtual address, then described access right proving installation is determined: the access to the virtual address is allowed to, and described operation power proving installation is determined: predetermined operation can be carried out; And,

Described instruction sending unit produces the restart information frame on core stack according to indicating from the page fault of described vector address generation unit, thereby sign causes the vector instruction of page fault indication, described restart information frame comprises a designator, has set up original restart information frame in order to indicate it on described core stack;

Described digital data processing equipment comprises:

E. program module is used for setting up and the corresponding physical address in virtual address that produces described page fault indication at described main storage unit;

F. fault instruction processing unit module is used for allowing handling the restart information frame on described storehouse, and this module uses designator to allow to handle described original restart information frame.

30, digital data processing equipment as claimed in claim 1, it is characterized in that, described main storage unit storage scalar operands and scalar instruction, one type described scalar instruction is second computations that is used to start second calculating operation, the described scalar instruction of another kind of type is the transfer scalar instruction that is used to start scalar jump operation and sign second virtual address, described main storage unit also comprises and each described virtual address corresponding page table entry, each described frame table entry comprises access right information and operation power information, and described digital data processing unit also comprises:

E. scalar register is used to store scalar operands;

F. scalar performance element is used to carry out the scalar operation of being discerned by the scalar operands of compute type, and the execution of this operation is associated with scalar operands in the described scalar register;

Described vector address generation unit comprises:

ⅰ. vectorial frame table entry indexing unit, this device be in response to the instruction of the transfer vector instruction type that receives, thereby retrieve described frame table entry;

ⅱ. vectorial page fault proving installation, be used to use the frame table entry that is retrieved, if not corresponding, then be used to produce the page fault indication whether corresponding to the physical address in the described main storage unit so that determine by the virtual address of the described transfer vector command identification that is retrieved;

ⅲ. device is surveyed in the test of vector access power, be used for testing the access right information of the frame table entry that is retrieved, so that determine whether the access of the virtual address discerned by the described frame table entry that is retrieved is allowed to, and when above-mentioned access is not allowed to, start a predetermined operation;

ⅳ. vector operations power proving installation, be used to test the operation power information in the frame table entry that is retrieved, so that whether determine predetermined operation can carry out, the execution of this operation is associated with the information that the virtual address identified that is identified by the described frame table entry that is retrieved, and starts a predetermined operation when described operation can not be carried out; With

ⅴ. the vector address converting means, be used for the executive address map function, so that according to being produced physical address by virtual address corresponding to the sign of the physical address in the described main storage unit, thereby allow vector operand between by described physical address that is produced and described vector registor, to shift, if described vectorial page fault proving installation is determined: it is corresponding with the physical address in the described main storage unit to be transferred the virtual address that vector instruction identifies, then described vector access power proving installation is determined: the access to the virtual address that is transferred the vector instruction sign allows, and vector operations power proving installation is determined: the operation of being scheduled to is executable; With

G. scalar address-generation unit comprises:

ⅰ. scalar frame table entry indexing unit is used to respond the transfer scalar instruction type instruction that receives, thereby retrieves the second described frame table entry;

ⅱ. scalar page fault proving installation, be used to use second frame table entry that is retrieved, thereby whether correspondingly determine by the described virtual address of described transfer scalar instruction sign with the physical address in the described main storage unit, and when not corresponding, be used to produce the page fault indication in above-mentioned address;

ⅲ. scalar access power proving installation, be used for testing the access right information of second frame table entry that is retrieved, thereby determine: to whether being allowed to, and when this access is not allowed to, start a predetermined operation by the access of the virtual address of described second frame table entry sign that is retrieved;

ⅳ. scalar operation power proving installation, be used for testing the operation power information of second frame table entry that is retrieved, thereby determine whether predetermined operation can be carried out, the execution of this operation is associated with the information that the virtual address identified that is identified by described second frame table entry that is retrieved, and is used for starting when aforesaid operations can not be carried out the second predetermined operation; With

ⅴ. the scalar address conversion device, be used to produce map function, so that according to the virtual address that is identified by the transfer scalar instruction corresponding with physical address in the described main storage unit, thereby produce second physical address, so that allow scalar operands between memory location that is identified by described second physical address that is produced and described scalar register, to shift, if described scalar page fault proving installation is determined: it is corresponding with the physical address in the described main storage unit to be transferred the virtual address that scalar instruction identifies, then described scalar access power proving installation is determined the access of the virtual address that is transferred the scalar instruction sign is allowed, and scalar operation power proving installation determines that the second predetermined operation is executable; With

H. instruction sending unit is used for retrieving repeatedly the vector sum scalar instruction from described main storage unit, and is used to the transmit operation of executing instruction, so that:

(ⅰ) vector instruction with described computations type is transferred to described vectorial performance element;

(ⅱ) vector instruction with described transfer vector instruction type is transferred to described vector address generation unit, thereby allows its executive address map function;

(ⅲ) scalar instruction of described computations type is transferred to described scalar performance element and

(ⅳ) scalar instruction with described transfer scalar instruction type is transferred to described scalar address-generation unit, thereby allow its executive address map function, described instruction sending unit is according to the page fault indication from described vector address generation unit, thereby determine the execution command transmit operation and on core stack, produce the information frame that restarts, so that sign causes the vector instruction of page fault indication, the described information frame that restarts comprises a designator, whether has set up original restart information frame in order to indicate it on described core stack;

I. program module is used to allow set up in described main storage unit and the corresponding physical address in virtual address that produces the page fault indication; With

J. fault instruction processing unit module is used for allowing handling the restart information frame on described core stack, and this fault instruction processing unit module is used this designator so that allow to handle described original restart information frame.

31, a kind of digital data processing equipment method of operating, this treatment facility is connected to the main storage unit that includes a plurality of memory locations, each storage unit is identified by a physical address, described memory location storage vector operand and vector instruction, one type described vector instruction is the computations that is used to start calculating operation, the described vector instruction of another kind of type is the transfer vector instruction that is used to start jump operation and sign virtual address, said method comprising the steps of:

A. from described main storage unit, retrieve vector instruction and execution command transmit operation repeatedly, thereby the instruction of described computations type is transferred to vectorial performance element so that handle, and when instructing, it is transferred to the vector address generation unit to the transfer vector instruction type;

B. according to the transfer vector instruction type instruction that receives, allow the map function of described vector address generation unit executive address, thereby

(1) according to by with described main storage unit in the virtual address that identified of the corresponding transfer vector of physical address instruction, thereby produce a physical address, so that allow vector operand between by memory location that described physical address identified and described vector registor, to shift

(2) if not corresponding with physical address in the described main storage unit, then produce the page fault indication by the described virtual address of described transfer vector command identification;

C. according to page fault indication, stop the execution command transmit operation, and produce restart information, thereby sign has caused the vector indication of page fault indication from described vector address generation unit;

D. set up the physical address corresponding to the virtual address in described main storage unit, this virtual address produces described page fault indication; With

Thereby E. use described restart information to handle vector instruction, this vector instruction causes the page fault indication to use the physical address of having set up.

32, method as claimed in claim 31, it is characterized in that, described restart information comprises a designator, in order to indicating this restart information originally to be produced,, above-mentioned use step use this designator to allow described equipment described original restart information is determined and to be handled thereby comprising.

Images