KR101191530B1 - Multi-core processor system having plurality of heterogeneous core and Method for controlling the same - Google Patents

Abstract

Disclosed are a multicore processor system including a plurality of heterogeneous cores, and a control method thereof. The disclosed multicore processor system includes a selector for selecting a core to execute a meta instruction, which is a higher instruction defined in the multicore processor system, from the plurality of heterogeneous cores; And a converting unit converting the meta instruction into a lower instruction executable in the selected core and transferring the meta instruction to the selected core. According to the present invention, two or more instructions can be simultaneously processed using a plurality of heterogeneous cores.

Description

Multi-core processor system having multiple of heterogeneous core and method for controlling the same}

Embodiments of the present invention relate to a multicore processor system and a control method thereof, and more particularly, to a multicore processor system and a control capable of simultaneously processing two or more instructions using a plurality of heterogeneous cores. It is about a method.

In general, the instruction systems used are different depending on the type of processor core (hereinafter referred to as "core"). Therefore, research and development on virtual machines that can be used in all processor systems without being dependent on different instruction systems have been in progress. Among them, the Java System developed by Sun Microsystems is the most widely used.

The Java system introduces the Java Programming Model and Java Virtual Machine (JVM) to provide an environment where the same Java program can run on all processor systems regardless of the type of Instruction Set Architecture (ISA). do. At this time, the Java virtual machine is implemented in software (Fig. 1 (a)) or hardware form (Fig. 1 (b)) in the processor system as shown in Fig. 1 to generate Java program code (Java instructions) respectively. Performs a function provided to the core by converting it into executable instructions in the core.

On the other hand, since a multi-core processor system including different types of cores (heterogeneous cores) has a structure in which a plurality of heterogeneous cores are used in one system, all ISA instructions for each core are executed ( Should be able to However, since the above command processing (execution) operation is a processing operation not defined in the existing Java system, the existing Java system cannot convert a Java command into an executable command in a plurality of heterogeneous cores and cannot be processed. There was this. In other words, in the heterogeneous multicore processor system, since there are a plurality of heterogeneous cores inside the processor, only the instruction conversion function of the existing Java virtual machine can perform the instruction scheduling function for each heterogeneous core and the instruction allocation function considering the characteristics of the instructions. There was a problem that can not.

In order to solve the problems of the prior art as described above, the present invention proposes a multi-core processor system and a control method capable of simultaneously processing two or more instructions using a plurality of heterogeneous cores.

Another object of the present invention is to provide a multicore processor system including a plurality of heterogeneous cores operable in the same manner as a multicore processor system including two or more cores of the same kind, and a control method thereof.

According to a preferred embodiment of the present invention to achieve the above object, in a multi-core processor system comprising a plurality of heterogeneous cores, the core to execute the meta-instructions that are higher instructions defined in the multi-core processor system A selection unit for selecting from the plurality of heterogeneous cores; Provided is a multi-core processor system including a converting unit for converting the meta-instruction into a lower instruction executable in the selected core and delivering the meta-instruction to the selected core.

The multicore processor system further includes a temporary storage unit for receiving and storing the meta-instruction from a memory, wherein the selection unit reads one or more meta-instructions from the temporary storage unit, and selects a core to execute the read one or more meta-instructions. You can choose.

The temporary storage unit may include a queue.

The selection unit is based on at least one of the state information of each of the plurality of heterogeneous cores, the meta instruction execution performance evaluation information of each of the plurality of heterogeneous cores, and the state information of a cache included in each of the plurality of heterogeneous cores. You can choose which core to run.

The state information of each of the heterogeneous cores may include any one of idle state information indicating that the core is in an idle state and busy state information indicating that the core is in a busy state.

The meta instruction execution performance evaluation information of each of the plurality of heterogeneous cores is generated by evaluating the execution performance of the meta instruction executed in advance by each of the plurality of heterogeneous cores, or with respect to the meta instruction executed by each of the plurality of heterogeneous cores. It can be generated by evaluating execution performance in real time.

The conversion unit may be connected to each of the plurality of heterogeneous cores, and may include a plurality of conversion modules for converting and transmitting the meta-instructions into lower instructions executable in the cores connected thereto.

The selecting unit selects a transformation module connected to a core to execute the meta-instruction among the plurality of transformation modules; And a delivery module for transmitting the meta-command to the selected transformation module.

The conversion unit may convert one meta command into at least one sub command or at least one meta command into one sub command.

In addition, according to another embodiment of the present invention, in a method of controlling a multicore processor system including a plurality of heterogeneous cores, the plurality of heterogeneous cores may include a core for executing a meta instruction, which is a higher instruction defined in the multicore processor system. Selecting from; And converting the meta-instruction into a lower instruction executable in the selected core and delivering the meta-instruction to the selected core.

The control method of the multicore processor system may further include receiving the meta instruction from a memory and storing the meta instruction in a queue, wherein the selecting includes reading one or more meta instructions from the queue and reading the one or more meta instructions from the queue. You can choose which core to run each.

The selecting may be performed based on at least one of state information of each of the plurality of heterogeneous cores, meta instruction execution performance evaluation information of each of the plurality of heterogeneous cores, and state information of a cache included in each of the plurality of heterogeneous cores. You can choose which core to run the meta instruction on.

The selecting may include selecting a conversion module connected to a core to execute the meta instruction from among a plurality of conversion modules respectively connected to the plurality of heterogeneous cores, and converting the meta instruction into a lower instruction executable in a core connected to the meta instruction. Making; And transmitting the meta instruction to the selected transformation module, wherein the converting may convert the meta instruction into a lower instruction of a core connected to the selected transformation module through the selected transformation module. .

According to the present invention, two or more instructions can be simultaneously processed using a plurality of heterogeneous cores.

In addition, according to the present invention, it is possible to operate a multicore processor system including a plurality of heterogeneous cores in the same manner as a multicore processor system including two or more cores of the same type.

1 is a diagram illustrating an example of a conventional processor system including a Java virtual machine.
2 is a block diagram showing a detailed configuration of a multicore processor system according to an embodiment of the present invention.
3 is a view for explaining the concept of the "SMAC" command.
4 is a flowchart illustrating an overall flow of a control method of a multicore processor system according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the embodiments. Like reference symbols in the drawings denote like elements.

2 is a block diagram showing a detailed configuration of a multicore processor system according to an embodiment of the present invention.

Referring to FIG. 2, the multicore processor system 200 according to an embodiment of the present invention includes N heterogeneous cores 210 (N is an integer of 2 or more), a temporary storage unit 220, and a selection unit. 230, and a conversion unit 240. Hereinafter, the function of each component will be described in detail with reference to FIG. 2.

The N heterogeneous cores 210 refer to processor cores having different instruction set architectures (ISAs). For example, the N heterogeneous cores 210 may include an Intel 8086 processor core, an IBM PowerPC processor core, an ARM processor core, and the like.

The temporary storage unit 220 receives (reads) and stores a meta command from the main memory 250.

The meta instruction is a newly defined instruction in a multicore processor system according to an embodiment of the present invention, and may be executed (processed) in N heterogeneous cores 210 (that is, each of the N heterogeneous cores 210). It is a high-level command (high command) of ISA). The meta instruction is converted into a command suitable for each core 210 by the conversion unit 240 as described below.

These meta-instructions cannot support dedicated instructions specific to a particular core. In addition, meta-instruction is a higher-level instruction, and since it has to use an instruction system that can be commonly expressed in all kinds of cores, it has an abstracted structure rather than the ISA of a general core. Hereinafter, an instruction that may be executed in each core 210 may be referred to as a "sub instruction" to distinguish it from a meta instruction.

Since the multi-core processor system 200 according to an embodiment of the present invention executes (processes) an instruction using a plurality of cores, only one instruction processing operation may be performed in one cycle, and N Command processing operations may be performed simultaneously. However, if the multicore processor system 200 only patches one instruction in one cycle, the overall system performance may be degraded due to a bottleneck occurring in the main memory 250. Therefore, the present invention buffers the occurrence of the above bottleneck through the temporary storage unit 220.

In this case, the temporary storage unit 220 may receive and store only one meta command from the main memory 250, or receive N meta commands corresponding to the number of heterogeneous cores 210 from the main memory 250. In addition, N or more meta commands may be received from the main memory 250 and stored.

According to an embodiment of the present invention, the temporary storage unit 220 may include a queue. In other words, the temporary storage unit 220 may be configured as a queue that operates as a first in first out (FIFO).

The selector 230 reads one or more meta-instructions from the temporary storage unit 220, and selects a core from among N heterogeneous cores 210 to execute the read one or more meta-instructions. That is, the selector 230 selects a core capable of executing (processing) the corresponding meta instruction best among the N heterogeneous cores 210. At this time, the selection information of the core and the corresponding meta command are transmitted to the conversion unit 240.

According to an embodiment of the present invention, the selector 230 may include status information of each of the N heterogeneous cores 210, meta-instruction execution performance evaluation information of each of the N heterogeneous cores 210, and N heterogeneous cores 210. The core to execute the meta-instruction may be selected based on at least one of state information of the cache included in each cache).

Here, the state information of the core may include any one of idle state information indicating that the core is in an idle state and busy state information indicating that the core is in a busy state. For example, when core 1 is in a busy state and cores 2 to N are in an idle state, the state information for core 1 includes busy state information, and the state information of cores 2 to core N includes idle state information. Include.

When a core for executing a meta instruction is selected based on the state information of the core, the selector 230 may preferentially select a core in an idle state.

In addition, the meta-instruction execution performance evaluation information of the core refers to information indicating which core among the N heterogeneous cores 210 can be executed (processed) best.

At this time, the meta-instruction execution performance evaluation information of the core is in the form of an evaluation value (for example, the execution performance evaluation value of each core for a predetermined meta instruction is [Core 1: 50%, Core 2: 70%, Core 3: 15%,..., Core N: 40%], and the priority of each core's execution performance for a given meta-instruction, for example in the form of [core 1: first]. 3 rank, core 2: first rank, core 3: fourth rank, ..., core N: second rank].

According to an embodiment of the present invention, the meta-instruction execution performance evaluation information of each of the N heterogeneous cores 210 is generated by evaluating the execution performance of the meta-instructions previously executed by each of the N heterogeneous cores 210 or N. The meta-instructions executed by each of the heterogeneous cores 210 may be generated by evaluating execution performance in real time. In other words, the core instruction execution performance evaluation of the core may be performed by evaluating a group of meta instructions that perform a specific function in advance and reflecting the result thereof, or by measuring and reflecting the execution result history of the meta instruction group in real time. It may be performed through at least one method.

When a core to execute a meta instruction is selected based on the meta instruction execution performance evaluation information of the core, the selector 230 may preferentially select a core having a high execution performance with respect to the corresponding meta instruction.

The state information of the cache included in the core refers to information indicating whether there is free storage space of information in the cache inside the core.

In this case, the free storage space may be represented by the number of bytes (for example, in the form of [Core 1: 200 Kbyte, Core 2: 100 Kbyte, Core 3: 350 Kbyte, ..., Core N: 400 Kbyte]) or in percentage form. Expression (eg, [Core 1: 20%, Core 2: 40%, Core 3: 35%, ..., Core N: 70%]).

When a core for executing a meta instruction is selected based on state information of an internal cache of the core, the selector 230 may preferentially select a core including a cache having a large amount of free storage space.

In addition, the above core selection elements may be used in combination of two or more. In this case, the selector 230 may select a core to process the instruction by combining two or more selection elements through a method of assigning priority to each of the selection elements.

The conversion unit 240 converts the corresponding meta-instruction into an instruction suitable for the ISA of the selected core based on the selection information of the core received from the selection unit 230, and transfers the converted instruction to the selected core. That is, the conversion unit 240 converts the meta instruction into a lower instruction executable in the selected core and delivers the meta instruction to the core. In one example, if the selected core is an ARM processor core, the corresponding meta-instructions are converted to the ISA of the ARM processor core.

In this case, the conversion unit 240 basically converts one meta command into one subcommand (1: 1 command conversion), but the conversion unit 240 may convert one meta command into two or more subcommands. You can also convert two or more meta-commands into one subcommand (K: 1 command conversion).

In case of 1: 1 instruction conversion in which the conversion unit 240 converts one meta instruction into one sub-command, basic instructions used in all heterogeneous cores such as "ADD" instruction, "SUB" instruction, "MUL" instruction, etc. Can be applied for

When the conversion unit 240 converts a meta instruction into two or more sub-instructions, the meta-instruction does not correspond to one instruction of the selected core (that is, when the meta-instruction cannot be expressed as one sub-instruction). May occur). This is because, as described above, meta-commands have an abstracted command structure of a higher concept.

As an example, as shown in (a) of FIG. 3, if the "SMAC" instruction, which is a multiplication and addition repetition instruction instruction mainly used in the DSP, is defined as a meta instruction and the core does not support the "SMAC" instruction, the conversion The unit 240 may convert one meta command (“SMAC” command) into two sub-commands (“MUL” command and “ADD” command) (see FIG. 3B).

In addition, when the conversion unit 240 converts two or more meta-instructions into one sub-instruction, the function evaluation result for the effect of the set of codes represented by the meta-instruction is a special instruction of the corresponding core (for example, DSP (Digital) Signal Processing command). Accordingly, two or more meta instructions are replaced with one special instruction of the corresponding core.

For example, if the aforementioned "SMAC" instruction is not defined as a meta instruction, and the heterogeneous core supports the "SMAC" instruction, the conversion unit 240 may execute two meta instructions ("MUL" instruction and "ADD" instruction). It can be converted into one subcommand (“SMAC” command) (see (c) of FIG. 3).

In summary, the conversion unit 240 may convert one meta command into at least one sub command or at least one meta command into one sub command.

According to an embodiment of the present invention, the conversion unit 240 is connected to each of the N heterogeneous cores 210, N conversion module 241 for converting the meta-instructions to the lower instruction executable in the core connected to it and transfers it. The selection unit 230 may include a selection module 231 for selecting a transformation module connected to a core to execute a meta instruction among the N transformation modules 241, and a transfer for transmitting the meta instruction to the selected transformation module. Module 232 may be included.

That is, the conversion unit 240 is composed of a dedicated conversion module for each core, the selection module 231 performs an instruction delivery scheduling function when delivering a meta-command to such a conversion module (ie, the corresponding core), 232 performs a function of distributing meta-commands to each conversion module.

As such, the multicore processor system 200 including a plurality of heterogeneous cores according to an embodiment of the present invention may operate in the same manner as a multicore processor system including two or more cores of the same type. More than one instruction can be processed at the same time.

4 is a flowchart illustrating an overall flow of a control method of a multicore processor system according to an exemplary embodiment of the present invention.

The control method of a multicore processor system according to an exemplary embodiment of the present invention is applicable to a multicore processor system including a plurality of heterogeneous cores as described above with reference to FIG. 2. Hereinafter, a process performed for each step will be described with reference to FIG. 4.

First, in step S410, a meta command is received from the main memory and stored in a queue. In this case, the number of stored meta-commands may be one or more. Also, the one or more meta instructions may be meta instructions to be executed on one heterogeneous core among a plurality of heterogeneous cores, or may be meta instructions to be executed on two or more heterogeneous cores.

In operation S420, one or more meta instructions are read from the queue, and a core to execute each of the read one or more meta instructions is selected. In this case, in operation S420, a core suitable for executing the corresponding meta instruction may be selected.

According to an embodiment of the present invention, in step S420, among the state information of each of the plurality of heterogeneous cores, the meta instruction execution performance evaluation information of each of the plurality of heterogeneous cores, and the state information of the cache included in each of the plurality of heterogeneous cores. It is possible to select a core on which to execute the meta instruction based on at least one. The meaning of each selection element is the same as the selection element described above with reference to FIG. 2.

In step S430, the meta instruction is converted into a lower instruction executable in the selected core and transferred to the selected core.

According to an embodiment of the present invention, in step S430, one meta command may be converted into one subcommand, one meta command may be converted into two or more subcommands, and two or more metacommands may be converted into one subcommand. You can also convert to a subcommand of.

On the other hand, in step (S420) is selected from the plurality of conversion modules connected to the core to execute the meta-instructions from among a plurality of conversion modules connected to each of the plurality of heterogeneous cores, converting the meta-instruction into a lower instruction executable in the core connected to it The meta instruction may be transmitted to the selected transformation module. In this case, in operation S430, the meta instruction may be converted into a lower instruction of a core connected to the selected transformation module through the selected transformation module.

Finally, in step S440, the core executes (processes) the corresponding sub-instruction.

So far, embodiments of the control method of the multicore processor system according to the present invention have been described, and the configuration of the multicore processor system 200 described above with reference to FIG. 2 is also applicable to the present embodiment. Hereinafter, a detailed description will be omitted.

In addition, embodiments of the present invention may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Examples of program instructions, such as magneto-optical and ROM, RAM, flash memory and the like, can be executed by a computer using an interpreter or the like, as well as machine code, Includes a high-level language code. The hardware device described above may be configured to operate as one or more software modules to perform the operations of one embodiment of the present invention, and vice versa.

As described above, the present invention has been described with reference to particular embodiments, such as specific elements, and limited embodiments and drawings. However, it should be understood that the present invention is not limited to the above- Various modifications and variations may be made thereto by those skilled in the art to which the present invention pertains. Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

Claims (13)

In a multicore processor system comprising a plurality of heterogeneous cores,
A selection unit for selecting a core to execute a meta instruction, which is an upper instruction defined in the multicore processor system, from the plurality of heterogeneous cores;
A converting unit converting the meta instruction into a lower instruction executable in the selected core and transferring the meta instruction to the selected core,
The selection unit is based on at least one of the state information of each of the plurality of heterogeneous cores, the meta instruction execution performance evaluation information of each of the plurality of heterogeneous cores, and the state information of a cache included in each of the plurality of heterogeneous cores. The multi-core processor system, characterized in that for selecting the core to run. The method of claim 1,
Temporary storage unit for receiving and storing the meta command from the memory
Further comprising:
The selection unit reads one or more meta-instructions from the temporary storage unit, and selects a core to execute the read one or more meta-instructions. The method of claim 2,
The temporary storage unit comprises a queue (Queue). delete The method of claim 1,
Status information of each of the plurality of heterogeneous cores is
And at least one of idle state information indicating that the core is in an idle state and busy state information indicating that the core is in a busy state. The method of claim 1,
The meta instruction execution performance evaluation information of each of the plurality of heterogeneous cores is
It is generated by evaluating the execution performance of the meta-instructions previously executed by each of the plurality of heterogeneous cores, or generated by evaluating the execution performance in real time with respect to the meta-instructions executed by each of the plurality of heterogeneous cores. Core processor system. The method of claim 1,
The conversion unit
A plurality of conversion modules each connected to the plurality of heterogeneous cores and converting the meta instructions into sub-commands executable in the cores connected thereto;
Multi-core processor system comprising a. The method of claim 7, wherein
The selection unit
A selection module for selecting a conversion module connected to a core to execute the meta instruction among the plurality of conversion modules; And
A transfer module for delivering the meta-command to the selected transform module
Multi-core processor system comprising a. The method of claim 1,
And the converting unit converts one meta instruction into at least one sub instruction or at least one meta instruction into one sub instruction. In the control method of a multicore processor system comprising a plurality of heterogeneous cores,
Selecting from among the plurality of heterogeneous cores a core to execute a meta instruction, which is a higher instruction defined in the multicore processor system; And
Converting the meta-instruction into a lower instruction executable in the selected core and delivering the meta-instruction to the selected core,
The selecting may be performed based on at least one of state information of each of the plurality of heterogeneous cores, meta instruction execution performance evaluation information of each of the plurality of heterogeneous cores, and state information of a cache included in each of the plurality of heterogeneous cores. A method for controlling a multicore processor system, comprising selecting a core to execute a meta instruction. The method of claim 10,
Receiving the meta-command from a memory and storing it in a queue
Further comprising:
The selecting may include reading one or more meta instructions from the queue, and selecting a core to execute each of the read one or more meta instructions. delete The method of claim 10,
The selecting may include selecting a conversion module connected to a core to execute the meta instruction from among a plurality of conversion modules respectively connected to the plurality of heterogeneous cores, and converting the meta instruction into a lower instruction executable in a core connected to the meta instruction. Making; And forwarding the meta instruction to a selected transform module,
The converting may include converting the meta-instruction into a lower instruction of a core connected to the selected transformation module through the selected transformation module.

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