CN102157382A - Hyperconjugation forming method - Google Patents
Hyperconjugation forming method Download PDFInfo
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- CN102157382A CN102157382A CN2011100562471A CN201110056247A CN102157382A CN 102157382 A CN102157382 A CN 102157382A CN 2011100562471 A CN2011100562471 A CN 2011100562471A CN 201110056247 A CN201110056247 A CN 201110056247A CN 102157382 A CN102157382 A CN 102157382A
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- backing material
- super knot
- hyperconjugation
- formation method
- ion injects
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Abstract
The invention belongs to the field of manufacturing of microelectronic components, in particular to a hyperconjugation forming method, comprising the following steps of: preparing a backing material; forming an etched deep groove in the body of the backing material; injecting impurities along the wall of the deep groove through an ion implantation method; and pushing a furnace tube to the inside to obtain hyperconjugation. The hyperconjugation forming method can reduce the steps for preparing a doping area and simplify the process flow, thus reducing the production cost.
Description
Technical field
The invention belongs to microelectronic component and make field, particularly a kind of super knot formation method.
Background technology
Mos field effect transistor (MOSFETS) is a kind of common type of device for power switching.A MOSFET device comprises a source region, a drain region, a channel region that between source and drain region, extends, an and grid structure that closely provides in channel region portion, this grid structure comprises the gate electrode layer of a conduction, and it is near but separated by dielectric layer and channel region that one deck approaches that it is positioned in this channel region portion.Super junction device (super junction devices) replaces a low-doped n type epitaxial region with a plurality of highly doped diffusion n types and p type island region in the super junction device of the n of a routine one raceway groove.Under logical state, electric current flows through highly doped n type district, and it diminishes on state resistance (Rdson).And under disconnected state, this highly doped n type and p type island region exhausts or compensate mutually so that a high puncture voltage (BVdss) to be provided, compare with common high-voltage MOSFET, the mos structure that Cool MOS(super junction structure is made) utilizes the notion of super knot (super junction), can significantly reduce chip area.With 600 volts power transistors is example, uses the conducting resistance of super-junction structure to have only 20% of equal area conventional power transistors.And its output capacitance, input capacitance also reduces synchronously, and the operating frequency characteristic is improved.The general use repeatedly of the realization of super-junction structure injected, and multilayer epitaxial forms the scheme of super knot.As described in CN101189710A, its manufacture method is as follows, comprise the Semiconductor substrate with groove and table top is provided, at least one table top has first and second sidewalls, the first side wall with the dopant doping table top of second conduction type, and with second sidewall of the dopant doping table top of second conduction type, use the first side wall of the dopant doping table top of first conduction type then, and with mix second sidewall of described at least one table top of the dopant of first conduction type, add lining with oxide material to major general and described at least one table top adjacent grooves then, fill then and go up a kind of in semi insulating material and the insulating material.Though it can make super knot, technology is very complicated, the cost costliness.
Summary of the invention
This patent has proposed a kind of formation technology that can simplify super knot, reduces the super knot formation method of manufacturing cost.
Technical scheme of the present invention is: a backing material is provided;
In this backing material body, form an etched deep trench;
With the method that ion injects, impurity is injected along the deep trench cell wall;
Boiler tube advances and obtains super knot.
As preferably, described backing material is a silicon substrate.
As preferably, the implant angle that described ion injects is 5 °-10 °.
As preferably, the implant angle that described ion injects is a plurality of.
As preferably, the injection phase that described ion injects moves from the deep trench bottom and implant angle becomes big successively.
Than existing technology, the technical program can reduce the step of making doped region, simplifies technological process, thereby reduces cost of manufacture.
Description of drawings
Fig. 1 is the backing material schematic diagram that etching of the present invention has deep trench;
Fig. 2 is that ion of the present invention injects schematic diagram;
Fig. 3 is that the super knot of the present invention forms view.
Number in the figure is as follows: 1-backing material, 2-deep trench, the super knot of 3-, β-implant angle.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in detail.As Fig. 1, Fig. 2 and shown in Figure 3, a backing material 1 is provided, in the present embodiment, backing material 1 is a silicon substrate, forms an etched deep trench 2 in silicon substrate material 1 body; With the method that ion injects, impurity is injected along deep trench 2 cell walls; Boiler tube advances and can obtain super knot.In the present embodiment, the implant angle β that ion injects is 4, and the injection phase that described ion injects moves from deep trench 2 bottoms and implant angle β becomes greatly successively, is respectively 5 °, 6 °, 8 ° and 10 °.
The invention is not restricted to the technical scheme that present embodiment provides, those skilled in the art can derive multiple scheme, and the various technical schemes under every design are all within the application's claims protection range.
Claims (5)
1. a super knot formation method is characterized in that comprising the following steps:
One backing material is provided;
In this backing material body, form an etched deep trench;
With the method that ion injects, impurity is injected along the deep trench cell wall;
Boiler tube advances and obtains super knot.
2. according to the described super knot formation method of claim 1, it is characterized in that: described backing material is a silicon substrate.
3. according to the described super knot formation method of claim 1, it is characterized in that: the implant angle that described ion injects is 5 °-10 °.
4. according to the described super knot formation method of claim 1, it is characterized in that: the implant angle that described ion injects is a plurality of.
5. according to the described super knot formation method of claim 4, it is characterized in that: the injection phase that described ion injects moves from the deep trench bottom and implant angle becomes big successively.
Priority Applications (1)
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CN2011100562471A CN102157382A (en) | 2011-03-09 | 2011-03-09 | Hyperconjugation forming method |
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CN2011100562471A CN102157382A (en) | 2011-03-09 | 2011-03-09 | Hyperconjugation forming method |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1405897A (en) * | 2001-06-11 | 2003-03-26 | 株式会社东芝 | Power semiconducter device with RESURF layer |
CN1638144A (en) * | 2003-12-25 | 2005-07-13 | 恩益禧电子股份有限公司 | Semiconductor apparatus and method for manufacturing the same |
JP2005197288A (en) * | 2003-12-26 | 2005-07-21 | Rohm Co Ltd | Fabrication process of semiconductor device and semiconductor device |
US20070080399A1 (en) * | 2004-12-24 | 2007-04-12 | Masaru Takaishi | Semiconductor device and production method therefor |
CN1992342A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Semiconductor device and method of manufacturing the same |
US20080197381A1 (en) * | 2007-02-15 | 2008-08-21 | Nec Electronics Corporation | Semiconductor device and method for manufacturing same |
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2011
- 2011-03-09 CN CN2011100562471A patent/CN102157382A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1405897A (en) * | 2001-06-11 | 2003-03-26 | 株式会社东芝 | Power semiconducter device with RESURF layer |
CN1638144A (en) * | 2003-12-25 | 2005-07-13 | 恩益禧电子股份有限公司 | Semiconductor apparatus and method for manufacturing the same |
JP2005197288A (en) * | 2003-12-26 | 2005-07-21 | Rohm Co Ltd | Fabrication process of semiconductor device and semiconductor device |
US20070080399A1 (en) * | 2004-12-24 | 2007-04-12 | Masaru Takaishi | Semiconductor device and production method therefor |
CN1992342A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Semiconductor device and method of manufacturing the same |
US20080197381A1 (en) * | 2007-02-15 | 2008-08-21 | Nec Electronics Corporation | Semiconductor device and method for manufacturing same |
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Application publication date: 20110817 |