CN102156687A - Converged-architecture processor chip - Google Patents
Converged-architecture processor chip Download PDFInfo
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- CN102156687A CN102156687A CN2011100847724A CN201110084772A CN102156687A CN 102156687 A CN102156687 A CN 102156687A CN 2011100847724 A CN2011100847724 A CN 2011100847724A CN 201110084772 A CN201110084772 A CN 201110084772A CN 102156687 A CN102156687 A CN 102156687A
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Abstract
The invention discloses a converged-architecture processor chip. The converged-architecture processor chip is characterized by comprising a public data memory and a public instruction memory which are used for converging a plurality of architecture processors; a multi-mode instruction decoding component explains instruction sets of the different architecture processors, correctly decodes all procedures running on the instruction sets of the different architecture processors, and outputs data to a public register and a calculator; and the number of stages of converging flows on the multi-mode instruction decoding component and the calculator is equal to a product formed by multiplying the number of stages of the converging flows on an instruction decoding component of the conventional discrete processor and the calculator, and the number of the plurality of architecture processors. By the converged-architecture processor chip, the utilization rate of an on-chip transistor is increased, and the problem that the transistor hardware resources are wasted due to the conventional multi-chip scheme or a spliced system chip technology is solved. The chip based on the converged-architecture technical scheme can replace a plurality of chips or reduce the area and the cost of the conventional spliced system chip greatly, so the construction cost and the production cost of electronic products, particularly high-end electronic products, are reduced greatly.
Description
Technical field
The present invention relates to a kind of processor chips, especially relate to a kind of processor chips that reduce area and cost, belong to the electronic chip technical field.
Background technology
Electronic product need use multiple chips to finish the corresponding task that it is endowed at present, each chips in the multicore sheet all has its separate processor framework, and used about several hundred million transistors to be realized, for example application processor adopts the RISC framework, multimedia processor adopts the DSP framework, and the wireless communication process device adopts communication DSP framework etc.Because each chip exists alone, its with the transistor be the hardware resource of basic comprising unit between chip, just can't share, shared.When for example smart mobile phone used the WLAN (wireless local area network) online, its WLAN (wireless local area network) chip was in work, but its 3G wireless wide area network chip is just in work, and the transistor hardware resource of integrated circuit just is not utilized thereby causes the waste of resource this moment on its chip.Present and the immediate technical scheme of the present invention is based on the single-chip integrated technology of System on Chip/SoC (being SoC), this technology adopts the integrated mode of pin-connected panel, originally a plurality of processors that belong to different chips are placed on the chips, so the area of System on Chip/SoC integrated a plurality of area of chip summations that are it, because the cost of chip and area of chip are proportional, so the solution of System on Chip/SoC and multicore sheet does not have the difference of matter on chip cost, the situation of transistor hardware resource waste is same the existence.
In addition, existing new function of the every increase of chip technology electronic product, all to increase a new chip more, or on System on Chip/SoC integrated new chip architecture in pin-connected panel ground and area thereof, such as making the mobile phone receiving digital television, just must increase a new Digital Television receiving chip on the mobile phone again or on System on Chip/SoC, increase the relevant chip area, if mobile phone is not being watched Digital Television but in other task of execution, thereby more than one hundred million transistorized resources on this Digital Television receiving chip just are used effectively and do not cause the waste of hardware resource.
No matter be multicore sheet solution, also be based on the integrated system chip technology scheme of pin-connected panel, all cause the waste of hardware resource between different processor, thereby make that the total area of chip is bigger, thereby cause cost too high because the integrated circuit transistor on the chip can't share.
Summary of the invention
Technical matters to be solved by this invention is: integrated circuit transistor can't be shared between different processor and cause the waste of hardware resource, thereby make that the total area of chip is bigger, so, reduce the core number that multicore sheet required by electronic product is wanted, or significantly reduce the chip area of System on Chip/SoC, reducing cost is to be badly in need of the technical matters that solves at present.
For solving the problems of the technologies described above, the invention provides a kind of fusion architecture processor chips, it is characterized in that: comprise the shared data internal memory and the shared instruction internal memory that merge multiple architecture processor, multimode instruction decoding parts are explained the instruction set of different architecture processors, and output data and control signal to shared register and arithmetical unit, make all programs that the fusion architecture processor can correct execution moves on different architecture processors, the progression * discrete different architecture processor quantity of the remittance current drainage on the instruction decoding parts of the processor that the progression of the remittance current drainage on described multimode instruction decoding parts and the arithmetical unit=original is discrete and the arithmetical unit.
Aforesaid fusion architecture processor chips, it is characterized in that: described shared data internal memory comprises the datarams of application processor, the datarams of multimedia digital signal processor and the datarams of number of communications word signal processor, and described shared instruction internal memory comprises the instruction internal memory of application processor, the instruction internal memory of multimedia digital signal processor and the instruction internal memory of number of communications word signal processor.
Aforesaid fusion architecture processor chips is characterized in that: described shared register comprises the register of application processor, the register of multimedia digital signal processor and the register of number of communications word signal processor.
Aforesaid fusion architecture processor chips, it is characterized in that: described arithmetical unit comprises shared arithmetical unit and special arithmetical unit, described shared arithmetical unit comprises the general character part of the arithmetical unit in application processor, multimedia digital signal processor and the number of communications word signal processor, and described special arithmetical unit comprises the special arithmetic section in the arithmetical unit of special arithmetic section in the arithmetical unit of application processor and digital signal processing.
Aforesaid fusion architecture processor chips, it is characterized in that: the program on the different architecture processors of described execution comprises the assembly routine and the corresponding software of RISC framework, the assembly routine of the assembly routine of DSP framework and corresponding software and x86 framework and corresponding software.
Aforesaid fusion architecture processor chips is characterized in that: the program on the RISC architecture processor of described execution comprises the assembly routine of ARM framework and the assembly routine and the corresponding software of corresponding software and MIPS framework.
The beneficial effect that the present invention reached:
The present invention proposes the notion and the technology implementation method of transistor reusability, and illustrated the concrete technical scheme of fusion architecture processor chips based on this, this scheme makes electronic product system when calling difference in functionality, no matter such as being the digital multimedia application, still get online without being tethered to a cable, (promptly multiplexing) same transistor is used in the capital, thereby transistorized utilization factor on the lifting chip (being reusability), the problem that the transistor hardware resource of therefore having avoided existing multicore sheet solution or pin-connected panel system chip technology to bring is wasted.Based on the alternative multiple chips of the chip of this fusion architecture technical scheme, or greatly reduce the area and the cost of present pin-connected panel System on Chip/SoC, thereby reduce the cost and the cost of the especially high-end electronic product of electronic product significantly.
Description of drawings
Fig. 1 is existing reduced instruction set computer application processor structural representation;
Fig. 2 is existing multimedia digital signal processor structure synoptic diagram;
Fig. 3 is existing number of communications word signal processor structural representation;
Fig. 4 is a fusion architecture processor structure synoptic diagram of the present invention;
Fig. 5 is the dark pipeline remittance current drainage synoptic diagram among the present invention.
Embodiment
Fig. 1-3 is existing three kinds of processor structure synoptic diagram, in existing multicore sheet solution or pin-connected panel System on Chip/SoC, by different processor chip architecture pin-connected panels combine.Each processor is by instruction internal memory (comprising buffer memory), and datarams (comprising buffer memory) is instructed and decoded, and parts such as register and arithmetical unit are formed.Because should be used as design targetedly to different, the number of the instruction set of each processor architecture (order number and decoding), register and the design of arithmetical unit all are different.For example the application processor of reduced instruction set computer ARM series uses 16 general-purpose registers, and the application processor of reduced instruction set computer MIPS series uses 32 general-purpose registers.Usually also can comprise signal Processing instruction that some are special etc. in the instruction set of DSP (digital signal processor).
Because at application different, the architecture design of different processor and corresponding instruction collection are different, software each other can not be compatible.Only need support to isolate in system, during single application, single processor chips are hardware design of system optimization, are used in the MP4 player such as only doing the multimedia decoding chip that multimedia handles.But when the system integration is multiple when being applied to all over the body, this use a plurality of chips to piece together simply to combine with the way of supporting multiple application just be not the hardware design of optimizing.The hardware resource waste that causes because of the overall reusability of transistor is low under multicore sheet situation is the mainspring that needs to do the architecture design of chip again and hardware resource is optimized.
The core technology thinking of the fusion architecture processor chips that technical scheme of the present invention proposes is farthest to improve transistorized reusability on the chip, identical transistor is shared by the system that makes when the operation different application, thereby makes the hardware resource of chip to maximize the use.The technical program comprises two-layer content and improves the transistorized reusability of processor chips, and the one, transistor spatial reuse rate, the 2nd, the time-multiplexed rate of transistor.
Fig. 4 is the fusion architecture processor chips structural representation that the present invention proposes.The mode that the general character parts utilization that the different processor framework is had is shared is carried out the simplification on the space.The datarams of application processor and instruction internal memory among Fig. 4, the datarams of multimedia digital signal processor and instruction internal memory, the datarams of number of communications word signal processor and instruction internal memory are all merged into single, a shared data internal memory and instruction internal memory; The register of application processor, 16 or 32, the register of multimedia digital signal processor is generally 32, and the register of number of communications word signal processor is generally 32, all merges into single, shared 32 registers.The general character of arithmetical unit partly is extracted out and forms single, a shared arithmetical unit in application processor, multimedia digital signal processor and the number of communications word signal processor, comprises totalizer, multiplier and shift operation etc.; Can not will be placed in the independent special arithmetical unit by special computing of the included application processor of shared arithmetical unit and the special computing of digital signal processing.Transistorized spatial reuse rate is greatly improved under fusion treatment device framework, and needed number of transistors is reduced widely on the chip, has improved the utilization factor of chip hardware resource.
The instruction decoding of fusion architecture processor can be according to the application requirements pattern of system, be that chip system is to be in the application processor pattern, or multimedia digital signal processor mode, or number of communications word signal processor pattern, or the like, the instruction that comes decoding processor to issue, multimode instruction decoding parts as shown in Figure 4, this multimode instruction decoding parts assurance fusion architecture processor can be explained the instruction set of different architecture processors exactly, make the fusion architecture processor chips as all softwares that the one chip framework can correct execution moves on different processor, comprise assembly routine.
The high performance characteristics of fusion architecture processor in order to keep the processor chip scheme to be had, the i.e. a certain integrated application of system may need the full load operation simultaneously of a plurality of processor chips, need to implement and improve transistorized time-multiplexed rate.Transistorized time-multiplexed rate is meant that the performed computing of transistor has how many times in the unit interval.The fusion architecture processor will reach carries out the operand sum of original a plurality of processor chips in the unit interval in the unit interval, need in the design of its processor architecture, the method by dark pipeline remittance current drainage promote transistorized time-multiplexed rate, as shown in Figure 5, dark pipeline converges current drainage has increased on parts such as the decoding parts of multimode instruction and arithmetical unit and has converged the progression of current drainage.The fusion architecture processor converges the progression of current drainage and need be proportional to the number of that merged, original discrete processor.Such as, if the fusion architecture processor merged application processor, multimedia digital signal processor mode and number of communications word signal processor pattern, it should be that original discrete processor converges 3 times of current drainage progression that its processor converges the progression of current drainage; Transistorized time delay is inversely proportional to the progression of remittance current drainage in the processor, the progression of current drainage of promptly converging is high more, each transistorized time delay of converging between the current drainage is just short more, thereby processor may operate on 3 times of high clock frequencies, thereby guarantee that the operand in the fusion architecture processor unit interval improves 3 times, make its performance satisfy discrete performance of processors summations such as original application processor, multimedia digital signal processor and number of communications word signal processor.
Fusion architecture processor adopting of the present invention transistorized spatial reuse and time-multiplexed method, quantity and the pairing chip of these discrete processors and the transistorized number of discrete processor have been reduced effectively, thereby reduced the total area of chip, kept the performance of original multiprocessor or multicore sheet solution simultaneously again.The fusion architecture processor chips can compatible different processor architecture as the one chip framework, and both it can move the software of different processor.The instruction set of different processor framework is explained exactly by the fusion architecture processor by single multimode instruction decoding parts and is carried out.The fusion architecture processor is supported the instruction set with compatible different architecture processors.The pattern of different processor refers to the framework kind of the discrete processors that the fusion architecture processor chips can be compatible, protects and draws together series such as RISC framework, DSP framework and x86 framework.Include fusion architecture processor chips and compatible with it discrete processors framework in and comprise reduced instruction set computer (RISC) processor based on ARM and MIPS framework, the x86 architecture processor, digital signal processor (DSP), multimedia digital signal processor and number of communications word signal processor etc.The discrete processors of including the fusion architecture processor in can be discrete chip, also can be the body that exists that is integrated into discrete processors in the System on Chip/SoC.
RISC: reduced instruction set computer, or based on the processor of reduced instruction set computer
DSP: digital signal processing, or based on the processor of digital signal processing instructions collection
SoC: System on Chip/SoC
Above-mentioned embodiment does not limit technical scheme of the present invention in any form, and the technical scheme that mode obtained that every employing is equal to replacement or equivalent transformation all drops on protection scope of the present invention.
Claims (6)
1. fusion architecture processor chips, it is characterized in that: comprise the shared data internal memory and the shared instruction internal memory that merge multiple architecture processor, multimode instruction decoding parts are explained the instruction set of different architecture processors, and output data and control signal to shared register and arithmetical unit, make all programs that the fusion architecture processor can correct execution moves on different architecture processors, the progression * discrete different architecture processor quantity of the remittance current drainage on the instruction decoding parts of the processor that the progression of the remittance current drainage on described multimode instruction decoding parts and the arithmetical unit=original is discrete and the arithmetical unit.
2. fusion architecture processor chips according to claim 1, it is characterized in that: described shared data internal memory comprises the datarams of application processor, the datarams of multimedia digital signal processor and the datarams of number of communications word signal processor, and described shared instruction internal memory comprises the instruction internal memory of application processor, the instruction internal memory of multimedia digital signal processor and the instruction internal memory of number of communications word signal processor.
3. fusion architecture processor chips according to claim 1 and 2 is characterized in that: described shared register comprises the register of application processor, the register of multimedia digital signal processor and the register of number of communications word signal processor.
4. fusion architecture processor chips according to claim 1 and 2, it is characterized in that: described arithmetical unit comprises shared arithmetical unit and special arithmetical unit, described shared arithmetical unit comprises the general character part of the arithmetical unit in application processor, multimedia digital signal processor and the number of communications word signal processor, and described special arithmetical unit comprises the special arithmetic section in the arithmetical unit of special arithmetic section in the arithmetical unit of application processor and digital signal processing.
5. fusion architecture processor chips according to claim 1, it is characterized in that: the program on the different architecture processors of described execution comprises the assembly routine and the corresponding software of RISC framework, the assembly routine of the assembly routine of DSP framework and corresponding software and x86 framework and corresponding software.
6. fusion architecture processor chips according to claim 1 or 5, it is characterized in that: the program on the RISC architecture processor of described execution comprises the assembly routine of ARM framework and the assembly routine and the corresponding software of corresponding software and MIPS framework.
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| CN2011100847724A CN102156687A (en) | 2011-04-06 | 2011-04-06 | Converged-architecture processor chip |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1053694A (en) * | 1990-01-24 | 1991-08-07 | 国际商业机器公司 | Occupy the diagnostic test of memory board |
| CN101546301A (en) * | 2009-05-05 | 2009-09-30 | 浪潮电子信息产业股份有限公司 | Method of synergetic computer comprising heterogeneous processors |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1053694A (en) * | 1990-01-24 | 1991-08-07 | 国际商业机器公司 | Occupy the diagnostic test of memory board |
| CN101546301A (en) * | 2009-05-05 | 2009-09-30 | 浪潮电子信息产业股份有限公司 | Method of synergetic computer comprising heterogeneous processors |
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Application publication date: 20110817 |