CN102136885B - Parallel physical uplink shared channel (PUSCH) interleaving and scrambling realization method and system for 3rd-generation partnership project long term evolution (3GPP LTE) - Google Patents

Abstract

The present invention provides a method and system for implementing 3GPP LTE PUSCH channel parallel channel interleaving and scrambling, the method comprising: 1) encoding RI information and ACK/NACK information; 2) inputting RI information, control and data information and ACK/NACK information, and store the row number last_row_index _RI and column number last_column_index RI _{where the last written RI information is located, and the row number last_row_index ACK and} column number last_column_index _ACK where the last written ACK/NACK information is located, according to the last written The row number and column number where the RI information is located and the row number and column number where the last written ACK/NACK information is located perform channel interleaving output operations; 3) Scramble the RI information, control and data information, and ACK/NACK information . The invention has fast processing speed, the coding mode has nothing to do with the QAM adjustment mode, and saves storage space.

Description

A method and system for implementing 3GPP LTE PUSCH channel parallel channel interleaving and scrambling

technical field

The present invention relates to the technical field of mobile communication, in particular to a method and system for realizing channel interleaving and scrambling of an uplink shared channel (PUSCH) in a third generation partnership project long term evolution system (3GPP LTE).

Background technique

The uplink of the 3GPP LTE communication system refers to the transmission from the user terminal (UE) to the base station (eNodeB). The uplink channels include the uplink shared channel (PUSCH), the uplink control channel (PUCCH) and the random access channel (PRACH). Among them, PUSCH mainly transmits data information, and can also transmit control information, such as channel quality indicator information (CQI, channel quality indicator), rank indicator information (RI, rank indication) and hybrid automatic retransmission request acknowledgment information (HARQ-ACK), where Hybrid Automatic Repeat Request Acknowledgment (HARQ-ACK) is also called ACK/NACK information.

The process of PUSCH encoding is shown in Figure 1. It can be seen that the input of channel interleaving has three parts: multiplexed channel-coded data and CQI information, channel-coded RI information and channel-coded HARQ-ACK information. Since the encoding methods of RI and HARQ-ACK are closely related to channel interleaving and scrambling, they are briefly introduced first.

The channel coding of RI information is related to the quadrature amplitude modulation (QAM) method, and is divided into the following two categories according to the number of input bits, as shown in Table 1 and Table 2 respectively:

Table 11 Coding of bit RI information

Table 22 Encoding of RI information

其最左边为最低有效位(LSB)；表1和表2中x和y是用于增加调制符号欧氏距离的占位符。Table 2

The leftmost is the least significant bit (LSB); x and y in Table 1 and Table 2 are placeholders used to increase the Euclidean distance of the modulation symbol.

Regarding the channel coding of HARQ-ACK, firstly, ACK is represented by binary "1", and NACK is represented by binary "0". It is known that time division multiplexing (TDD) ACK/NACK coding has two feedback modes: bundling and multiplexing. For the bundling feedback mode, HARQ-ACK consists of 1-2 bits of information; for the multiplexing feedback mode, HARQ-ACK consists of 1-4 bits. Like the RI information, the coding method of the HARQ-ACK channel coding is also related to the QAM method. The specific description is as follows:

ACK/NACK multiplexing feedback 1-bit coding and 2-bit coding are shown in Table 3 and Table 4 respectively:

Encoding of Table 31 bit HARQ-ACK/NACK information

Encoding of 42-bit HARQ-ACK/NACK information in table

Table 4 The leftmost is the least significant bit (LSB); x and y in Table 3 and Table 4 are placeholders used to increase the Euclidean distance of the modulation symbol.

将其进行选择后与加扰序列按一定方式加扰(异或)，得到捆绑反馈编码的输出序列为

加扰方式为加扰数据位和占位符“y”，占位符“x”不变。其中加扰序列如表5中所示：ACK/NACK bundling feedback coding is to scramble the output data of ACK/NACK multiplexing feedback 1 or 2-bit coding, assuming that the output sequence of ACK/NACK multiplexing feedback 1 or 2-bit coding is

After it is selected, it is scrambled (XOR) with the scrambling sequence in a certain way, and the output sequence of the bundled feedback code is obtained as

The scrambling method is scrambling data bits and a placeholder "y", and the placeholder "x" remains unchanged. The scrambling sequence is shown in Table 5:

Table 5 TDD ACK/NACK bunding coding scrambling sequence

Wherein, i=(N _bundled -1)mod 4, where N _bundled is an input parameter.

The base sequence of table 6 (32, O)

i M _i,0 M _i,1 Mi _{, 2} Mi _{, 3} Mi _{, 4} Mi _{, 5} Mi _{, 6} Mi _{, 7} Mi _{, 8} Mi _{, 9} Mi _{, 10} 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 2 1 0 0 1 0 0 1 0 1 1 1 3 1 0 1 1 0 0 0 0 1 0 1 4 1 1 1 1 0 0 0 1 0 0 1 5 1 1 0 0 1 0 1 1 1 0 1 6 1 0 1 0 1 0 1 0 1 1 1 7 1 0 0 1 1 0 0 1 1 0 1 8 1 1 0 1 1 0 0 1 0 1 1 9 1 0 1 1 1 0 1 0 0 1 1 10 1 0 1 0 0 1 1 1 0 1 1 11 1 1 1 0 0 1 1 0 1 0 1 12 1 0 0 1 0 1 0 1 1 1 1 13 1 1 0 1 0 1 0 1 0 1 1 14 1 0 0 0 1 1 0 1 0 0 1 15 1 1 0 0 1 1 1 1 0 1 1 16 1 1 1 0 1 1 1 0 0 1 0 17 1 0 0 1 1 1 0 0 1 0 0 18 1 1 0 1 1 1 1 1 0 0 0 19 1 0 0 0 0 1 1 0 0 0 0 20 1 0 1 0 0 0 1 0 0 0 1 twenty one 1 1 0 1 0 0 0 0 0 1 1 twenty two 1 0 0 0 1 0 0 1 1 0 1 twenty three 1 1 1 0 1 0 0 0 1 1 1 twenty four 1 1 1 1 1 0 1 1 1 1 0 25 1 1 0 0 0 1 1 1 0 0 1 26 1 0 1 1 0 1 0 0 1 1 0 27 1 1 1 1 0 1 0 1 1 1 0 28 1 0 1 0 1 1 1 0 1 0 0 29 1 0 1 1 1 1 1 1 1 0 0 30 1 1 1 1 1 1 1 1 1 1 1 31 1 0 0 0 0 0 0 0 0 0 0

输出序列为

则编码方式为：For ACK/NACK multiplexing feedback 3 or 4-bit coding, assume that the input sequence is

The output sequence is

Then the encoding method is:

其中M_i，o如表6所示。

Among them, M _{i, o} are shown in Table 6.

The function of channel interleaving is to interweave data information and control information together. The interleaving process in the prior art is described as follows:

其中

代表一个子帧中用于PUSCH传输的SC-OFDM符号个数，代表一个时隙中SC-OFDM符号的个数，N_SRS代表一个子帧中用于SRS传输的SC-OFDM符号个数；行数R_mux＝H″/C_mux，其中H″代表一个子帧中所有调制符号的个数；Step 1, calculate the number of columns and rows of the subframe interleaving matrix, the number of columns

in

Represents the number of SC-OFDM symbols used for PUSCH transmission in a subframe, Represents the number of SC-OFDM symbols in a time slot, N _SRS represents the number of SC-OFDM symbols used for SRS transmission in a subframe; the number of rows R _mux = H″/C _mux , where H″ represents a subframe The number of all modulation symbols in ;

Step 2, if the RI information is transmitted on the subframe, fill the RI coded information from the last row upwards according to the column order shown in Table 7;

Table 7 Column set of RI information in the channel interleaving matrix

Cyclic prefix configuration (CP configuration) The column number where the RI is located Normal state (common) {1, 10, 7, 4} Extended state (extended) {0, 8, 5, 3}

Step 3, after the RI is filled, fill the multiplexed data and CQI information from the first row of the matrix to the bottom one by one, and skip if RI information is encountered;

Step 4, if the HARQ-ACK information is transmitted on the subframe, fill it from the last row upwards according to the column order shown in Table 8, and overwrite it if the position to be filled has the data filled in step 3;

Table 8 Column set of HARQ-ACK information in channel interleaving matrix

Cyclic prefix configuration (CP configuration) The column number where the HARQ-ACK is located Normal state (common) {2, 9, 8, 3} Extended state (extended) {1, 7, 6, 2}

Step 5: Read the bit sequence column by column from the interleaving matrix (R _mux *C _mux ) as the output of the channel interleaver.

Finally, the scrambling module scrambles the output of channel interleaving, and the scrambling rule is:

If the scrambled data is a placeholder "x", it will be "1" after scrambling.

If the scrambled data is a placeholder "y", it will be "the scrambled value of the previous bit" after scrambling.

If it is not a placeholder, it will be the XOR value of the random sequence and the scrambled data after scrambling.

In the prior art as mentioned above, since the scrambling module after channel interleaving adopts different scrambling methods according to different data types, each data in the interleaver needs to store two additional bits to indicate the data type , where the data types include: RI, HARQ-ACK, multiplexed data, and CQI information as described above, which wastes a lot of storage space; both RI encoding and HARQ-ACK encoding are related to QAM; there are x, y placeholders , increasing the complexity; at the same time, the amount of data in the interleaving and scrambling part is large, and operations are performed on a per-bit basis in the prior art, which takes a long time and affects the rate of the entire system.

Contents of the invention

The purpose of the present invention is to solve the shortcomings of the above-mentioned prior art that require a large amount of storage space and slow speed, and propose a 3GPP LTE PUSCH channel parallel channel interleaving and scrambling method by using the characteristics of the control information RI and HARQ-ACK coding methods Implementation.

According to an invention of the present invention, a kind of realization method of 3GPP LTE PUSCH channel parallel channel interleaving and scrambling is provided, comprising the following steps:

1) Encoding RI information and ACK/NACK information;

2) Input RI information, control and data information, and ACK/NACK information, and store the row number last_row_index _RI and column number last_column_index _RI where the last written RI information is located and the row number last_row_index _ACK where the last written ACK/NACK information is located and column number last_column_index _ACK , perform channel interleaving output operation according to the row number and column number where the last written RI information is located and the row number and column number where the last written ACK/NACK information is located;

3) Scrambling RI information, multiplexed control and data information, and ACK/NACK information.

In the above method, said step 2) further includes:

21) Calculate the number of rows and columns of the interleaving matrix occupied by the subframe in the channel interleaving memory;

22) From the last row of the channel interleaving memory matrix, write RI information up and store the row number last_row_index _RI and column number last_column_index _RI where the last written RI information is located;

23) Write the multiplexed data and CQI information according to the row number and column number where the last written RI information is located;

24) Write ACK/NACK information;

25) According to the row number and column number where the last written RI information is located and/or the row number and column number where the last written ACK/NACK information is located, output all information and data in the channel interleaving matrix by column.

In the above method, the step of encoding the RI information in step 1) includes: encoding the RI information into 6-bit data, wherein the first 4 bits are all 1, and the last two bits are the least significant bits.

In the above method, the step of encoding the ACK/NACK information in step 1) includes: encoding the 1 or 2-bit ACK/NACK information in the multiplexed feedback mode into 6-bit data, wherein the first 4 bits are all 1 , the last two digits are the least significant digits.

In the above method, the step of encoding the ACK/NACK information in step 1) includes: first, encoding the 1 or 2-bit ACK/NACK information in the bundling mode according to the encoding method adopted in the multiplexing feedback mode; then The scrambling sequence is regarded as a 12-bit circular shift register, and each rising edge of the clock shifts two bits to the right and adds to the leftmost end of the register, and the obtained 2-bit output data and the lowest 2 bits of the output data of the multiplexed feedback mode Do scrambling.

In the above method, when encoding the 3 or 4-bit ACK/NACK information in the multiplexing feedback mode in the step 1), the input sequence and the base sequence are bitwise ANDed, and the obtained sequence is completed by bitwise exclusive OR Modulo 2 accumulates.

In the above method, said step 3) includes:

31) Initialize the pseudo-random scrambling sequence in a 31-bit parallel manner;

32) Generate a pseudo-random scrambling sequence in parallel and recursively according to the initialized pseudo-random scrambling sequence;

33) Perform data scrambling using the generated pseudo-random scrambling sequence.

According to another aspect of the present invention, a kind of 3GPP LTE PUSCH channel parallel channel interleaving and scrambling system is also provided, comprising:

RI channel coder, for carrying out channel coding to RI information;

HARQ-ACK channel encoder, used for channel encoding ACK/NACK information;

Channel interleaving system, input RI information, control and data information and ACK/NACK information, store the row number last_row_index _RI and column number _{last_column_index} of the last written RI information, and the row number last_row_index of the last written ACK/NACK information _ACK and column number last_column_index _ACK , perform channel interleaving output operation according to the row number and column number where the last written RI information is located and/or the row number and column number where the last written ACK/NACK information is located;

The scrambling device is used for scrambling RI information, multiplexed control and data information, and ACK/NACK information.

In the above channel interleaving and scrambling system, the channel interleaving system includes a channel interleaving write controller, a channel interleaving memory, and a channel interleaving read controller, wherein

The channel interleaving and writing controller, first, calculates the number of rows and columns of the interleaving matrix occupied by the subframe in the channel interleaving memory; then, writes RI information upwards from the last row of the channel interleaving memory matrix and stores the last written RI The row number last_row_index _RI and the column number last_column_index _RI where the information is located, write the multiplexed data and CQI information according to the row number and column number of the last written RI information, and write the ACK/NACK information;

A channel interleaving memory, used to store RI information, multiplexed data and control information, and ACK/NACK information;

The channel interleaving read controller is used to receive the number of rows and columns of the channel interleaving matrix calculated by the channel interleaving write controller, and output all information stored in the channel interleaving memory by column.

In the above channel interleaving and scrambling system, the channel interleaving memory includes 12 sub-memory, and each sub-memory stores one column of information.

In the present invention, RI coding, HARQ-ACK coding, channel interleaving and scrambling modules are operated by symbols, which greatly improves the processing speed compared with bit-level operations; the coding and interleaving stages do not need to generate and store "x" and "y " placeholder, so that the encoding method has nothing to do with the QAM adjustment method; judge whether it is RI and HARQ-ACK information by the last written RI and HARQ-ACK address during interleaving, saving storage space; scrambling adopts parallel scrambling method, The type of the element is judged by the indicator signal generated above, and the symbol scramble is performed, which reduces the hardware overhead and further speeds up the scrambling speed.

Description of drawings

Figure 1 is a schematic diagram of the data flow of 3GPP LTE PUSCH channel coding;

2 is a block diagram of a 3GPP LTE PUSCH channel parallel channel interleaving and scrambling system according to a preferred embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the interleaving and scrambling method and system according to an embodiment of the present invention will be further described in detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

According to a preferred embodiment of the present invention, the method comprises the following steps:

101.RI (Rank indicator) channel coding

最右边是最低有效位(LSB)，将其连续输出，直到输出符号数达到规定的数目。如果有2比特RI信息，则编码后的符号为

其中

最右边是最低有效位(LSB)，将它们依次循环输出，直到输出符号数达到规定的数目。The RI has at most 2 bits of valid information. Specifically, when interleaving and scrambling by symbol, only the lower two bits of a coded symbol are valid, and the higher bits are x or invalid. Therefore, in a preferred embodiment of the present invention, the data bit width is set to 6 bits, and the upper 4 bits are fixed to 1, so that the RI channel coding has nothing to do with the QAM modulation mode. The specific implementation is as follows: If only 1 bit RI information , then a coded symbol is

The rightmost is the least significant bit (LSB), which is continuously output until the number of output symbols reaches the specified number. If there is 2-bit RI information, the coded symbol is

in

The rightmost is the least significant bit (LSB), and they are output cyclically in turn until the number of output symbols reaches the specified number.

Those skilled in the art can understand that a preferred RI (Rankindicator) channel coding method is given above, but it can also be implemented by other methods, such as those stipulated in the 3GPP protocol.

102.HARQ-ACK channel coding

For ACK/NACK multiplexing feedback 1, 2-bit coding, when operating according to the symbol, only the lower two bits in a coded symbol are valid, and the upper bit is x or invalid. Therefore, in the preferred embodiment of the present invention, the data bit width is set to 6 bits, and the upper 4 bits are fixed as 1, so that the HARQ-ACK channel coding has nothing to do with the QAM modulation mode. In this case, the implementation manner is the same as that of the RI, and will not be repeated here. Since the RI coding and the HARQ-ACK coding do not need to be performed simultaneously, the RI coding circuit can be used to realize the HARQ-ACK coding.

For ACK/NACK bundling feedback, the encoding method is to perform 1 or 2-bit encoding of ACK/NACK multiplexing feedback, and then scramble (exclusive OR) the output data of ACK/NACK multiplexing feedback. During implementation, according to the scrambling method, one scrambled bit is read at a time during 1-bit encoding, and the same scrambled bit is read three times during 2-bit encoding, and the scrambling sequence w ^ACK is regarded as a 12-bit cyclic shift Bit register, each clock rising edge shifts two bits to the right and adds to the leftmost end (MSB) of the register, and the resulting 2-bit output data w ^ACK [1:0] and ACK/NACK multiplexing feedback output data The lowest 2 bits Do scrambling.

The initial value of the scrambling sequence w ^ACK is shown in Table 9 for 1-bit encoding, and shown in Table 10 for 2-bit encoding, where i=(N _bundled -1) mod 4, where N _bundled is an input parameter.

Table 9 HARQ-ACK/NACK 1-bit bundling feedback coding scrambling sequence

i w ^ACK [11:0] 0 1111_1111_1111 1 0101_0101_0101 2 0011_0011_0011 3 1001_1001_1001

Table 10 HARQ-ACK/NACK 2-bit bundling feedback coding scrambling sequence

i w ^ACK [11:0] 0 1111_1111_1111 1 0001_1100_0111 2 0000_0011_1111 3 1110_0000_0111

输出序列为

则编码方式为：For ACK/NACK multiplexing feedback 3, 4-bit coding, assume that the input sequence is

The output sequence is

Then the encoding method is:

Preferably, the input sequence is bitwise ANDed with [M _{(i mod 32), 0} , M _{(i mod 32), 1} , M _{(i mod 32), 2} , M _{(i mod 32), 3,} ], The obtained sequence is then completed by bitwise XOR to complete the modulo 2 accumulation to obtain the output sequence Thus, the encoding process can be completed after one clock cycle.

Those skilled in the art can understand that a preferred HARQ-ACK channel coding method is given above, but it can also be implemented by other methods, such as those stipulated in the 3GPP protocol.

103. Channel Interleaving

The specific process is as follows.

Step 1: Calculate the number of rows and columns of the subframe in the channel interleaving memory.

其中

代表一个子帧中用于PUSCH传输的SC-OFDM符号个数，

代表一个时隙中SC-OFDM符号的个数，N_SRS代表一个子帧中用于SRS传输的SC-OFDM符号个数；行数R_mux＝H″/C_mux，其中H″代表一个子帧中所有调制符号的个数。Number of columns

in

Represents the number of SC-OFDM symbols used for PUSCH transmission in a subframe,

Represents the number of SC-OFDM symbols in a time slot, N _SRS represents the number of SC-OFDM symbols used for SRS transmission in a subframe; the number of rows R _mux = H″/C _mux , where H″ represents a subframe The number of all modulation symbols in .

Step 2: If the RI information is transmitted on the subframe, write the RI information upwards from the last row of the channel interleaving memory matrix and store the position of the last written RI, where last_row_index _RI and last_column_index _RI are the last written The row and column number of the imported RI. The location of the last written RI can be used in subsequent steps, thereby avoiding the need to store two additional bits to indicate the data type of the RI, thereby saving a large amount of storage space.

Step 3: Write the multiplexed data and CQI information. The CQI information comes first, and the data information follows. At this time, it is necessary to skip the previously input RI information when writing, and it is necessary to determine the positions of all RIs based on the row and column position information of the last written RI. Let row_index be the row number to which the current input data is written.

Step 3.1, when row_index<last_row_index _RI , there is no RI information in this row, and the multiplexed data and CQI information are written into the interleaver in sequence;

Step 3.2, when row_index=last_row_index _RI , that is, when the last row written by RI is reached, the column positions of all RI symbols in this row are shown in Table 11:

Table 11 The column number of the last written RI

The relationship table with the number of the column where RI exists in the row where the last written RI is located

表示最后写入的RI所处的行中存在RI的列的编号，将复用后的数据和CQI信息写入交织器时需要跳过这些位置。in

Indicates the number of the RI column in the row where the last written RI is located, and these positions need to be skipped when writing the multiplexed data and CQI information into the interleaver.

表示该行所有RI符号所处的列位置。对于普通CP，

10、7或4；对于扩展CP，8、5或3，将复用后的数据和CQI信息写入交织器时需要跳过这些位置。Step 3.3, when R _mux >= row_index > last_row_index _RI , use

Indicates the column position of all RI symbols in the row. For ordinary CP,

10, 7 or 4; for extended CP, 8, 5 or 3, these positions need to be skipped when writing the multiplexed data and CQI information into the interleaver.

Step 4, if the HARQ-ACK information is transmitted on the subframe, write the HARQ-ACK information.

Step 5, output of channel interleaving: data readout is carried out by column, starting from the first column and first row, after reading the first column, then turn to the second column, proceed to the c _mux column, and read all the data.

When the RI information is read, the RI indicator signal is set high, and when the HARQ-ACK information is read, the HARQ-ACK indicator signal is set high.

If the current column number is 1, 10, 7, 4 in the normal CP case or 0, 8, 5, 3 in the extended CP case, and the row number satisfies row_index≥last_row_index _RI +1-ri_indicator[i]), it means the current symbol For the RI information symbol, the RI indication signal needs to be set high. Where ri_indicator[i] is determined by the column position last_column_index _RI where the last RI symbol is located, as shown in Table 12:

Table 12

i=0, 1, 2, 3, represents the position of the current column in the 4 possible RI columns. When setting the normal CP situation, the 1st column is i=0; the 4th column is i=1; the 7th Column is i=2; column 10 is i=3; column 0 is i=0; column 3 is i=1; column 5 is i=2; column 8 is i=3 .

If the current column number is 2, 9, 8, 3 in the normal CP case or 1, 7, 6, 2 in the extended CP case, and the row number satisfies row_index≥last_row_index _ACK +1-ack_indicator[i], it means that the current symbol is For the HARQ-ACK information symbol, the HARQ-ACK indication signal needs to be set high. Where ack_indicator[i] is determined by the column position last_column_index _ACK where the last HARQ-ACK symbol is located, as shown in Table 13:

Table 13

i=0, 1, 2, 3, representing the position of the current column in the 4 possible HARQ-ACK columns. When setting the normal CP situation, the second column is i=0; the third column is i=1; The 8th column is i=2; the 9th column is i=3; when extending the CP case, the 1st column is i=0; the 2nd column is i=1; the 6th column is i=2; the 7th column is i =3.

104. The scrambling is preferably performed in parallel.

Step 1: Initialize the pseudo-random scrambling sequence

Let c represent a pseudo-random sequence, and use the largest 31-bit parallel calculation to obtain x1(1600) and x2(1600), thereby obtaining the initial value c(0) of the pseudo-random scrambling sequence=(x1(1600)+x2(1600 ))mod2, the specific generation formula of the pseudo-random sequence refers to the protocol 3GPP 36.211 Section 7.2.

The parallel calculation method is that both x1 and x2 are represented by 31-bit registers, and the values of x1[30:0] and x2[30:0] containing 31 initial bits are calculated at the initial moment; after that, each clock cycle can be parallelized The 31-bit x1 and x2 are obtained by recursion; in the last initialization cycle clock, which is the 52nd clock cycle, only the upper 19 bits of x1 and x2 are recursively calculated to obtain x1 (1600) and x2 (1600).

Step 2: Generate pseudo-random scrambling sequence

At the same time, pseudo-random scrambling sequences of 2 bits c[1:0], 4 bits c[3:0], and 6 bits c[5:0] are generated in parallel, corresponding to scrambling in the case of QPSK, QAM16, and QAM64, respectively.

The parallel calculation method is similar to step 1, except that the number of bits for each parallel recursion is different. Parallel recursion x1[1:0] and x2[1:0] in QPSK mode; parallel recursion x1[3:0] and x2[3:0] in QAM16 mode; parallel recursion x1[5 in QAM64 mode :0] and x2[5:0]. Then calculate c[1:0], c[3:0] or c[5:0] based on x1 and x2.

Step 3: Data Scrambling

In this step, scrambling needs to be performed according to the scrambling rules of the protocol. Since there are no placeholders "x" and "y" in the present invention, the scrambling methods for different information or data include the following three types:

Method a: scramble the lowest bit, the second lowest bit is the same as the lowest bit, that is, the input data is scrambled with 6 bits of {0000, c[0], c[0]}.

Method b: Scramble the lowest 2 bits, that is, input data and 6-bit {0000, c[1:0]} are scrambled;

Method c: all scrambled, that is, the input data is scrambled with 6-bit c[5:0].

According to a specific embodiment of the present invention, the complete scrambling scheme is:

If the input is RI information, in the case of 1-bit encoding, use method a; in the case of 2-bit encoding, use method b;

If the input is multiplexed control and data information, all scrambled, adopt method c;

If the input is HARQ-ACK information, when the feedback mode is 1-bit multiplex feedback, use method a; when multiplex feedback 2 bits, use method b; in the case of other HARQ-ACK information, scramble all data, use method c .

According to another aspect of the present invention, also provide a kind of 3GPP LTE PUSCH channel parallel channel interleaving and scrambling system, its structure is as shown in Figure 2, and this system mainly comprises the following several parts:

RI channel encoder 201, configured to perform channel encoding on RI information. According to a preferred embodiment of the present invention, the RI information is encoded as 6-bit data, wherein the first 4 bits are all 1, and the last two bits are the least significant bits.

The HARQ-ACK channel encoder 202 is configured to perform channel encoding on ACK/NACK information. According to a preferred embodiment of the present invention: the 1 or 2-bit ACK/NACK information in the multiplexing feedback mode is encoded as 6-bit data, wherein the first 4 bits are all 1, and the last two bits are the least significant bits; in the bundling mode, first , use the 1 or 2-bit encoding method in the multiplexing feedback mode to encode 6-bit data, in which the first 4 bits are all 1, and the last two bits are the least significant bits; then the scrambling sequence is regarded as a 12-bit circular shift register , each clock rising edge shifts two bits to the right and adds to the leftmost end of the register, and the obtained 2-bit output data and the lowest 2 bits of the output data in the multiplexed feedback mode are scrambled; the 3 or 2 bits in the multiplexed feedback mode When 4-bit ACK/NACK information is encoded, the input sequence and the base sequence are bitwise ANDed, and the obtained sequence is then bitwise XORed to complete modulo 2 accumulation.

Channel interleaving system 210 stores the row number last_row_index _RI and column number last_column_index _RI of the last written RI information and the row number of the last written ACK/NACK information during the input of channel interleaving (writing channel interleaving memory) last_row_index _ACK and column number last_column_index _ACK , and then perform channel interleaving output (read channel interleaving memory) operation according to them. In a preferred embodiment of the present invention, the channel interleaving system 210 includes a channel interleaving write controller 211 , a channel interleaving memory 212 and a channel interleaving read controller 213 .

The channel interleaving write controller 211 is used to calculate the number of rows and columns of the interleaving matrix occupied by the subframe in the channel interleaving memory 212, and accordingly write all information to the corresponding addresses in the channel interleaving memory 212 according to their respective types . Preferably, the channel interleaving write controller 203 includes a state machine, which is used to control the sequence of writing data streams. In this preferred embodiment, the writing sequence is to sequentially input RI information, multiplexed data and control information , ACK/NACK information. The specific writing process is: first, write RI information up from the last line of the channel interleaving memory matrix and store the row number last_row_index _RI and column number last_column_index _RI where the last written RI information is in the register; then, Write the multiplexed data and CQI information according to the row number and column number where the last written RI information is located; finally, write the ACK/NACK information.

The channel interleaving memory 212 is used to store RI information, multiplexed data and control information, and ACK/NACK information. Since channel interleaving is carried out by symbol in hardware implementation, that is, QPSK 2bit, QAM16 4bit, QAM64 6bit, so preferably, the channel interleaving memory includes a group of 12 sub-memory, and each sub-memory stores 1 column of information. The width of the sub-memory is 6 bits, and the depth is the column length of the interleaver, that is, the number of sub-carriers is 12×110=1320.

The channel interleaving read controller 213 is used to receive the number of rows and columns of the interleaving matrix occupied by the subframe in the channel interleaving memory 212 calculated by the channel interleaving writing controller, and output all information stored in the channel interleaving memory accordingly. Specifically, the output is carried out by column, starting from the first column and the first row, after reading the first column, then turning to the second column, and proceeding to the c _mux column, when the RI information is read, the RI indicator signal is set to High, when HARQ-ACK information is read, set the HARQ-ACK indication signal high.

The scrambling device 220 is configured to scramble RI information, control and data information, and ACK/NACK information. According to a preferred embodiment of the present invention, the scrambling process is done in parallel.

It should be noted and understood that various modifications and improvements can be made to the invention described in detail above without departing from the spirit and scope of the invention as claimed in the appended claims. Accordingly, the scope of the claimed technical solution is not limited by any particular exemplary teaching given.

Claims (10)

1. a 3GPP LTE PUSCH channel parallel channel interweaves and the implementation method of scrambling, comprises the following steps:

1) RI information and ACK/NACK information are encoded;

2) input RI information, the control after multiplexing and data message and ACK/NACK information are carried out channel interleaving, comprising:

21) transmit in subframe when RI information, begin up to write the line number last_row_index at the RI information place that RI information and storage write at last from last column of channel interleaving memory matrix _RIWith column number last_column_index _RI

22) according to line number and the column number at the RI information place that writes at last, skip the RI information that writes previously, write data and control information after multiplexing, wherein control information is front, and data message is rear;

23) transmit in this subframe when ACK/NACK information, write ACK/NACK information;

24) according to the line number at the line number at the RI information place that writes at last and column number and the ACK/NACK information place that writes at last and the output function that column number carries out channel interleaving;

3) RI information, control after multiplexing and data message and ACK/NACK information are carried out scrambling.

2. method according to claim 1 is characterized in that, described step 21) also comprise before:

20) calculate the row, column number of the interleaver matrix that subframe takies in the channel interleaving memory.

3. method according to claim 1 and 2 is characterized in that, the step of in the described step 1) RI information being encoded comprises: be 6 Bit datas with the RI information coding, wherein front 4 are 1, and rear two is least significant bit.

4. method according to claim 1 and 2, it is characterized in that, the step of in the described step 1) ACK/NACK information being encoded comprises: 1 or 2 bit ACK in the multiplexing feedback model/nack message is encoded to 6 Bit datas, and wherein front 4 are 1, and rear two is least significant bit.

5. method according to claim 1 and 2, it is characterized in that, the step of in the described step 1) ACK/NACK information being encoded comprises: at first 1 in the tie-in mode or 2 bit ACK/nack message are encoded according to the coded system that multiplexing feedback model adopts; Then scramble sequence is used as 12 circulating register, each rising edge clock dibit that moves to right adds the high order end of this register to, and the 2 bits output data of acquisition and 2 minimum bits of output data of multiplexing feedback model carry out scrambling.

6. method according to claim 1 and 2, it is characterized in that, in the described step 1) during to 3 or 4 bit ACK in the multiplexing feedback model/nack message coding, with list entries and basic sequence carry out step-by-step with, the sequence that obtains is finished mould 2 by the step-by-step XOR again and is added up.

7. method according to claim 1 and 2 is characterized in that, described step 3) comprises:

31) the mode initializing pseudo random scramble sequence of employing 31 parallel-by-bits;

32) generate the pseudorandom scramble sequence according to initialized pseudorandom scramble sequence Parallel Recursive;

33) utilize the pseudorandom scramble sequence that generates to carry out data scrambling.

8. a 3GPP LTE PUSCH channel parallel channel interweaves and scrambling system, comprising:

The RI channel encoder is used for RI information is carried out chnnel coding;

The HARQ-ACK channel encoder is used for ACK/NACK information is carried out chnnel coding;

The channel interleaving system, be used for input RI information, the control after multiplexing and data message and ACK/NACK information and carry out channel interleaving, comprise: when RI information is transmitted in subframe, begin up to write the line number last_row_index at the RI information place that RI information and storage write at last from last column of channel interleaving memory matrix _RIWith column number last_column_index _RIAccording to line number and the column number at the RI information place that writes at last, skip the RI information that writes previously, write data and control information after multiplexing, wherein control information is front, and data message is rear; Transmit in this subframe when ACK/NACK information, write ACK/NACK information; According to the line number at the line number at the RI information place that writes at last and column number and/or the ACK/NACK information place that writes at last and the output function that column number carries out channel interleaving;

Scrambling apparatus is used for RI information, control and data message, ACK/NACK information after multiplexing are carried out scrambling.

9. channel interleaving according to claim 8 and scrambling system is characterized in that, described channel interleaving system comprises channel interleaving writing controller, channel interleaving memory and channel interleaving Read Controller, wherein

The channel interleaving writing controller, be used for to calculate the row, column number of the interleaver matrix that subframe takies at the channel interleaving memory, begin up to write the line number last_row_index at the RI information place that RI information and storage write at last from last column of channel interleaving memory matrix _RIWith column number last_column_index _RI, write data and control information after multiplexing according to the line number at the RI information place that writes at last and column number, write ACK/NACK information;

The channel interleaving memory is used for storage RI information, the data after multiplexing and control information, ACK/NACK information;

The channel interleaving Read Controller is used for receive channel interweave the row, column number of the interleaver matrix that subframe that writing controller calculates takies at the channel interleaving memory and all information of the storage in the delivery channel interleaver memory.

10. channel interleaving according to claim 9 and scrambling system is characterized in that, described channel interleaving memory comprises 12 quantum memories, 1 column information of each quantum memory storage interleaver matrix.

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